Neil Jones
6 years ago
9 changed files with 304 additions and 36 deletions
@ -0,0 +1,2 @@
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MODULE = board
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include $(RIOTBASE)/Makefile.base |
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# Put defined MCU peripherals here (in alphabetical order)
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FEATURES_PROVIDED += periph_timer
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FEATURES_PROVIDED += periph_uart
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# Various other features (if any)
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FEATURES_PROVIDED += cpp
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# The board MPU family (used for grouping by the CI system)
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FEATURES_MCU_GROUP = mips32r2
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@ -0,0 +1,4 @@
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export CPU = mips_pic32mx
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export CPU_MODEL=p32mx470f512h
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export INCLUDES += -I$(RIOTBOARD)/$(BOARD)/include/
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export APPDEPS += $(RIOTCPU)/$(CPU)/$(CPU_MODEL)/$(CPU_MODEL).S
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/*
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* Copyright(C) 2016,2017, Imagination Technologies Limited and/or its |
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* affiliated group companies. |
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* |
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* This file is subject to the terms and conditions of the GNU Lesser |
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* General Public License v2.1. See the file LICENSE in the top level |
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* directory for more details. |
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* |
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*/ |
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#include <stdio.h> |
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#include <stdint.h> |
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#include "periph/uart.h" |
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#include "bitarithm.h" |
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#include "board.h" |
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#include "periph_conf.h" |
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extern void dummy(void); |
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void board_init(void) |
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{ |
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/*
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* Setup pin mux for UART3 this is the one connected |
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* to the mickroBUS |
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*/ |
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U3RXREG = 0x2; /*connect pin RPF5 to UART3 RX*/ |
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RPF4R = 0x1; /*connect pin RPF4 to UART3 TX*/ |
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PORTFCLR = BIT5 | BIT4; /*set '0' on Porf F pins 4 and 5 */ |
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TRISFCLR = BIT4; /*set PortF pin 4 for output */ |
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TRISFSET = BIT5; /*set PortF pin 5 for input */ |
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ODCFCLR = BIT5 | BIT4; /*set PortF pin 4 and 5 as not open-drain */ |
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/* intialise UART used for debug (printf) */ |
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#ifdef DEBUG_VIA_UART |
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uart_init(DEBUG_VIA_UART, DEBUG_UART_BAUD, NULL, 0); |
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#endif |
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/* Stop the linker from throwing away the PIC32 config register settings */ |
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dummy(); |
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} |
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void pm_reboot(void) |
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{ |
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/* TODO, note this is needed to get 'default' example to build */ |
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} |
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@ -0,0 +1,59 @@
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/*
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* Copyright(C) 2016,2017, Imagination Technologies Limited and/or its |
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* affiliated group companies. |
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* |
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* This file is subject to the terms and conditions of the GNU Lesser |
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* General Public License v2.1. See the file LICENSE in the top level |
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* directory for more details. |
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* |
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*/ |
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/**
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* @defgroup boards_pic32-clicker MikroE PIC32 Clicker |
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* @ingroup boards |
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* @brief board configuration for the MikroE PIC32 Clicker |
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* @details |
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* see: |
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* http://www.mikroe.com/pic32/pic32mx-clicker/
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* For more information on the board. |
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* |
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* @{ |
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* |
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* @file |
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* @brief board configuration for the MikroE PIC32 Clicker |
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* |
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* @author Neil Jones <Neil.Jones@imgtec.com> |
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*/ |
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#ifndef _BOARD_H_ |
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#define _BOARD_H_ |
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#ifdef __cplusplus |
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extern "C" { |
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#endif |
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#include "vendor/p32mx470f512h.h" |
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/**
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* @brief Set how many increments of the count register per uS |
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* needed by the timer code. |
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*/ |
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#define TICKS_PER_US (48) |
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/**
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* @brief We are using an External Interrupt Controller (all pic32 devices use this mode) |
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*/ |
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#define EIC_IRQ (1) |
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/**
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* @brief Board level initialisation |
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*/ |
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void board_init(void); |
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#ifdef __cplusplus |
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} |
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#endif |
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#endif /* _BOARD_H_ */ |
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/** @} */ |
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@ -0,0 +1,65 @@
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/*
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* Copyright(C) 2016,2017, Imagination Technologies Limited and/or its |
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* affiliated group companies. |
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* |
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* This file is subject to the terms and conditions of the GNU Lesser |
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* General Public License v2.1. See the file LICENSE in the top level |
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* directory for more details. |
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* |
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*/ |
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/**
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* @defgroup boards_pic32-clicker MikroE PIC32 Clicker |
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* @ingroup boards |
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* @brief peripheral configuration for the MikroE PIC32 Clicker |
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* @{ |
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* |
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* @file |
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* @brief peripheral configuration for the MikroE PIC32 Clicker |
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* |
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* @author Neil Jones <Neil.Jones@imgtec.com> |
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*/ |
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#ifndef _PERIPH_CONF_H_ |
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#define _PERIPH_CONF_H_ |
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#ifdef __cplusplus |
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extern "C" { |
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#endif |
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/**
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* @brief The peripheral clock is required for the UART Baud rate calculation |
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* It is configured by the 'config' registers (see pic32_config_settings.c) |
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* Note 120MHz is the max F for this device. |
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*/ |
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#define PERIPHERAL_CLOCK (96000000) /* Hz */ |
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/**
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* @brief Timer definitions |
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* @{ |
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*/ |
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#define TIMER_NUMOF (1) |
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#define TIMER_0_CHANNELS (3) |
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/** @} */ |
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/**
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* @brief UART Definitions |
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* There are 4 UARTS available on this CPU. |
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* We route debug via UART3 on this board, |
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* this is the UART connected to the MikroBUS |
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* |
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* Note Microchip number the UARTS 1->4 |
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* @{ |
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*/ |
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#define UART_NUMOF (4) |
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#define DEBUG_VIA_UART (3) |
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#define DEBUG_UART_BAUD (9600) |
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/** @} */ |
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#ifdef __cplusplus |
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} |
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#endif |
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#endif |
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/** @} */ |
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@ -0,0 +1,117 @@
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/*
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* Copyright(C) 2016,2017, Imagination Technologies Limited and/or its |
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* affiliated group companies. |
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* |
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* This file is subject to the terms and conditions of the GNU Lesser |
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* General Public License v2.1. See the file LICENSE in the top level |
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* directory for more details. |
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* |
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*/ |
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#include <stdint.h> |
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#include "vendor/p32mx470f512h.h" |
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/*
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* DEVCFG3 @ 0x1FC02FF0 |
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* |
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* |
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* USERID |
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* FSRSSEL 7 Assign IPL 7 to a shadow register set. |
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* PMDLIWAY 1 |
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* IOL1WAY 1 |
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* FUSBIDIO OFF USB USBID Selection Controlled by Port Function |
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* FVBUSONIO ON VBUSON pin is controlled by the USB module function |
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*/ |
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volatile uint32_t _DEVCFG3 __attribute__((used, section(".devcfg3"))) = |
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0x0 /* unused bits must be 0 */ |
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| (_DEVCFG3_USERID_MASK & 0xFFFF << _DEVCFG3_USERID_POSITION) |
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| (_DEVCFG3_FSRSSEL_MASK & 7 << _DEVCFG3_FSRSSEL_POSITION) |
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| (_DEVCFG3_PMDL1WAY_MASK & 1 << _DEVCFG3_PMDL1WAY_POSITION) |
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| (_DEVCFG3_IOL1WAY_MASK & 1 << _DEVCFG3_IOL1WAY_POSITION) |
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| (_DEVCFG3_FUSBIDIO_MASK & 0 << _DEVCFG3_FUSBIDIO_POSITION) |
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| (_DEVCFG3_FVBUSONIO_MASK & 1 << _DEVCFG3_FVBUSONIO_POSITION); |
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/* Note this sets the PLL to 96MHz (8/2 * 24) which is only supported by 3xx
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* and 4xx parts and assumes an 8MHz XTAL. |
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* |
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* 1xx/2xx/53x/57x only support 50MHz (use 8/2 x 24 / 2 = 48Mhz) |
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* 5xx/6xx/7xx only support 80Mhz (use 8/2 * 20 = 80MHz). |
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* |
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* |
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* DEVCFG2 @ 0x1FC02FF4 ( |
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* |
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* FPLLIDIV DIV_2 System PLL Input Divider 2x Divider |
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* FPLLMUL 24x System PLL Multiplier PLL Multiply by 24, 8/2 x 24 = 96MHz |
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* UPLLIDIV DIV_12x USB PLL divider |
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* UPLLEN OFF USB PLL disabled |
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* FPLLODIV DIV_1 System PLL Output Clock Divider 1x Divider |
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*/ |
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volatile uint32_t _DEVCFG2 __attribute__ ((used, section(".devcfg2"))) = |
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0xffffffff /* unused bits must be 1 */ |
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& (~_DEVCFG2_FPLLIDIV_MASK | 1 << _DEVCFG2_FPLLIDIV_POSITION) |
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& (~_DEVCFG2_FPLLMUL_MASK | 7 << _DEVCFG2_FPLLMUL_POSITION) |
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& (~_DEVCFG2_UPLLIDIV_MASK | 7 << _DEVCFG2_UPLLIDIV_POSITION) |
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& (~_DEVCFG2_UPLLEN_MASK | 0 << _DEVCFG2_UPLLEN_POSITION) |
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& (~_DEVCFG2_FPLLODIV_MASK | 0 << _DEVCFG2_FPLLODIV_POSITION); |
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/*
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* DEVCFG1 @ 0x1FC02FF8 |
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* |
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* FNOSC PRIPLL Oscillator Selection Bits Primary Osc w/PLL (XT+,HS+,EC+PLL) |
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* FSOSCEN ON Secondary Oscillator Enable Enabled |
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* IESO ON Internal/External Switch Over Enabled |
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* OSCIOFNC OFF CLKO Output Signal Active on the OSCO Pin Disabled |
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* FPBDIV DIV_1 Peripheral Clock Divisor Pb_Clk is Sys_Clk/1 |
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* FCKSM CSDCMD Clock Switching and Monitor Selection Clock Switch Disable, FSCM Disabled |
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* WDTPS PS2 Watchdog Timer Postscaler 1:2 |
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* WINDIS OFF Watchdog Timer Window Enable Watchdog Timer is in Non-Window Mode |
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* FWDTEN OFF Watchdog Timer Enable WDT Disabled (SWDTEN Bit Controls) |
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* FWDTWINSZ 25% |
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*/ |
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volatile uint32_t _DEVCFG1 __attribute__ ((used, section(".devcfg1"))) = |
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0xffffffff /* unused bits must be 1 */ |
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& (~_DEVCFG1_FNOSC_MASK | 3 << _DEVCFG1_FNOSC_POSITION) |
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& (~_DEVCFG1_FSOSCEN_MASK | 1 << _DEVCFG1_FSOSCEN_POSITION) |
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& (~_DEVCFG1_IESO_MASK | 1 << _DEVCFG1_IESO_POSITION) |
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& (~_DEVCFG1_POSCMOD_MASK | 1 << _DEVCFG1_POSCMOD_POSITION) |
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& (~_DEVCFG1_OSCIOFNC_MASK | 1 << _DEVCFG1_OSCIOFNC_POSITION) |
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& (~_DEVCFG1_FPBDIV_MASK | 0 << _DEVCFG1_FPBDIV_POSITION) |
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& (~_DEVCFG1_FCKSM_MASK | 3 << _DEVCFG1_FCKSM_POSITION) |
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& (~_DEVCFG1_WDTPS_MASK | 1 << _DEVCFG1_WDTPS_POSITION) |
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& (~_DEVCFG1_WINDIS_MASK | 0 << _DEVCFG1_WINDIS_POSITION) |
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& (~_DEVCFG1_FWDTEN_MASK | 0 << _DEVCFG1_FWDTEN_POSITION) |
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& (~_DEVCFG1_FWDTWINSZ_MASK | 3 << _DEVCFG1_FWDTWINSZ_POSITION); |
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/*
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* DEVCFG0 @ 0x1FC02FFC |
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* |
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* DEBUG OFF Background Debugger Enable Debugger is disabled |
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* JTAGEN ON JTAG Enable JTAG Port Enabled |
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* ICESEL ICS_PGx1 CE/ICD Comm Channel Select Communicate on PGEC1/PGED1 |
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* PWP OFF Program Flash Write Protect Disable |
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* BWP OFF Boot Flash Write Protect bit Protection Disabled |
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* CP OFF Code Protect Protection Disabled |
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*/ |
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volatile uint32_t _DEVCFG0 __attribute__ ((used, section(".devcfg0"))) = |
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0x7fffffff /* unused bits must be 1 except MSB which is 0 for some odd reason */ |
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& (~_DEVCFG0_DEBUG_MASK | 3 << _DEVCFG0_DEBUG_POSITION) |
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& (~_DEVCFG0_JTAGEN_MASK | 1 << _DEVCFG0_JTAGEN_POSITION) |
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& (~_DEVCFG0_ICESEL_MASK | 3 << _DEVCFG0_ICESEL_POSITION) |
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& (~_DEVCFG0_PWP_MASK | 0xff << _DEVCFG0_PWP_POSITION) |
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& (~_DEVCFG0_BWP_MASK | 1 << _DEVCFG0_BWP_POSITION) |
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& (~_DEVCFG0_CP_MASK | 1 << _DEVCFG0_CP_POSITION); |
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/*
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* Without a reference to this function from elsewhere LD throws the whole |
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* compile unit away even though the data is 'volatile' and 'used' !!! |
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*/ |
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void dummy(void) |
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{ |
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(void)1; |
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} |
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