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at86rf2xx/915MHz fix

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dev/timer
bapclenet 8 years ago
parent 46a3e8ac83
commit dd8cc82da0
3 changed files with 11 additions and 20 deletions
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20
drivers/ng_at86rf2xx/include/ng_at86rf2xx_registers.h
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@ -259,22 +259,6 @@ extern "C" {
#define NG_AT86RF2XX_PHY_TX_PWR_DEFAULT__PA_BUF_LT (0xC0)
#define NG_AT86RF2XX_PHY_TX_PWR_DEFAULT__PA_LT (0x00)
#define NG_AT86RF2XX_PHY_TX_PWR_DEFAULT__TX_PWR (0x00)
#define NG_AT86RF2XX_PHY_TX_PWR_TX_PWR_VALUE__3dBm (0x00)
#define NG_AT86RF2XX_PHY_TX_PWR_TX_PWR_VALUE__2_8dBm (0x01)
#define NG_AT86RF2XX_PHY_TX_PWR_TX_PWR_VALUE__2_3dBm (0x02)
#define NG_AT86RF2XX_PHY_TX_PWR_TX_PWR_VALUE__1_8dBm (0x03)
#define NG_AT86RF2XX_PHY_TX_PWR_TX_PWR_VALUE__1_3dBm (0x04)
#define NG_AT86RF2XX_PHY_TX_PWR_TX_PWR_VALUE__0_7dBm (0x05)
#define NG_AT86RF2XX_PHY_TX_PWR_TX_PWR_VALUE__0dBm (0x06)
#define NG_AT86RF2XX_PHY_TX_PWR_TX_PWR_VALUE__m1dBm (0x07)
#define NG_AT86RF2XX_PHY_TX_PWR_TX_PWR_VALUE__m2dBm (0x08)
#define NG_AT86RF2XX_PHY_TX_PWR_TX_PWR_VALUE__m3dBm (0x09)
#define NG_AT86RF2XX_PHY_TX_PWR_TX_PWR_VALUE__m4dBm (0x0A)
#define NG_AT86RF2XX_PHY_TX_PWR_TX_PWR_VALUE__m5dBm (0x0B)
#define NG_AT86RF2XX_PHY_TX_PWR_TX_PWR_VALUE__m7dBm (0x0C)
#define NG_AT86RF2XX_PHY_TX_PWR_TX_PWR_VALUE__m9dBm (0x0D)
#define NG_AT86RF2XX_PHY_TX_PWR_TX_PWR_VALUE__m12dBm (0x0E)
#define NG_AT86RF2XX_PHY_TX_PWR_TX_PWR_VALUE__m17dBm (0x0F)
/** @} */
/**
@ -333,6 +317,10 @@ extern "C" {
#ifdef MODULE_NG_AT86RF212B
#define NG_AT86RF2XX_RF_CTRL_0_MASK__PA_LT (0xC0)
#define NG_AT86RF2XX_RF_CTRL_0_MASK__GC_TX_OFFS (0x03)
#define NG_AT86RF2XX_RF_CTRL_0_GC_TX_OFFS__0DB (0x01)
#define NG_AT86RF2XX_RF_CTRL_0_GC_TX_OFFS__1DB (0x02)
#define NG_AT86RF2XX_RF_CTRL_0_GC_TX_OFFS__2DB (0x03)
#endif
/** @} */

4
drivers/ng_at86rf2xx/ng_at86rf2xx.c
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@ -146,8 +146,8 @@ void ng_at86rf2xx_reset(ng_at86rf2xx_t *dev)
/* enable safe mode (protect RX FIFO until reading data starts) */
ng_at86rf2xx_reg_write(dev, NG_AT86RF2XX_REG__TRX_CTRL_2,
NG_AT86RF2XX_TRX_CTRL_2_MASK__RX_SAFE_MODE);
#ifdef MODULE_NG_AT86RF212
ng_at86rf2xx_set_freq(NG_AT86RF2XX_FREQ_915MHZ);
#ifdef MODULE_NG_AT86RF212B
ng_at86rf2xx_set_freq(dev,NG_AT86RF2XX_FREQ_915MHZ);
#endif
/* enable interrupts */
ng_at86rf2xx_reg_write(dev, NG_AT86RF2XX_REG__IRQ_MASK,

7
drivers/ng_at86rf2xx/ng_at86rf2xx_getset.c
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@ -139,13 +139,16 @@ void ng_at86rf2xx_set_freq(ng_at86rf2xx_t *dev, ng_at86rf2xx_freq_t freq)
uint8_t tmp1 = 0, tmp2 = 0;
tmp1 = ng_at86rf2xx_reg_read(dev, NG_AT86RF2XX_REG__TRX_CTRL_2);
tmp1 &= ~(NG_AT86RF2XX_TRX_CTRL_2_MASK__FREQ_MODE);
tmp2 = ng_at86rf2xx_reg_read(dev, NG_AT86RF2XX_REG__RF_CTRL_0);
/* Erase previous conf for GC_TX_OFFS */
tmp2 &= ~NG_AT86RF2XX_RF_CTRL_0_MASK__GC_TX_OFFS;
if (freq == NG_AT86RF2XX_FREQ_915MHZ) {
dev->freq = NG_AT86RF2XX_FREQ_915MHZ;
/* settings used by Linux 4.0rc at86rf212b driver - BPSK-40*/
tmp1 |= NG_AT86RF2XX_TRX_CTRL_2_MASK__SUB_MODE
| NG_AT86RF2XX_TRX_CTRL_2_MASK__OQPSK_SCRAM_EN;
tmp2 = 0x03;
tmp2 |= NG_AT86RF2XX_RF_CTRL_0_GC_TX_OFFS__2DB;
if (dev->chan == 0) {
ng_at86rf2xx_set_chan(dev,NG_AT86RF2XX_DEFAULT_CHANNEL);
@ -156,7 +159,7 @@ void ng_at86rf2xx_set_freq(ng_at86rf2xx_t *dev, ng_at86rf2xx_freq_t freq)
dev->freq = NG_AT86RF2XX_FREQ_868MHZ;
/* OQPSK-SIN-RC-100 IEEE802.15.4 for 868,3MHz */
tmp1 |= NG_AT86RF2XX_TRX_CTRL_2_MASK__BPSK_OQPSK;
tmp2 = 0x02;
tmp2 |= NG_AT86RF2XX_RF_CTRL_0_GC_TX_OFFS__1DB;
/* Channel = 0 for 868MHz means 868.3MHz, only one available */
ng_at86rf2xx_set_chan(dev,0x00);

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