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boards/nucleo32-l432: initial support

master
Alexandre Abadie 6 years ago
parent
commit
df02207ed7
  1. 3
      boards/nucleo32-l432/Makefile
  2. 1
      boards/nucleo32-l432/Makefile.dep
  3. 13
      boards/nucleo32-l432/Makefile.features
  4. 6
      boards/nucleo32-l432/Makefile.include
  5. 36
      boards/nucleo32-l432/board.c
  6. 7
      boards/nucleo32-l432/dist/openocd.cfg
  7. 33
      boards/nucleo32-l432/include/board.h
  8. 205
      boards/nucleo32-l432/include/periph_conf.h

3
boards/nucleo32-l432/Makefile

@ -0,0 +1,3 @@
MODULE = board
include $(RIOTBASE)/Makefile.base

1
boards/nucleo32-l432/Makefile.dep

@ -0,0 +1 @@
include $(RIOTBOARD)/nucleo-common/Makefile.dep

13
boards/nucleo32-l432/Makefile.features

@ -0,0 +1,13 @@
# Put defined MCU peripherals here (in alphabetical order)
FEATURES_PROVIDED += periph_cpuid
FEATURES_PROVIDED += periph_gpio
FEATURES_PROVIDED += periph_pwm
FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_uart
# load the common Makefile.features for Nucleo-32 boards
include $(RIOTBOARD)/nucleo32-common/Makefile.features
# The board MPU family (used for grouping by the CI system)
FEATURES_MCU_GROUP = cortex_m4_1

6
boards/nucleo32-l432/Makefile.include

@ -0,0 +1,6 @@
## the cpu to build for
export CPU = stm32l4
export CPU_MODEL = stm32l432kc
# load the common Makefile.include for Nucleo-32 boards
include $(RIOTBOARD)/nucleo32-common/Makefile.include

36
boards/nucleo32-l432/board.c

@ -0,0 +1,36 @@
/*
* Copyright (C) 2017 Inria
* 2017 OTA keys
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_nucleo32-l432
* @{
*
* @file
* @brief Board specific implementations for the nucleo32-l432 board
*
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
* @author Vincent Dupont <vincent@otakeys.com>
*
* @}
*/
#include "board.h"
#include "periph/gpio.h"
void board_init(void)
{
/* initialize the CPU */
cpu_init();
#ifdef AUTO_INIT_LED0
/* The LED pin is also used for SPI, so we enable it
only if explicitly wanted by the user */
gpio_init(LED0_PIN, GPIO_OUT);
#endif
}

7
boards/nucleo32-l432/dist/openocd.cfg vendored

@ -0,0 +1,7 @@
source [find interface/stlink-v2-1.cfg]
transport select hla_swd
source [find target/stm32l4x.cfg]
reset_config srst_only srst_nogate

33
boards/nucleo32-l432/include/board.h

@ -0,0 +1,33 @@
/*
* Copyright (C) 2017 Inria
* 2017 OTA keys
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @defgroup boards_nucleo32-l432 Nucleo32-L432
* @ingroup boards
* @brief Board specific files for the nucleo32-l432 board
* @{
*
* @file
* @brief Board specific definitions for the nucleo32-l432 board
*
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
* @author Vincent Dupont <vincent@otakeys.com>
*/
#ifndef BOARD_H
#define BOARD_H
#include "board_common.h"
#ifdef __cplusplus
extern "C" {}
#endif
#endif /* BOARD_H */
/** @} */

205
boards/nucleo32-l432/include/periph_conf.h

@ -0,0 +1,205 @@
/*
* Copyright (C) 2017 Inria
* 2017 OTA keys
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_nucleo32-l432
* @{
*
* @file
* @brief Peripheral MCU configuration for the nucleo32-l432 board
*
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
* @author Vincent Dupont <vincent@otakeys.com>
*/
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
#include "periph_cpu.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock system configuration
* @{
*/
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (0)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1)
/* give the target core clock (HCLK) frequency [in Hz], maximum: 80MHz */
#define CLOCK_CORECLOCK (80000000U)
/* PLL configuration: make sure your values are legit!
*
* compute by: CORECLOCK = (((PLL_IN / M) * N) / R)
* with:
* PLL_IN: input clock, HSE or MSI @ 48MHz
* M: pre-divider, allowed range: [1:8]
* N: multiplier, allowed range: [8:86]
* R: post-divider, allowed range: [2,4,6,8]
*
* Also the following constraints need to be met:
* (PLL_IN / M) -> [4MHz:16MHz]
* (PLL_IN / M) * N -> [64MHz:344MHz]
* CORECLOCK -> 80MHz MAX!
*/
#define CLOCK_PLL_M (6)
#define CLOCK_PLL_N (20)
#define CLOCK_PLL_R (2)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4
#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2
#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
/** @} */
/**
* @name Timer configuration
* @{
*/
static const timer_conf_t timer_config[] = {
{
.dev = TIM2,
.max = 0xffffffff,
.rcc_mask = RCC_APB1ENR1_TIM2EN,
.bus = APB1,
.irqn = TIM2_IRQn
}
};
#define TIMER_0_ISR isr_tim2
#define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
/** @} */
/**
* @name UART configuration
* @{
*/
static const uart_conf_t uart_config[] = {
{
.dev = USART2,
.rcc_mask = RCC_APB1ENR1_USART2EN,
.rx_pin = GPIO_PIN(PORT_A, 15),
.tx_pin = GPIO_PIN(PORT_A, 2),
.rx_af = GPIO_AF3,
.tx_af = GPIO_AF7,
.bus = APB1,
.irqn = USART2_IRQn
},
{
.dev = USART1,
.rcc_mask = RCC_APB2ENR_USART1EN,
.rx_pin = GPIO_PIN(PORT_A, 10),
.tx_pin = GPIO_PIN(PORT_A, 9),
.rx_af = GPIO_AF7,
.tx_af = GPIO_AF7,
.bus = APB2,
.irqn = USART1_IRQn
},
};
#define UART_0_ISR (isr_usart2)
#define UART_1_ISR (isr_usart1)
#define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
/** @} */
/**
* @name PWM configuration
* @{
*/
static const pwm_conf_t pwm_config[] = {
{
.dev = TIM1,
.rcc_mask = RCC_APB2ENR_TIM1EN,
.chan = { { .pin = GPIO_PIN(PORT_A, 8) /* D9 */, .cc_chan = 0 },
{ .pin = GPIO_UNDEF, .cc_chan = 0 },
{ .pin = GPIO_UNDEF, .cc_chan = 0 },
{ .pin = GPIO_UNDEF, .cc_chan = 0 } },
.af = GPIO_AF1,
.bus = APB2
}
};
#define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
/** @} */
/**
* @name SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 20000000Hz */
7, /* -> 78125Hz */
5, /* -> 312500Hz */
3, /* -> 1250000Hz */
1, /* -> 5000000Hz */
0 /* -> 10000000Hz */
},
{ /* for APB2 @ 40000000Hz */
7, /* -> 156250Hz */
6, /* -> 312500Hz */
4, /* -> 1250000Hz */
2, /* -> 5000000Hz */
1 /* -> 10000000Hz */
}
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,
.mosi_pin = GPIO_PIN(PORT_B, 5),
.miso_pin = GPIO_PIN(PORT_B, 4),
.sclk_pin = GPIO_PIN(PORT_B, 3),
.cs_pin = GPIO_UNDEF,
.af = GPIO_AF5,
.rccmask = RCC_APB2ENR_SPI1EN,
.apbbus = APB2
}
};
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
/**
* @name RTC configuration
* @{
*/
#define RTC_NUMOF (0U)
/** @} */
/**
* @name ADC configuration
* @{
*/
#define ADC_NUMOF (0U)
/** @} */
/**
* @name DAC configuration
* @{
*/
#define DAC_NUMOF (0U)
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* PERIPH_CONF_H */
/** @} */
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