Merge pull request #3779 from haukepetersen/add_lpc2387_timer
cpu/lpc2387: added periph timer implementationdev/timer
Hauke Petersen
8 years ago
commit
ea4fb69f9d
@ -1,4 +1,5 @@
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FEATURES_PROVIDED += periph_gpio
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FEATURES_PROVIDED += periph_rtc
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FEATURES_PROVIDED += periph_spi
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FEATURES_PROVIDED += periph_timer
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FEATURES_MCU_GROUP = arm7
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@ -1,51 +0,0 @@
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/*
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* Copyright (C) 2014 INRIA
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup msba2
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* @{
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*/
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/**
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* @file
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* @brief msba2 benchmark functions
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*
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* @author Heiko Will <heiko.will@fu-berlin.de>
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* @author Zakaria Kasmi <zkasmi@inf.fu-berlin.de>
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* @author Kaspar Schleiser <kaspar@schleiser.de>
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*
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*/
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#include <stdint.h>
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#include <stdio.h>
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#include "lpc2387.h"
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void benchmark_init(void)
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{
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PCLKSEL1 = (PCLKSEL1 & ~(BIT14|BIT15)) | (1 << 14); // CCLK to PCLK divider
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PCONP |= PCTIM3;
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T3TCR = 0; // disable timer
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T3MCR = 0; // disable interrupt
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T3CCR = 0; // capture is disabled.
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T3EMR = 0; // no external match output.
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T3PR = 0; // set prescaler
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T3TC = 0; // reset counter
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}
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void benchmark_reset_start(void)
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{
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T3TCR = 0; // disable timer
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T3TC = 0; // reset counter
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T3TCR = BIT0;
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}
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unsigned int benchmark_read_stop(void)
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{
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T3TCR = 0; // disable timer
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return T3TC;
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}
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@ -1,4 +1,5 @@
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FEATURES_PROVIDED += periph_gpio
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FEATURES_PROVIDED += periph_rtc
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FEATURES_PROVIDED += periph_spi
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FEATURES_PROVIDED += periph_timer
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FEATURES_MCU_GROUP = arm7
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@ -1,206 +0,0 @@
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/*
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* Copyright (C) 2014 INRIA
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu
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* @file
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* @internal
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* @brief ARM kernel timer CPU dependent functions implementation
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*
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* @author Thomas Hillebrandt <hillebra@inf.fu-berlin.de>
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* @author Heiko Will <hwill@inf.fu-berlin.de>
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* @author Oliver Hahm <oliver.hahm@inria.fr>
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*
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*/
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#include "cpu.h"
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#include "bitarithm.h"
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#include "hwtimer_cpu.h"
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#include "arch/hwtimer_arch.h"
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#include "irq.h"
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#define VULP(x) ((volatile unsigned long*) (x))
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/* High level interrupt handler */
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static void (*int_handler)(int);
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/* Timer 0-3 interrupt handler */
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static void timer_irq(void) __attribute__((interrupt("IRQ")));
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inline static unsigned long get_base_address(short timer)
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{
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return (volatile unsigned long)(TMR0_BASE_ADDR + (timer / 8) * 0x6C000 + (timer / 4 - (timer / 8) * 2) * 0x4000);
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}
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static void timer_irq(void)
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{
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short timer = 0;
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if (T0IR) {
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timer = 0;
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}
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else if (T1IR) {
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timer = 4;
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}
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else if (T2IR) {
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timer = 8;
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}
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volatile unsigned long base = get_base_address(timer);
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if (*VULP(base + TXIR) & BIT0) {
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*VULP(base + TXMCR) &= ~BIT0;
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*VULP(base + TXIR) = BIT0;
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int_handler(timer);
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}
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if (*VULP(base + TXIR) & BIT1) {
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*VULP(base + TXMCR) &= ~BIT3;
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*VULP(base + TXIR) = BIT1;
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int_handler(timer + 1);
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}
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if (*VULP(base + TXIR) & BIT2) {
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*VULP(base + TXMCR) &= ~BIT6;
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*VULP(base + TXIR) = BIT2;
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int_handler(timer + 2);
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}
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if (*VULP(base + TXIR) & BIT3) {
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*VULP(base + TXMCR) &= ~BIT9;
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*VULP(base + TXIR) = BIT3;
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int_handler(timer + 3);
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}
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VICVectAddr = 0; /* acknowledge interrupt (if using VIC IRQ) */
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}
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static void timer0_init(uint32_t cpsr)
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{
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PCONP |= PCTIM0; /* power up timer */
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T0TCR = 2; /* disable and reset timer */
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T0MCR = 0; /* disable compare */
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T0CCR = 0; /* capture is disabled */
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T0EMR = 0; /* no external match output */
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T0PR = cpsr; /* set prescaler */
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install_irq(TIMER0_INT, &timer_irq, 1);
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T0TCR = 1; /* reset counter */
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}
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static void timer1_init(uint32_t cpsr)
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{
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PCONP |= PCTIM1; /* power up timer */
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T1TCR = 2; /* disable and reset timer */
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T1MCR = 0; /* disable compare */
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T1CCR = 0; /* capture is disabled */
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T1EMR = 0; /* no external match output */
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T1PR = cpsr; /* set prescaler */
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install_irq(TIMER1_INT, &timer_irq, 1);
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T1TCR = 1; /* reset counter */
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}
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static void timer2_init(uint32_t cpsr)
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{
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PCONP |= PCTIM2; /* power up timer */
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T2TCR = 2; /* disable and reset timer */
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T2MCR = 0; /* disable compare */
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T2CCR = 0; /* capture is disabled */
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T2EMR = 0; /* no external match output */
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T2PR = cpsr; /* set prescaler */
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install_irq(TIMER2_INT, &timer_irq, 1);
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T2TCR = 1; /* reset counter */
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}
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void hwtimer_arch_init(void (*handler)(int), uint32_t fcpu)
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{
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uint32_t cpsr;
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int_handler = handler;
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cpu_clock_scale(fcpu, HWTIMER_SPEED, &cpsr);
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timer0_init(cpsr);
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timer1_init(cpsr);
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timer2_init(cpsr);
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}
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/*---------------------------------------------------------------------------*/
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void hwtimer_arch_enable_interrupt(void)
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{
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VICIntEnable = 1 << TIMER0_INT; /* Enable Interrupt */
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VICIntEnable = 1 << TIMER1_INT; /* Enable Interrupt */
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VICIntEnable = 1 << TIMER2_INT; /* Enable Interrupt */
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}
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/*---------------------------------------------------------------------------*/
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void hwtimer_arch_disable_interrupt(void)
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{
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VICIntEnClr = 1 << TIMER0_INT; /* Disable Interrupt */
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VICIntEnClr = 1 << TIMER1_INT; /* Disable Interrupt */
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VICIntEnClr = 1 << TIMER2_INT; /* Disable Interrupt */
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}
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/*---------------------------------------------------------------------------*/
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void hwtimer_arch_set(unsigned long offset, short timer)
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{
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/* Calculate base address of timer register */
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/* Timer 0-3 are matched to TIMER0 */
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/* Timer 4-7 are matched to TIMER1 */
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/* Timer 8-11 are matched to TIMER2 */
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volatile unsigned long base = get_base_address(timer);
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/* Calculate match register address of corresponding timer */
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timer %= 4;
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unsigned long cpsr = disableIRQ();
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volatile unsigned long *addr = VULP(base + TXMR0 + 4 * timer);
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/* Calculate match register value */
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unsigned long value = *VULP(base + TXTC) + offset;
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*addr = value; /* set match register */
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*VULP(base + TXIR) = 0x01 << timer; /* reset interrupt register value for corresponding match register */
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*VULP(base + TXMCR) &= ~(7 << (3 * timer)); /* Clear all bits */
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*VULP(base + TXMCR) |= (MR0I << (3 * timer)); /* enable interrupt for match register */
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restoreIRQ(cpsr);
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}
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void hwtimer_arch_set_absolute(unsigned long value, short timer)
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{
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/* Calculate base address of timer register */
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/* Timer 0-3 are matched to TIMER0 */
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/* Timer 4-7 are matched to TIMER1 */
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/* Timer 8-11 are matched to TIMER2 */
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volatile unsigned long base = get_base_address(timer);
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/* Calculate match register address of corresponding timer */
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timer %= 4;
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volatile unsigned long *addr = VULP(base + TXMR0 + 4 * timer);
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/* Calculate match register value */
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*addr = value; /* set match register */
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*VULP(base + TXIR) = 0x01 << timer; /* reset interrupt register value for corresponding match register */
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*VULP(base + TXMCR) &= ~(7 << (3 * timer)); /* Clear all bits */
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*VULP(base + TXMCR) |= (MR0I << (3 * timer)); /* enable interrupt for match register */
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}
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/*---------------------------------------------------------------------------*/
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void hwtimer_arch_unset(short timer)
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{
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volatile unsigned long base = get_base_address(timer);
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timer %= 4;
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*VULP(base + TXMCR) &= ~(MR0I << (3 * timer)); /* disable interrupt for match register */
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*VULP(base + TXIR) = 0x01 << timer; /* reset interrupt register value for corresponding match register */
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}
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/*---------------------------------------------------------------------------*/
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unsigned long hwtimer_arch_now(void)
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{
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return T0TC;
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}
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void hwtimer_arch_setcounter(unsigned int val)
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{
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T0TC = val;
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}
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@ -0,0 +1,232 @@
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/*
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* Copyright (C) 2015 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup cpu_lpc2387
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* @{
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*
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* @file
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* @brief Implementation of the low-level timer driver for the LPC2387
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @}
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*/
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#include <stdint.h>
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#include <string.h>
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#include "periph_conf.h"
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#include "periph_cpu.h"
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#include "periph/timer.h"
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/**
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* @brief Check the board config to make sure we do not exceed max number of
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* timers
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*/
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#if TIMER_NUMOF > 3
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#error "ERROR in timer configuration: too many timers defined"
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#endif
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/**
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* @brief Interrupt context information for configured timers
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*/
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static timer_isr_ctx_t isr_ctx[TIMER_NUMOF];
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/**
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* @brief Forward declarations for interrupt functions
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* @{
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*/
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void tim_isr_0(void);
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void tim_isr_1(void);
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void tim_isr_2(void);
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void tim_isr_3(void);
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/** @} */
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/**
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* @brief Get the base pointer of a timer
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*/
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static inline lpc23xx_timer_t *get_dev(tim_t tim)
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{
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switch (tim) {
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case 0:
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return TMR0;
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#if TIMER_NUMOF > 1
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case 1:
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return TMR1;
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#endif
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#if TIMER_NUMOF > 2
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case 2:
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return TMR2;
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#endif
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#if TIMER_NUMOF > 3
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case 3:
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return TMR3;
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#endif
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default:
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return NULL;
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}
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}
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static inline void pwr_clk_and_isr(tim_t tim)
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{
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switch (tim) {
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case 0:
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PCONP |= (1 << 1);
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PCLKSEL0 &= ~(0x03 << 2);
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PCLKSEL0 |= (0x01 << 2);
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install_irq(TIMER0_INT, &tim_isr_0, 1);
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break;
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#if TIMER_NUMOF > 1
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case 1:
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PCONP |= (1 << 2);
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PCLKSEL0 &= ~(0x03 << 4);
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PCLKSEL0 |= (0x01 << 4);
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install_irq(TIMER1_INT, &tim_isr_1, 1);
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break;
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#endif
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#if TIMER_NUMOF > 2
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case 2:
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PCONP |= (1 << 22);
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PCLKSEL1 &= ~(0x03 << 12);
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PCLKSEL1 |= (0x01 << 12);
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install_irq(TIMER2_INT, &tim_isr_2, 1);
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break;
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#endif
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#if TIMER_NUMOF > 3
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case 3:
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PCONP |= (1 << 23);
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PCLKSEL1 &= ~(0x03 << 14);
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PCLKSEL1 |= (0x01 << 14);
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install_irq(TIMER3_INT, &tim_isr_3, 1);
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break;
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#endif
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}
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}
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int timer_init(tim_t tim, unsigned int us_per_tick, void (*callback)(int))
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{
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/* get the timers base register */
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lpc23xx_timer_t *dev = get_dev(tim);
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/* make sure the timer device is valid */
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if (dev == NULL) {
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return -1;
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}
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/* save the callback */
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isr_ctx[tim].cb = callback;
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/* enable power, config periph clock and install ISR vector */
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pwr_clk_and_isr(tim);
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/* reset timer configuration (sets the timer to timer mode) */
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dev->TCR = 0;
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dev->CTCR = 0;
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/* configure the prescaler */
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dev->PR = (us_per_tick * ((CLOCK_PCLK / 1000000) - 1));
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/* enable timer */
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dev->TCR = 1;
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return 0;
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}
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int timer_set(tim_t tim, int channel, unsigned int timeout)
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{
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unsigned int now = timer_read(tim);
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return timer_set_absolute(tim, channel, (timeout + now));
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}
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int timer_set_absolute(tim_t tim, int channel, unsigned int value)
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{
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if (tim >= TIMER_NUMOF || channel >= TIMER_CHAN_NUMOF) {
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return -1;
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}
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lpc23xx_timer_t *dev = get_dev(tim);
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dev->MR[channel] = value;
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dev->MCR |= (1 << (channel * 3));
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return 0;
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}
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int timer_clear(tim_t tim, int channel)
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{
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if (tim >= TIMER_NUMOF || channel >= TIMER_CHAN_NUMOF) {
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return -1;
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}
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get_dev(tim)->MCR &= ~(1 << (channel * 3));
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return 0;
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}
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unsigned int timer_read(tim_t tim)
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{
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return (unsigned int)(get_dev(tim)->TC);
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}
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void timer_start(tim_t tim)
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{
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get_dev(tim)->TCR = 1;
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}
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void timer_stop(tim_t tim)
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{
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get_dev(tim)->TCR = 0;
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}
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void timer_reset(tim_t tim)
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{
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lpc23xx_timer_t *dev = get_dev(tim);
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dev->TCR |= 2;
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asm("nop");
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dev->TCR &= ~(2);
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}
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void timer_irq_enable(tim_t tim)
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{
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/* TODO */
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}
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void timer_irq_disable(tim_t tim)
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{
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/* TODO */
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}
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static inline void isr_handler(lpc23xx_timer_t *dev, int tim_num)
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{
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for (int i = 0; i < TIMER_CHAN_NUMOF; i++) {
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if (dev->IR & (1 << i)) {
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dev->IR |= (1 << i);
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dev->MCR &= ~(1 << (i * 3));
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isr_ctx[tim_num].cb(i);
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}
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}
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/* we must not forget to acknowledge the handling of the interrupt */
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VICVectAddr = 0;
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}
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void __attribute__((interrupt("IRQ"))) tim_isr_0(void)
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{
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isr_handler(TMR0, 0);
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}
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#if TIMER_NUMOF > 1
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void __attribute__((interrupt("IRQ"))) tim_isr_1(void)
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{
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isr_handler(TMR1, 1);
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}
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#endif
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#if TIMER_NUMOF > 2
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void __attribute__((interrupt("IRQ"))) tim_isr_2(void)
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{
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isr_handler(TMR2, 2);
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}
|
||||
#endif
|
||||
|
||||
#if TIMER_NUMOF > 3
|
||||
void __attribute__((interrupt("IRQ"))) tim_isr_3(void)
|
||||
{
|
||||
isr_handler(TMR3, 3);
|
||||
}
|
||||
#endif
|
||||
Loading…
Reference in New Issue