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cpu/atmega_common: adapted SPI driver

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pr/spi.typo
Hauke Petersen 7 years ago
parent a25b25d830
commit f5595693f6
2 changed files with 67 additions and 92 deletions
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38
cpu/atmega_common/include/periph_cpu_common.h
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@ -32,6 +32,16 @@ extern "C" {
*/
#define GPIO_PIN(x, y) ((x << 4) | y)
/**
* @brief Use some common SPI functions
* @{
*/
#define PERIPH_SPI_NEEDS_INIT_CS
#define PERIPH_SPI_NEEDS_TRANSFER_BYTE
#define PERIPH_SPI_NEEDS_TRANSFER_REG
#define PERIPH_SPI_NEEDS_TRANSFER_REGS
/** @} */
/**
* @brief SPI mode select macro
*
@ -47,13 +57,13 @@ extern "C" {
* correct configuration there
* @{
*/
#define HAVE_SPI_CONF_T
#define HAVE_SPI_MODE_T
typedef enum {
SPI_CONF_FIRST_RISING = SPI_MODE_SEL(0, 0), /**< mode 0 */
SPI_CONF_SECOND_RISING = SPI_MODE_SEL(0, 1), /**< mode 1 */
SPI_CONF_FIRST_FALLING = SPI_MODE_SEL(1, 0), /**< mode 2 */
SPI_CONF_SECOND_FALLING = SPI_MODE_SEL(1, 1) /**< mode 3 */
} spi_conf_t;
SPI_MODE_0 = SPI_MODE_SEL(0, 0), /**< mode 0 */
SPI_MODE_1 = SPI_MODE_SEL(0, 1), /**< mode 1 */
SPI_MODE_2 = SPI_MODE_SEL(1, 0), /**< mode 2 */
SPI_MODE_3 = SPI_MODE_SEL(1, 1) /**< mode 3 */
} spi_mode_t;
/** @} */
/**
@ -62,7 +72,7 @@ typedef enum {
* We encode the speed in bits 2, 1, and 0, where bit0 and bit1 hold the SPCR
* prescaler bits, while bit2 holds the SPI2X bit.
*/
#define SPI_SPEED_SEL(s2x, pr1, pr0) ((s2x << 2) | (pr1 << 1) | pr0)
#define SPI_CLK_SEL(s2x, pr1, pr0) ((s2x << 2) | (pr1 << 1) | pr0)
/**
* @brief Override SPI speed values
@ -70,14 +80,14 @@ typedef enum {
* We assume a master clock speed of 16MHz here.
* @{
*/
#define HAVE_SPI_SPEED_T
#define HAVE_SPI_CLK_T
typedef enum {
SPI_SPEED_100KHZ = SPI_SPEED_SEL(0, 1, 1), /**< 16/128 -> 125KHz */
SPI_SPEED_400KHZ = SPI_SPEED_SEL(1, 1, 0), /**< 16/32 -> 500KHz */
SPI_SPEED_1MHZ = SPI_SPEED_SEL(0, 0, 1), /**< 16/16 -> 1MHz */
SPI_SPEED_5MHZ = SPI_SPEED_SEL(0, 0, 0), /**< 16/4 -> 4MHz */
SPI_SPEED_10MHZ = SPI_SPEED_SEL(1, 0, 0) /**< 16/2 -> 8MHz */
} spi_speed_t;
SPI_CLK_100KHZ = SPI_CLK_SEL(0, 1, 1), /**< 16/128 -> 125KHz */
SPI_CLK_400KHZ = SPI_CLK_SEL(1, 1, 0), /**< 16/32 -> 500KHz */
SPI_CLK_1MHZ = SPI_CLK_SEL(0, 0, 1), /**< 16/16 -> 1MHz */
SPI_CLK_5MHZ = SPI_CLK_SEL(0, 0, 0), /**< 16/4 -> 4MHz */
SPI_CLK_10MHZ = SPI_CLK_SEL(1, 0, 0) /**< 16/2 -> 8MHz */
} spi_clk_t;
/** @} */
#ifdef __cplusplus

121
cpu/atmega_common/periph/spi.c
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@ -22,31 +22,30 @@
#include "cpu.h"
#include "mutex.h"
#include "assert.h"
#include "periph/spi.h"
#define ENABLE_DEBUG (0)
#include "debug.h"
/* guard this file in case no SPI device is defined */
#if SPI_NUMOF
/**
* @brief Extract BR0, BR1 and SPI2X bits from speed value
* @{
*/
#define SPEED_MASK (0x3)
#define CLK_MASK (0x3)
#define S2X_SHIFT (2)
/** @} */
static mutex_t lock = MUTEX_INIT;
int spi_init_master(spi_t dev, spi_conf_t conf, spi_speed_t speed)
void spi_init(spi_t bus)
{
assert(bus == 0);
/* power off the SPI peripheral */
MEGA_PRR |= (1 << PRSPI);
/* trigger the pin configuration */
spi_init_pins(bus);;
}
void spi_init_pins(spi_t bus)
{
DEBUG("spi.c: conf = %d, speed = %d\n", conf, speed);
/* make sure device is valid (there is only one...) */
if (dev != 0) {
return -1;
}
/* the pin configuration for this CPU is fixed:
* - PB3: MISO (configure as input - done automatically)
@ -59,93 +58,59 @@ int spi_init_master(spi_t dev, spi_conf_t conf, spi_speed_t speed)
* select externally for now)
*/
DDRB |= ((1 << DDB2) | (1 << DDB1) | (1 << DDB0));
}
int spi_acquire(spi_t bus, spi_cs_t cs, spi_mode_t mode, spi_clk_t clk)
{
(void)cs;
/* make sure the SPI is not powered off */
/* lock the bus and power on the SPI peripheral */
mutex_lock(&lock);
MEGA_PRR &= ~(1 << PRSPI);
/* configure as master, with given mode and clock */
SPSR = (speed >> S2X_SHIFT);
SPCR = ((1 << SPE) | (1 << MSTR) | conf | (speed & SPEED_MASK));
SPSR = (clk >> S2X_SHIFT);
SPCR = ((1 << SPE) | (1 << MSTR) | mode | (clk & CLK_MASK));
SPCR |= (1 << SPE);
/* clear interrupt flag by reading SPSR */
/* clear interrupt flag by reading SPSR and data register by reading SPDR */
(void)SPSR;
/* clear data register */
(void)SPDR;
return 0;
}
int spi_acquire(spi_t dev)
{
mutex_lock(&lock);
return 0;
return SPI_OK;
}
int spi_release(spi_t dev)
void spi_release(spi_t bus)
{
/* power off and release the bus */
SPCR &= ~(1 << SPE);
MEGA_PRR |= (1 << PRSPI);
mutex_unlock(&lock);
return 0;
}
int spi_init_slave(spi_t dev, spi_conf_t conf, char (*cb)(char data))
{
(void) dev;
(void) conf;
(void) cb;
/* not implemented */
return -1;
}
void spi_transmission_begin(spi_t dev, char reset_val)
void spi_transfer_bytes(spi_t bus, spi_cs_t cs, bool cont,
const void *out, void *in, size_t len)
{
(void)dev;
(void)reset_val;
uint8_t *out_buf = (uint8_t *)out;
uint8_t *in_buf = (uint8_t *)in;
/* not implemented */
}
assert(out_buf || in_buf);
int spi_transfer_byte(spi_t dev, char out, char *in)
{
return spi_transfer_bytes(dev, &out, in, 1);
}
if (cs != SPI_CS_UNDEF) {
gpio_clear((gpio_t)cs);
}
int spi_transfer_bytes(spi_t dev, char *out, char *in, unsigned int length)
{
for (unsigned int i = 0; i < length; i++) {
char tmp = (out) ? out[i] : 0;
for (size_t i = 0; i < len; i++) {
uint8_t tmp = (out_buf) ? out_buf[i] : 0;
SPDR = tmp;
while (!(SPSR & (1 << SPIF))) {}
tmp = SPDR;
if (in) {
in[i] = tmp;
if (in_buf) {
in_buf[i] = tmp;
}
}
return (int)length;
}
int spi_transfer_reg(spi_t dev, uint8_t reg, char out, char *in)
{
spi_transfer_bytes(dev, (char *)&reg, NULL, 1);
return spi_transfer_bytes(dev, &out, in, 1);
}
int spi_transfer_regs(spi_t dev, uint8_t reg, char *out, char *in, unsigned int length)
{
spi_transfer_bytes(dev, (char *)&reg, NULL, 1);
return spi_transfer_bytes(dev, out, in, length);
}
void spi_poweron(spi_t dev)
{
SPCR |= (1 << SPE);
}
void spi_poweroff(spi_t dev)
{
SPCR &= ~(1 << SPE);
if ((!cont) && (cs != SPI_CS_UNDEF)) {
gpio_set((gpio_t)cs);
}
}
#endif /* SPI_NUMOF */

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