boards/nucleo32-l031: initial support
Alexandre Abadie
6 years ago
parent
bf45254a8d
commit
fb7fe334b6
@ -0,0 +1,3 @@
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MODULE = board
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include $(RIOTBASE)/Makefile.base
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@ -0,0 +1,3 @@
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ifneq (,$(filter saul_default,$(USEMODULE)))
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USEMODULE += saul_gpio
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endif
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@ -0,0 +1,12 @@
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# Put defined MCU peripherals here (in alphabetical order)
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FEATURES_PROVIDED += periph_cpuid
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FEATURES_PROVIDED += periph_gpio
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FEATURES_PROVIDED += periph_pwm
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FEATURES_PROVIDED += periph_timer
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FEATURES_PROVIDED += periph_uart
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# Various common features of Nucleo boards
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FEATURES_PROVIDED += cpp
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# The board MPU family (used for grouping by the CI system)
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FEATURES_MCU_GROUP = cortex_m0_1
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@ -0,0 +1,13 @@
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## the cpu to build for
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export CPU = stm32l0
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export CPU_MODEL = stm32l031k6
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# define the default port depending on the host OS
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PORT_LINUX ?= /dev/ttyACM0
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PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.usbmodem*)))
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# setup serial terminal
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include $(RIOTBOARD)/Makefile.include.serial
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# this board uses openocd
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include $(RIOTBOARD)/Makefile.include.openocd
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@ -0,0 +1,34 @@
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/*
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* Copyright (C) 2017 Freie Universität Berlin
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* 2017 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_nucleo32-l031
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* @{
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*
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* @file
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* @brief Board specific implementations for the nucleo32-l031 board
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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*
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* @}
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*/
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#include "board.h"
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#include "periph/gpio.h"
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void board_init(void)
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{
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/* initialize the boards LED */
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gpio_init(LED0_PIN, GPIO_OUT);
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/* initialize the CPU */
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cpu_init();
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}
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@ -0,0 +1,7 @@
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source [find interface/stlink-v2-1.cfg]
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transport select hla_swd
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source [find target/stm32l0.cfg]
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reset_config srst_only
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@ -0,0 +1,64 @@
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/*
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* Copyright (C) 2017 Freie Universität Berlin
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* 2017 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @defgroup boards_nucleo32-l031 Nucleo32-L031
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* @ingroup boards
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* @brief Board specific files for the nucleo32-l031 board
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* @{
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*
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* @file
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* @brief Board specific definitions for the nucleo32-l031 board
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Alexandre Aabdie <alexandre.abadie@inria.fr>
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*/
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#ifndef BOARD_H
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#define BOARD_H
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name xtimer configuration
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* @{
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*/
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#define XTIMER_DEV TIMER_DEV(0)
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#define XTIMER_CHAN (0)
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#define XTIMER_WIDTH (16)
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/** @} */
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/**
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* @name Macros for controlling the on-board LED.
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* @{
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*/
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#define LED0_PIN GPIO_PIN(PORT_B, 3)
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#define LED0_MASK (1 << 3)
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#define LED0_ON (GPIOB->BSRR = LED0_MASK)
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#define LED0_OFF (GPIOB->BRR = LED0_MASK)
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#define LED0_TOGGLE (GPIOB->ODR ^= LED0_MASK)
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/** @} */
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/**
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* @brief Initialize board specific hardware, including clock, LEDs and std-IO
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*/
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void board_init(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* BOARD_H */
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/** @} */
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@ -0,0 +1,48 @@
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/*
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* Copyright (C) 2017 Inria
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* 2017 OTA keys
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_nucleo32-l031
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* @{
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*
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* @file
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* @brief Board specific configuration of direct mapped GPIOs
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*
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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* @author Vincent Dupont <vincent@otakeys.com>
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*/
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#ifndef GPIO_PARAMS_H
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#define GPIO_PARAMS_H
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#include "board.h"
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#include "saul/periph.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief GPIO pin configuration
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*/
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static const saul_gpio_params_t saul_gpio_params[] =
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{
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{
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.name = "LED(green)",
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.pin = LED0_PIN,
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.mode = GPIO_OUT
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},
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};
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#ifdef __cplusplus
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}
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#endif
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#endif /* GPIO_PARAMS_H */
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/** @} */
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@ -0,0 +1,179 @@
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/*
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* Copyright (C) 2017 Freie Universität Berlin
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* 2017 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_nucleo32-l031
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* @{
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*
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* @file
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* @brief Peripheral MCU configuration for the nucleo32-l031 board
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Alexandre Aabdie <alexandre.abadie@inria.fr>
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*/
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#ifndef PERIPH_CONF_H
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#define PERIPH_CONF_H
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#include "periph_cpu.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Clock system configuration
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* @{
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*/
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#define CLOCK_HSI (16000000U) /* internal oscillator */
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#define CLOCK_CORECLOCK (32000000U) /* desired core clock frequency */
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/* configuration of PLL prescaler and multiply values */
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/* CORECLOCK := HSI / CLOCK_PLL_DIV * CLOCK_PLL_MUL */
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#define CLOCK_PLL_DIV RCC_CFGR_PLLDIV2
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#define CLOCK_PLL_MUL RCC_CFGR_PLLMUL4
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/* configuration of peripheral bus clock prescalers */
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* AHB clock -> 32MHz */
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* APB2 clock -> 32MHz */
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV1 /* APB1 clock -> 32MHz */
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/* configuration of flash access cycles */
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#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY
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/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
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#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
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/** @} */
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/**
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* @brief Timer configuration
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* @{
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*/
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static const timer_conf_t timer_config[] = {
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{
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.dev = TIM2,
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.max = 0x0000ffff,
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.rcc_mask = RCC_APB1ENR_TIM2EN,
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.bus = APB1,
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.irqn = TIM2_IRQn
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}
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};
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#define TIMER_0_ISR isr_tim2
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#define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
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/** @} */
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/**
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* @brief UART configuration
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* @{
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*/
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static const uart_conf_t uart_config[] = {
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{
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.dev = USART2,
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.rcc_mask = RCC_APB1ENR_USART2EN,
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.rx_pin = GPIO_PIN(PORT_A, 15),
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.tx_pin = GPIO_PIN(PORT_A, 2),
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.rx_af = GPIO_AF4,
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.tx_af = GPIO_AF4,
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.bus = APB1,
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.irqn = USART2_IRQn
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}
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};
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#define UART_0_ISR (isr_usart2)
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#define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
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/** @} */
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/**
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* @brief PWM configuration
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* @{
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*/
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static const pwm_conf_t pwm_config[] = {
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{
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.dev = TIM21,
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.rcc_mask = RCC_APB2ENR_TIM21EN,
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.chan = { { .pin = GPIO_PIN(PORT_B, 6) /* D5 */, .cc_chan = 0 },
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{ .pin = GPIO_UNDEF, .cc_chan = 0 },
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{ .pin = GPIO_UNDEF, .cc_chan = 0 },
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{ .pin = GPIO_UNDEF, .cc_chan = 0 } },
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.af = GPIO_AF5,
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.bus = APB2
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}
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};
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#define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
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/** @} */
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/**
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* @name SPI configuration
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* @{
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*/
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static const uint8_t spi_divtable[2][5] = {
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{ /* for APB1 @ 32000000Hz */
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7, /* -> 125000Hz */
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5, /* -> 500000Hz */
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4, /* -> 1000000Hz */
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2, /* -> 4000000Hz */
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1 /* -> 8000000Hz */
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},
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{ /* for APB2 @ 32000000Hz */
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7, /* -> 125000Hz */
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5, /* -> 500000Hz */
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4, /* -> 1000000Hz */
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2, /* -> 4000000Hz */
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1 /* -> 8000000Hz */
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}
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};
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static const spi_conf_t spi_config[] = {
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{
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.dev = SPI1,
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.mosi_pin = GPIO_PIN(PORT_B, 5),
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.miso_pin = GPIO_PIN(PORT_B, 4),
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.sclk_pin = GPIO_PIN(PORT_B, 3),
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.cs_pin = GPIO_UNDEF,
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.af = GPIO_AF0,
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.rccmask = RCC_APB2ENR_SPI1EN,
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.apbbus = APB2
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}
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};
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#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
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/** @} */
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/**
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* @brief ADC configuration
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* @{
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*/
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#define ADC_NUMOF (0)
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/** @} */
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/**
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* @brief DAC configuration
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* @{
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*/
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#define DAC_NUMOF (0)
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/** @} */
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/**
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* @name RTC configuration
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* @{
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*/
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#define RTC_NUMOF (0U)
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CONF_H */
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/** @} */
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