From fb7fe334b637bbbc142072f443fd1605bb5db6f5 Mon Sep 17 00:00:00 2001 From: Alexandre Abadie Date: Fri, 24 Feb 2017 17:22:59 +0100 Subject: [PATCH] boards/nucleo32-l031: initial support --- boards/nucleo32-l031/Makefile | 3 + boards/nucleo32-l031/Makefile.dep | 3 + boards/nucleo32-l031/Makefile.features | 12 ++ boards/nucleo32-l031/Makefile.include | 13 ++ boards/nucleo32-l031/board.c | 34 ++++ boards/nucleo32-l031/dist/openocd.cfg | 7 + boards/nucleo32-l031/include/board.h | 64 ++++++++ boards/nucleo32-l031/include/gpio_params.h | 48 ++++++ boards/nucleo32-l031/include/periph_conf.h | 179 +++++++++++++++++++++ 9 files changed, 363 insertions(+) create mode 100644 boards/nucleo32-l031/Makefile create mode 100644 boards/nucleo32-l031/Makefile.dep create mode 100644 boards/nucleo32-l031/Makefile.features create mode 100644 boards/nucleo32-l031/Makefile.include create mode 100644 boards/nucleo32-l031/board.c create mode 100644 boards/nucleo32-l031/dist/openocd.cfg create mode 100644 boards/nucleo32-l031/include/board.h create mode 100644 boards/nucleo32-l031/include/gpio_params.h create mode 100644 boards/nucleo32-l031/include/periph_conf.h diff --git a/boards/nucleo32-l031/Makefile b/boards/nucleo32-l031/Makefile new file mode 100644 index 000000000..f8fcbb53a --- /dev/null +++ b/boards/nucleo32-l031/Makefile @@ -0,0 +1,3 @@ +MODULE = board + +include $(RIOTBASE)/Makefile.base diff --git a/boards/nucleo32-l031/Makefile.dep b/boards/nucleo32-l031/Makefile.dep new file mode 100644 index 000000000..5472bf8b8 --- /dev/null +++ b/boards/nucleo32-l031/Makefile.dep @@ -0,0 +1,3 @@ +ifneq (,$(filter saul_default,$(USEMODULE))) + USEMODULE += saul_gpio +endif diff --git a/boards/nucleo32-l031/Makefile.features b/boards/nucleo32-l031/Makefile.features new file mode 100644 index 000000000..15648797f --- /dev/null +++ b/boards/nucleo32-l031/Makefile.features @@ -0,0 +1,12 @@ +# Put defined MCU peripherals here (in alphabetical order) +FEATURES_PROVIDED += periph_cpuid +FEATURES_PROVIDED += periph_gpio +FEATURES_PROVIDED += periph_pwm +FEATURES_PROVIDED += periph_timer +FEATURES_PROVIDED += periph_uart + +# Various common features of Nucleo boards +FEATURES_PROVIDED += cpp + +# The board MPU family (used for grouping by the CI system) +FEATURES_MCU_GROUP = cortex_m0_1 diff --git a/boards/nucleo32-l031/Makefile.include b/boards/nucleo32-l031/Makefile.include new file mode 100644 index 000000000..ac09741b5 --- /dev/null +++ b/boards/nucleo32-l031/Makefile.include @@ -0,0 +1,13 @@ +## the cpu to build for +export CPU = stm32l0 +export CPU_MODEL = stm32l031k6 + +# define the default port depending on the host OS +PORT_LINUX ?= /dev/ttyACM0 +PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.usbmodem*))) + +# setup serial terminal +include $(RIOTBOARD)/Makefile.include.serial + +# this board uses openocd +include $(RIOTBOARD)/Makefile.include.openocd diff --git a/boards/nucleo32-l031/board.c b/boards/nucleo32-l031/board.c new file mode 100644 index 000000000..bd93b1dce --- /dev/null +++ b/boards/nucleo32-l031/board.c @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2017 Freie Universität Berlin + * 2017 Inria + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup boards_nucleo32-l031 + * @{ + * + * @file + * @brief Board specific implementations for the nucleo32-l031 board + * + * @author Hauke Petersen + * @author Alexandre Abadie + * + * @} + */ + +#include "board.h" +#include "periph/gpio.h" + + +void board_init(void) +{ + /* initialize the boards LED */ + gpio_init(LED0_PIN, GPIO_OUT); + + /* initialize the CPU */ + cpu_init(); +} diff --git a/boards/nucleo32-l031/dist/openocd.cfg b/boards/nucleo32-l031/dist/openocd.cfg new file mode 100644 index 000000000..b4c770675 --- /dev/null +++ b/boards/nucleo32-l031/dist/openocd.cfg @@ -0,0 +1,7 @@ +source [find interface/stlink-v2-1.cfg] + +transport select hla_swd + +source [find target/stm32l0.cfg] + +reset_config srst_only diff --git a/boards/nucleo32-l031/include/board.h b/boards/nucleo32-l031/include/board.h new file mode 100644 index 000000000..f520bc1c2 --- /dev/null +++ b/boards/nucleo32-l031/include/board.h @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2017 Freie Universität Berlin + * 2017 Inria + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @defgroup boards_nucleo32-l031 Nucleo32-L031 + * @ingroup boards + * @brief Board specific files for the nucleo32-l031 board + * @{ + * + * @file + * @brief Board specific definitions for the nucleo32-l031 board + * + * @author Hauke Petersen + * @author Alexandre Aabdie + */ + +#ifndef BOARD_H +#define BOARD_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @name xtimer configuration + * @{ + */ +#define XTIMER_DEV TIMER_DEV(0) +#define XTIMER_CHAN (0) +#define XTIMER_WIDTH (16) +/** @} */ + +/** + * @name Macros for controlling the on-board LED. + * @{ + */ +#define LED0_PIN GPIO_PIN(PORT_B, 3) + +#define LED0_MASK (1 << 3) + +#define LED0_ON (GPIOB->BSRR = LED0_MASK) +#define LED0_OFF (GPIOB->BRR = LED0_MASK) +#define LED0_TOGGLE (GPIOB->ODR ^= LED0_MASK) +/** @} */ + +/** + * @brief Initialize board specific hardware, including clock, LEDs and std-IO + */ +void board_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* BOARD_H */ +/** @} */ diff --git a/boards/nucleo32-l031/include/gpio_params.h b/boards/nucleo32-l031/include/gpio_params.h new file mode 100644 index 000000000..89d7278dd --- /dev/null +++ b/boards/nucleo32-l031/include/gpio_params.h @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2017 Inria + * 2017 OTA keys + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup boards_nucleo32-l031 + * @{ + * + * @file + * @brief Board specific configuration of direct mapped GPIOs + * + * @author Alexandre Abadie + * @author Vincent Dupont + */ + +#ifndef GPIO_PARAMS_H +#define GPIO_PARAMS_H + +#include "board.h" +#include "saul/periph.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief GPIO pin configuration + */ +static const saul_gpio_params_t saul_gpio_params[] = +{ + { + .name = "LED(green)", + .pin = LED0_PIN, + .mode = GPIO_OUT + }, +}; + +#ifdef __cplusplus +} +#endif + +#endif /* GPIO_PARAMS_H */ +/** @} */ diff --git a/boards/nucleo32-l031/include/periph_conf.h b/boards/nucleo32-l031/include/periph_conf.h new file mode 100644 index 000000000..7ad178181 --- /dev/null +++ b/boards/nucleo32-l031/include/periph_conf.h @@ -0,0 +1,179 @@ +/* + * Copyright (C) 2017 Freie Universität Berlin + * 2017 Inria + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup boards_nucleo32-l031 + * @{ + * + * @file + * @brief Peripheral MCU configuration for the nucleo32-l031 board + * + * @author Hauke Petersen + * @author Alexandre Aabdie + */ + +#ifndef PERIPH_CONF_H +#define PERIPH_CONF_H + +#include "periph_cpu.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @name Clock system configuration + * @{ + */ +#define CLOCK_HSI (16000000U) /* internal oscillator */ +#define CLOCK_CORECLOCK (32000000U) /* desired core clock frequency */ + +/* configuration of PLL prescaler and multiply values */ +/* CORECLOCK := HSI / CLOCK_PLL_DIV * CLOCK_PLL_MUL */ +#define CLOCK_PLL_DIV RCC_CFGR_PLLDIV2 +#define CLOCK_PLL_MUL RCC_CFGR_PLLMUL4 +/* configuration of peripheral bus clock prescalers */ +#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* AHB clock -> 32MHz */ +#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* APB2 clock -> 32MHz */ +#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV1 /* APB1 clock -> 32MHz */ +/* configuration of flash access cycles */ +#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY + +/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */ +#define CLOCK_AHB (CLOCK_CORECLOCK / 1) +#define CLOCK_APB2 (CLOCK_CORECLOCK / 1) +#define CLOCK_APB1 (CLOCK_CORECLOCK / 1) +/** @} */ + +/** + * @brief Timer configuration + * @{ + */ +static const timer_conf_t timer_config[] = { + { + .dev = TIM2, + .max = 0x0000ffff, + .rcc_mask = RCC_APB1ENR_TIM2EN, + .bus = APB1, + .irqn = TIM2_IRQn + } +}; + +#define TIMER_0_ISR isr_tim2 + +#define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0])) +/** @} */ + +/** + * @brief UART configuration + * @{ + */ +static const uart_conf_t uart_config[] = { + { + .dev = USART2, + .rcc_mask = RCC_APB1ENR_USART2EN, + .rx_pin = GPIO_PIN(PORT_A, 15), + .tx_pin = GPIO_PIN(PORT_A, 2), + .rx_af = GPIO_AF4, + .tx_af = GPIO_AF4, + .bus = APB1, + .irqn = USART2_IRQn + } +}; + +#define UART_0_ISR (isr_usart2) + +#define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0])) +/** @} */ + +/** + * @brief PWM configuration + * @{ + */ +static const pwm_conf_t pwm_config[] = { + { + .dev = TIM21, + .rcc_mask = RCC_APB2ENR_TIM21EN, + .chan = { { .pin = GPIO_PIN(PORT_B, 6) /* D5 */, .cc_chan = 0 }, + { .pin = GPIO_UNDEF, .cc_chan = 0 }, + { .pin = GPIO_UNDEF, .cc_chan = 0 }, + { .pin = GPIO_UNDEF, .cc_chan = 0 } }, + .af = GPIO_AF5, + .bus = APB2 + } +}; + +#define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0])) +/** @} */ + +/** + * @name SPI configuration + * @{ + */ +static const uint8_t spi_divtable[2][5] = { + { /* for APB1 @ 32000000Hz */ + 7, /* -> 125000Hz */ + 5, /* -> 500000Hz */ + 4, /* -> 1000000Hz */ + 2, /* -> 4000000Hz */ + 1 /* -> 8000000Hz */ + }, + { /* for APB2 @ 32000000Hz */ + 7, /* -> 125000Hz */ + 5, /* -> 500000Hz */ + 4, /* -> 1000000Hz */ + 2, /* -> 4000000Hz */ + 1 /* -> 8000000Hz */ + } +}; + +static const spi_conf_t spi_config[] = { + { + .dev = SPI1, + .mosi_pin = GPIO_PIN(PORT_B, 5), + .miso_pin = GPIO_PIN(PORT_B, 4), + .sclk_pin = GPIO_PIN(PORT_B, 3), + .cs_pin = GPIO_UNDEF, + .af = GPIO_AF0, + .rccmask = RCC_APB2ENR_SPI1EN, + .apbbus = APB2 + } +}; + +#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0])) +/** @} */ + +/** + * @brief ADC configuration + * @{ + */ +#define ADC_NUMOF (0) +/** @} */ + + +/** + * @brief DAC configuration + * @{ + */ +#define DAC_NUMOF (0) +/** @} */ + +/** + * @name RTC configuration + * @{ + */ +#define RTC_NUMOF (0U) +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* PERIPH_CONF_H */ +/** @} */