This is a rewrite of the Kinetis GPIO driver which follows the
refactored API in [1]. Pins are specified using the GPIO_PIN(PORT_x, y)
macro, e.g. GPIO_PIN(PORT_E, 25) for the PTE25 pin.
The interrupt pin handling is now implemented as a linked list, this
is more memory efficient, but with a minor variation in interrupt
latency depending on in what order the pins were initialized at
runtime.
Because the linked list entries are taken from a shared pool, there is
also the possibility of running out of available configuration slots,
define the preprocessor macro GPIO_INT_POOL_SIZE in periph_conf.h if
you need more than 16 pins configured for interrupts in the same
application.
[1]: https://github.com/RIOT-OS/RIOT/pull/3095
Fixes error on LLVM/Clang:
cpu/cortexm_common/vectors_cortexm.c:287:5: error: non-ASM statement in naked function is not supported
core_panic(PANIC_HARD_FAULT, "HARD FAULT HANDLER");
^
cpu/cortexm_common/include/vectors_cortexm.h:65:46: note: attribute is here
void hard_fault_default(void) __attribute__((naked));
^
1 error generated.
e4218: SIM/FLEXBUS: SIM_SCGC7[FLEXBUS] bit should be cleared when the
FlexBus is not being used.
Errata type: Errata
Description:
The SIM_SCGC7[FLEXBUS] bit is set by default. This means that the
FlexBus will be enabled and come up in global chip select mode. With
some code sequence and register value combinations the core could
attempt to prefetch from the FlexBus even though it might not actually
use the value it prefetched. In the case where the FlexBus is
unconfigured, this can result in a hung bus cycle on the FlexBus.
Workaround:
- If the FlexBus is not being used, disabled the clock to the FlexBus
during chip initialization by clearing the SIM_SCGC7[FLEXBUS] bit.
- If the FlexBus will be used, then enable at least one chip select as
early in the chip initialization process as possible.
Peter Kietzmann