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5 Commits

Author SHA1 Message Date
Marc Poulhiès 39d9057e42 Remove comments, is a fixup 7 years ago
Marc 2932aeab3f DO NOT MERGE 7 years ago
Marc 58871faeaa Initial support for ADC 7 years ago
Marc e75cc80024 initial support for PWM output 7 years ago
Marc 8f99077651 Initial gpio support for stellaris/lm4f120 7 years ago
  1. 30
      boards/ek-lm4f120xl/include/periph_conf.h
  2. 15
      cpu/lm4f120/include/periph_cpu.h
  3. 187
      cpu/lm4f120/periph/adc.c
  4. 339
      cpu/lm4f120/periph/gpio.c
  5. 242
      cpu/lm4f120/periph/pwm.c
  6. 392
      cpu/lm4f120/periph/timer.c
  7. 346
      cpu/stellaris_common/include/cortex-m4-def.h

30
boards/ek-lm4f120xl/include/periph_conf.h

@ -42,19 +42,26 @@ extern "C" {
*/
#define TIMER_NUMOF (2U)
#define TIMER_0_EN 1
#define TIMER_1_EN 0
#define TIMER_1_EN 1
#define TIMER_IRQ_PRIO 1
/* Timer 0 configuration */
/* Timer 0 configuration
*
* WTIMER0 is a 32/64bits timer.
* We use timer_a as TIMER_0
*/
#define TIMER_0_CHANNELS 1
#define TIMER_0_PRESCALER (39U)
#define TIMER_0_MAX_VALUE (0xffffffff)
#define TIMER_0_ISR isr_wtimer0a
#define TIMER_0_IRQ_CHAN Timer0A_IRQn
/* Timer 1 configuration */
/* Timer 1 configuration
*
* WTIMER1 is a 32/64bits timer.
* We use timer_a as TIMER_1
*/
#define TIMER_1_CHANNELS 1
#define TIMER_1_PRESCALER (39U)
#define TIMER_1_MAX_VALUE (0xffffffff)
#define TIMER_1_ISR isr_wtimer1a
#define TIMER_1_IRQ_CHAN Timer1A_IRQn
@ -86,6 +93,19 @@ extern "C" {
#define UART_1_ISR isr_uart1
/** @} */
/**
* @name PWM configuration
* @{
*/
#define PWM_NUMOF (PWM_0_EN)
#define PWM_0_EN 1
//#define PWM_1_EN 1
#define PWM_MAX_CHANNELS 1
#define ADC_NUMOF 1
#define ADC_0_EN 1
#define ADC_MAX_CHANNELS 12
#ifdef __cplusplus
}
#endif

15
cpu/lm4f120/include/periph_cpu.h

@ -15,18 +15,31 @@
*
* @author Rakendra Thapa <rakendrathapa@gmail.com>
*/
#ifndef PERIPH_CPU_H_
#define PERIPH_CPU_H_
#include <inttypes.h>
#include "periph/dev_enums.h"
#ifdef __cplusplus
extern "C" {
#endif
#define HAVE_GPIO_T
typedef uint32_t gpio_t;
#define GPIO(x,y) ((gpio_t)(x<<4 | y))
/* nothing to do here, yet */
enum {
PORT_A = 0, /**< port A */
PORT_B = 1, /**< port B */
PORT_C = 2, /**< port C */
PORT_D = 3, /**< port D */
PORT_E = 4, /**< port E */
PORT_F = 5, /**< port F */
};
#ifdef __cplusplus
}
#endif

187
cpu/lm4f120/periph/adc.c

@ -0,0 +1,187 @@
/*
* Copyright (C) 2015 Marc Poulhiès
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup cpu_lm4f120
* @{
*
* @file
* @brief Low-level ADC driver implementation
*
* @author Marc Poulhiès <dkm@kataplop.net>
*
* @}
*/
#include <stdint.h>
#include <string.h>
#include "cpu.h"
#include "periph/adc.h"
#include "periph_conf.h"
/* guard in case that no ADC device is defined */
#if ADC_NUMOF
static unsigned long adc0_gpio[ADC_MAX_CHANNELS][3] = {
{GPIO_PORTE_BASE, SYSCTL_PERIPH_GPIOE, GPIO_PIN_3}, // AIN0
{GPIO_PORTE_BASE, SYSCTL_PERIPH_GPIOE, GPIO_PIN_2}, // AIN1
{GPIO_PORTE_BASE, SYSCTL_PERIPH_GPIOE, GPIO_PIN_1}, // AIN2
{GPIO_PORTE_BASE, SYSCTL_PERIPH_GPIOE, GPIO_PIN_0}, // AIN3
{GPIO_PORTE_BASE, SYSCTL_PERIPH_GPIOD, GPIO_PIN_3}, // AIN4
{GPIO_PORTE_BASE, SYSCTL_PERIPH_GPIOD, GPIO_PIN_2}, // AIN5
{GPIO_PORTE_BASE, SYSCTL_PERIPH_GPIOD, GPIO_PIN_1}, // AIN6
{GPIO_PORTE_BASE, SYSCTL_PERIPH_GPIOD, GPIO_PIN_0}, // AIN7
{GPIO_PORTE_BASE, SYSCTL_PERIPH_GPIOE, GPIO_PIN_5}, // AIN8
{GPIO_PORTE_BASE, SYSCTL_PERIPH_GPIOE, GPIO_PIN_4}, // AIN9
{GPIO_PORTE_BASE, SYSCTL_PERIPH_GPIOB, GPIO_PIN_4}, // AIN10
{GPIO_PORTE_BASE, SYSCTL_PERIPH_GPIOB, GPIO_PIN_5}, // AIN11
};
#define ADC_0_SYSCTL SYSCTL_PERIPH_ADC0
#define ADC_0_GPIO adc0_gpio
//#define ADC_0_GPIO_PIN GPIO_PIN_3
#define ADC_0_BASE ADC0_BASE
#define ADC_0_CHANNEL ADC_CTL_CH0
#define ADC_0_SEQ 3
typedef struct {
uint8_t precision;
} adc_config_t;
adc_config_t config[ADC_NUMOF];
int adc_init(adc_t dev, adc_precision_t precision)
{
unsigned long adc_base;
unsigned long adc_seq;
switch (dev) {
#if ADC_0_EN
case ADC_0:
adc_base = ADC_0_BASE;
adc_seq = ADC_0_SEQ;
break;
#endif
}
adc_poweron(dev);
// ROM_ADCHardwareOversampleConfigure(adc_base, 64);
ROM_ADCSequenceDisable(adc_base, adc_seq);
ROM_SysCtlADCSpeedSet(SYSCTL_ADCSPEED_500KSPS);
/* ROM_ADCIntEnable(adc_base, adc_seq); */
/* ROM_ADCSequenceConfigure(adc_base, adc_seq, ADC_TRIGGER_PROCESSOR, 0); */
/* ROM_ADCSequenceStepConfigure(adc_base, adc_seq, 0, adc_channel | ADC_CTL_IE | ADC_CTL_END); */
/* ROM_ADCSequenceEnable(adc_base, adc_seq); */
/* ROM_ADCIntClear(adc_base, adc_seq); */
/* switch (precision) { */
/* case ADC_RES_6BIT: */
/* case ADC_RES_8BIT: */
/* case ADC_RES_10BIT: */
/* case ADC_RES_12BIT: */
/* case ADC_RES_14BIT: */
/* case ADC_RES_16BIT: */
/* adc_poweroff(dev); */
/* return -1; */
/* break; */
/* } */
return 0;
}
int adc_sample(adc_t dev, int channel)
{
int value[2];
unsigned long adc_base;
unsigned long adc_seq;
unsigned long adc_gpio_port = 0;
unsigned long adc_gpio_pin = 0;
unsigned long adc_gpio_sysctl = 0;
if (channel >= ADC_MAX_CHANNELS){
return -1;
}
switch (dev) {
#if ADC_0_EN
case ADC_0:
adc_base = ADC_0_BASE;
adc_seq = ADC_0_SEQ;
adc_gpio_port = ADC_0_GPIO[channel][0];
adc_gpio_sysctl = ADC_0_GPIO[channel][1];
adc_gpio_pin = ADC_0_GPIO[channel][2];
break;
#endif
}
ROM_SysCtlPeripheralEnable(adc_gpio_sysctl);
ROM_GPIOPinTypeADC(adc_gpio_port, adc_gpio_pin);
ROM_ADCSequenceDisable(adc_base, adc_seq);
ROM_ADCIntClear(adc_base, adc_seq);
ROM_ADCSequenceConfigure(adc_base, adc_seq, ADC_TRIGGER_PROCESSOR, 0);
ROM_ADCSequenceStepConfigure(adc_base, adc_seq, 0, channel | ADC_CTL_IE | ADC_CTL_END);
ROM_ADCSequenceEnable(adc_base, adc_seq);
ROM_ADCIntClear(adc_base, adc_seq);
ROM_ADCProcessorTrigger(adc_base, adc_seq);
while(!ROM_ADCIntStatus(adc_base, adc_seq, false)) {
}
ROM_ADCIntClear(adc_base, adc_seq);
ROM_ADCSequenceDataGet(adc_base, adc_seq, (unsigned long*) value);
return value[0];
}
void adc_poweron(adc_t dev)
{
unsigned long adc_sysctl;
switch (dev) {
#if ADC_0_EN
case ADC_0:
adc_sysctl = ADC_0_SYSCTL;
break;
#endif
}
ROM_SysCtlPeripheralEnable(adc_sysctl);
}
void adc_poweroff(adc_t dev)
{
unsigned long adc_sysctl;
switch (dev) {
#if ADC_0_EN
case ADC_0:
adc_sysctl = ADC_0_SYSCTL;
break;
#endif
}
ROM_SysCtlPeripheralDisable(adc_sysctl);
}
int adc_map(adc_t dev, int value, int min, int max)
{
return 0;
}
float adc_mapf(adc_t dev, int value, float min, float max)
{
return 0.0;
}
#endif /* ADC_NUMOF */

339
cpu/lm4f120/periph/gpio.c

@ -0,0 +1,339 @@
/*
* Copyright (C) 2015 Marc Poulhiès
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup cpu_lm4f120
* @{
*
* @file
* @brief Low-level GPIO driver implementation
*
* @author Marc Poulhiès <dkm@kataplop.net>
*
* @}
*/
#include <stdio.h>
#include "cpu.h"
#include "cpu_conf.h"
#include "periph/gpio.h"
#include "periph_conf.h"
#define ENABLE_DEBUG (0)
#include "debug.h"
/**
* @brief Extract the pin number of the given pin
*/
static inline uint8_t _pin_num(gpio_t pin)
{
return (pin & 0x0f);
}
/**
* @brief Extract the port number of the given pin
*/
static inline uint8_t _port_num(gpio_t pin)
{
return (pin >> 4);
}
static uint32_t _port_base[] = {
GPIO_PORTA_BASE,
GPIO_PORTB_BASE,
GPIO_PORTC_BASE,
GPIO_PORTD_BASE,
GPIO_PORTE_BASE,
GPIO_PORTF_BASE,
};
#define NUM_OF_PORT 6
#define NUM_OF_PINS 8
typedef struct {
gpio_cb_t cb; /**< callback called from GPIO interrupt */
void *arg; /**< argument passed to the callback */
} gpio_state_t;
static gpio_state_t gpio_config[NUM_OF_PORT][NUM_OF_PINS];
static inline uint16_t _port_addr(gpio_t pin)
{
uint8_t port_num = _port_num(pin);
uint32_t port_addr = _port_base[port_num];
return port_addr;
}
#define _WRITE_CR_PIN(port,val) \
do { \
GPIO_##port##_LOCK_R = GPIO_LOCK_KEY; \
GPIO_##port##_CR_R |= (val); \
GPIO_##port##_LOCK_R = 0; \
} while(0)
#define _LOCK_PORT \
do { \
switch(port_num){ \
case PORT_A: \
_WRITE_CR_PIN(PORTA,(1<<pin_num)); \
break; \
case PORT_B: \
_WRITE_CR_PIN(PORTB,(1<<pin_num)); \
break; \
case PORT_C: \
_WRITE_CR_PIN(PORTC,(1<<pin_num)); \
break; \
case PORT_D: \
_WRITE_CR_PIN(PORTD,(1<<pin_num)); \
break; \
case PORT_E: \
_WRITE_CR_PIN(PORTE,(1<<pin_num)); \
break; \
case PORT_F: \
_WRITE_CR_PIN(PORTF,(1<<pin_num)); \
break; \
} \
} while (0);
#define _UNLOCK_PORT \
do { \
switch(port_num){ \
case PORT_A: \
GPIO_PORTA_CR_R &= ~(1<<pin_num); \
break; \
case PORT_B: \
GPIO_PORTB_CR_R &= ~(1<<pin_num); \
break; \
case PORT_C: \
GPIO_PORTC_CR_R &= ~(1<<pin_num); \
break; \
case PORT_D: \
GPIO_PORTD_CR_R &= ~(1<<pin_num); \
break; \
case PORT_E: \
GPIO_PORTE_CR_R &= ~(1<<pin_num); \
break; \
case PORT_F: \
GPIO_PORTF_CR_R &= ~(1<<pin_num); \
break; \
} \
} while(0)
int gpio_init(gpio_t pin, gpio_dir_t dir, gpio_pp_t pullup)
{
uint8_t port_num = _port_num(pin);
uint32_t port_addr = _port_base[port_num];
uint8_t pin_num = _pin_num(pin);
if (dir == GPIO_DIR_IN){
switch(pullup){
case GPIO_PULLDOWN:
_LOCK_PORT;
ROM_GPIODirModeSet(port_addr, 1<<pin_num, GPIO_DIR_MODE_IN);
ROM_GPIOPadConfigSet(port_addr, 1<<pin_num,
GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPD);
_UNLOCK_PORT;
break;
case GPIO_PULLUP:
_LOCK_PORT;
ROM_GPIODirModeSet(port_addr, 1<<pin_num, GPIO_DIR_MODE_IN);
ROM_GPIOPadConfigSet(port_addr, 1<<pin_num,
GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPU);
_UNLOCK_PORT;
break;
case GPIO_NOPULL:
ROM_GPIODirModeSet(port_addr, 1<<pin_num, GPIO_DIR_MODE_IN);
ROM_GPIOPadConfigSet(port_addr, 1<<pin_num,
GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
break;
}
} else if (dir == GPIO_DIR_OUT){
ROM_GPIOPinTypeGPIOOutput(port_addr, 1<<pin_num);
}
return 0;
}
static void _isr_gpio(uint32_t port_num){
uint32_t port_addr = _port_base[port_num];
uint32_t isr = ROM_GPIOPinIntStatus(port_addr, true);
uint8_t i;
ROM_GPIOPinIntClear(port_addr, isr);
for (i=0; i<8; i++, isr>>=1) {
if ((isr & 0x1) == 0)
continue;
if (gpio_config[port_num][i].cb)
gpio_config[port_num][i].cb(gpio_config[port_num][i].arg);
}
}
void isr_gpio_porta(void){
_isr_gpio(0);
}
void isr_gpio_portb(void){
_isr_gpio(1);
}
void isr_gpio_portc(void){
_isr_gpio(2);
}
void isr_gpio_portd(void){
_isr_gpio(3);
}
void isr_gpio_porte(void){
_isr_gpio(4);
}
void isr_gpio_portf(void){
_isr_gpio(5);
}
static void lm4f120_gpio_int_clear(uint32_t icr_reg_addr, uint32_t pin_mask){
HWREG(icr_reg_addr) = pin_mask;
}
int gpio_init_int(gpio_t pin, gpio_pp_t pullup, gpio_flank_t flank,
gpio_cb_t cb, void *arg)
{
uint8_t port_num = _port_num(pin);
uint32_t port_addr = _port_base[port_num];
uint32_t icr_reg_addr = port_addr + GPIO_ICR_R_OFF;
uint8_t pin_num = _pin_num(pin);
uint8_t pin_bit = 1<<pin_num;
uint32_t lm4fMode = 0;
gpio_config[port_num][pin_num].cb = cb;
gpio_config[port_num][pin_num].arg = arg;
switch(flank) {
/* case LOW: */
/* lm4fMode = GPIO_LOW_LEVEL; */
/* break; */
case GPIO_BOTH:
lm4fMode = GPIO_BOTH_EDGES;
break;
case GPIO_RISING:
lm4fMode = GPIO_RISING_EDGE;
break;
case GPIO_FALLING:
lm4fMode = GPIO_FALLING_EDGE;
break;
}
unsigned long pull_val = GPIO_PIN_TYPE_STD;
switch(pullup){
case GPIO_PULLDOWN:
pull_val = GPIO_PIN_TYPE_STD_WPD;
break;
case GPIO_PULLUP:
pull_val = GPIO_PIN_TYPE_STD_WPU;
break;
case GPIO_NOPULL:
pull_val = GPIO_PIN_TYPE_STD;
break;
}
_LOCK_PORT;
ROM_GPIODirModeSet(port_addr, 1<<pin_num, GPIO_DIR_MODE_IN);
ROM_GPIOPadConfigSet(port_addr, 1<<pin_num,
GPIO_STRENGTH_2MA, pull_val);
_UNLOCK_PORT;
ROM_IntMasterDisable();
lm4f120_gpio_int_clear(icr_reg_addr, pin_bit);
ROM_GPIOIntTypeSet(port_addr, pin_bit, lm4fMode);
gpio_irq_enable(pin);
ROM_IntEnable(INT_GPIOF);
ROM_IntMasterEnable();
return 0;
}
void gpio_irq_enable(gpio_t pin)
{
uint8_t port_num = _port_num(pin);
uint32_t port_addr = _port_base[port_num];
uint32_t im_reg_addr = port_addr + GPIO_IM_R_OFF;
uint8_t pin_num = _pin_num(pin);
uint8_t pin_bit = 1<<pin_num;
HWREG(im_reg_addr) |= pin_bit;
}
void gpio_irq_disable(gpio_t pin)
{
uint8_t port_num = _port_num(pin);
uint32_t port_addr = _port_base[port_num];
uint32_t im_reg_addr = port_addr + GPIO_IM_R_OFF;
uint8_t pin_num = _pin_num(pin);
uint8_t pin_bit = 1<<pin_num;
HWREG(im_reg_addr) &= ~(pin_bit);
}
int gpio_read(gpio_t pin)
{
uint8_t port_num = _port_num(pin);
uint32_t port_addr = _port_base[port_num];
uint8_t pin_num = _pin_num(pin);
if(ROM_GPIOPinRead(port_addr, 1<<pin_num)){
return 1;
}
return 0;
}
void gpio_set(gpio_t pin)
{
uint8_t port_num = _port_num(pin);
uint32_t port_addr = _port_base[port_num];
uint8_t pin_num = _pin_num(pin);
ROM_GPIOPinWrite(port_addr, 1<<pin_num, 1<<pin_num);
}
void gpio_clear(gpio_t pin)
{
uint8_t port_num = _port_num(pin);
uint32_t port_addr = _port_base[port_num];
uint8_t pin_num = _pin_num(pin);
ROM_GPIOPinWrite(port_addr, 1<<pin_num, 0);
}
void gpio_toggle(gpio_t pin)
{
if (gpio_read(pin)) {
gpio_clear(pin);
}
else {
gpio_set(pin);
}
}
void gpio_write(gpio_t pin, int value)
{
if (value) {
gpio_set(pin);
}
else {
gpio_clear(pin);
}
}

242
cpu/lm4f120/periph/pwm.c

@ -0,0 +1,242 @@
/*
* Copyright (C) 2015 Marc Poulhiès
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup cpu_lm4f120
* @{
*
* @file
* @brief Low-level PWM driver implementation
*
* @author Marc Poulhiès <dkm@kataplop.net>
*
* @}
*/
#include <stdint.h>
#include <string.h>
#include "log.h"
#include "cpu.h"
#include "board.h"
#include "periph/pwm.h"
#include "periph/gpio.h"
#include "periph_conf.h"
#define ENABLE_DEBUG (1)
#include "debug.h"
/* ignore file in case no PWM devices are defined */
#if PWM_NUMOF
typedef struct pwm_conf_s {
uint8_t pin_num;
uint32_t ccp;
uint32_t timer;
} pwm_conf_t;
#define PWM_0_GPIO_PIN GPIO_PIN_4
#define PWM_0_GPIO_SYSCTL_PORT SYSCTL_PERIPH_GPIOB
#define PWM_0_GPIO_PORT_BASE GPIO_PORTB_BASE
#define PWM_0_CCP GPIO_PB4_T1CCP0
#define PWM_0_TIMER TIMER1_BASE
#define PWM_0_TIMER_SIDE TIMER_A
#define PWM_0_TIMER_SYSCTL SYSCTL_PERIPH_TIMER1
#define PWM_0_TIMER_PWMCFG TIMER_CFG_A_PWM
/*
* 4 devices, 2 channels per device.
*/
/*
* PWM dev 0 : T0
* - PB3 CCP0
* - PB2 CCP1
* dev 1 : T1
* - PB4 CCP0
* - PB5 CCP1
* dev 2 : T2
* - PB0 CCP0
* - PB1 CCP1
* dev 3 : T3
* - PB2 CCP0
* - PB3 CCP1
*/
int pwm_init(pwm_t dev, pwm_mode_t mode,
unsigned int frequency, unsigned int resolution)
{
if (dev >= PWM_NUMOF) {
return -1;
}
unsigned long timer_base;
unsigned long gpio_pin;
unsigned long ccp;
unsigned long timer_ab;
unsigned long gpio_sysctl;
unsigned long gpio_port_base;
unsigned long timer_pwm_cfg;
switch (dev){
case PWM_0:
timer_pwm_cfg = PWM_0_TIMER_PWMCFG;
timer_base = PWM_0_TIMER;
gpio_pin = PWM_0_GPIO_PIN;
ccp = PWM_0_CCP;
timer_ab = PWM_0_TIMER_SIDE;
gpio_sysctl = PWM_0_GPIO_SYSCTL_PORT;
gpio_port_base = PWM_0_GPIO_PORT_BASE;
break;
#if 0
case PWM_1:
case PWM_2:
#endif
default:
return -1;
}
// Enable GPIO port
ROM_SysCtlPeripheralEnable(gpio_sysctl);
ROM_GPIOPinConfigure(ccp);
ROM_GPIOPinTypeTimer(gpio_port_base, gpio_pin);
pwm_poweron(dev);
ROM_TimerDisable(timer_base, timer_ab);
ROM_TimerConfigure(timer_base, TIMER_CFG_SPLIT_PAIR | timer_pwm_cfg);
unsigned long clock = ROM_SysCtlClockGet();
// interface specifies we must keep the resolution
unsigned long ticks = resolution;
unsigned long real_freq = clock/resolution;
// unsigned long prescale = clock / (frequency * resolution);
unsigned long prescale_count_extend = ticks >> 16;
unsigned long ticks_low = ticks & 0xFFFF;
if (prescale_count_extend & ~0xFF) {
DEBUG("Resolution too high\n");
return -1;
}
/* if (prescale & (~0xFF)){ */
/* DEBUG("Can't find settings for freq %u at resolution %u\n", frequency, resolution); */
/* return -1; */
/* } */
DEBUG("Prescaler set at %lu\n", prescale_count_extend);
ROM_TimerPrescaleSet(timer_base, timer_ab, prescale_count_extend);
// uint32_t ticks = resolution; //clock / frequency;
DEBUG("Setting ticks at %lu (reqf: %u, freq cpu: %lu)\n", ticks, frequency, clock);
DEBUG("Real freq: %lu\n", real_freq);
ROM_TimerMatchSet(timer_base, timer_ab, /* dutyCycle */ prescale_count_extend);
ROM_TimerPrescaleMatchSet(timer_base, timer_ab, 0);
ROM_TimerLoadSet(timer_base, timer_ab, /* ticks */ ticks_low);
/* set PWM mode */
/* switch (mode) { */
/* case PWM_LEFT: */
/* case PWM_RIGHT: */
/* case PWM_CENTER: */
/* default: */
/* return -1; */
/* } */
pwm_start(dev);
return real_freq;
}
int pwm_set(pwm_t dev, int channel, unsigned int value)
{
if (channel >= PWM_MAX_CHANNELS) {
return -1;
}
unsigned long timer_base;
unsigned long timer_ab;
switch (dev){
case PWM_0:
timer_base = PWM_0_TIMER;
timer_ab = PWM_0_TIMER_SIDE;
break;
default:
return -1;
}
ROM_TimerMatchSet(timer_base, timer_ab, value);
return 0;
}
void pwm_start(pwm_t dev)
{
unsigned long timer_base = -1;
unsigned long timer_ab;
switch (dev){
case PWM_0:
timer_base = PWM_0_TIMER;
timer_ab = PWM_0_TIMER_SIDE;
break;
default:
return;
}
ROM_TimerEnable(timer_base, timer_ab);
}
void pwm_stop(pwm_t dev)
{
unsigned long timer_base = -1;
unsigned long timer_ab;
switch (dev){
case PWM_0:
timer_base = PWM_0_TIMER;
timer_ab = PWM_0_TIMER_SIDE;
break;
default:
return;
}
ROM_TimerDisable(timer_base, timer_ab);
}
void pwm_poweron(pwm_t dev)
{
unsigned long timer_sysctl;
switch (dev){
case PWM_0:
timer_sysctl = PWM_0_TIMER_SYSCTL;
break;
default:
return;
}
ROM_SysCtlPeripheralEnable(timer_sysctl);
}
void pwm_poweroff(pwm_t dev)
{
unsigned long timer_sysctl;
switch (dev){
case PWM_0:
timer_sysctl = PWM_0_TIMER_SYSCTL;
break;
default:
return;
}
ROM_SysCtlPeripheralDisable(timer_sysctl);
}
#endif /* PWM_NUMOF */

392
cpu/lm4f120/periph/timer.c

@ -1,5 +1,6 @@
/*
* Copyright (C) 2015 Rakendra Thapa <rakendrathapa@gmail.com
* 2015 Marc Poulhiès <dkm@kataplop.net>
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
@ -14,6 +15,7 @@
* @brief Implementation of the low-level timer driver for the LM4F120
*
* @author Rakendra Thapa <rakendrathapa@gmail.com>
* Marc Poulhiès <dkm@kataplop.net>
*/
#include <stdint.h>
@ -36,131 +38,401 @@
*/
typedef struct {
void (*cb)(int); /**< timeout callback */
unsigned int diviser; /**< software clock diviser */
} timer_conf_t;
static timer_conf_t config[TIMER_NUMOF];
/**@}*/
#include "hw_timer.h"
// Missing from driverlib ?!
static inline unsigned long
PRIV_TimerPrescaleSnapshotGet(unsigned long ulBase, unsigned long ulTimer)
{
return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAPS) :
HWREG(ulBase + TIMER_O_TBPS));
}
static inline unsigned long long _scaled_to_ll_value(unsigned int uncorrected, unsigned int diviser){
unsigned long long scaledv = (unsigned long long) uncorrected * diviser;
return scaledv;
}
static inline unsigned int _llvalue_to_scaled_value(unsigned long long corrected, unsigned int diviser){
unsigned long long scaledv = corrected / diviser;
return scaledv;
}
int timer_init(tim_t dev, unsigned int us_per_tick, void (*callback)(int))
{
if (dev == TIMER_0) {
config[dev].cb = callback; /* User Function */
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_WTIMER0); /* Activate Timer0 */
WTIMER0_CTL_R &= ~0x00000001; /* Disable timer0A during setup */
WTIMER0_CFG_R = TIMER_CFG_16_BIT;
WTIMER0_TAMR_R = TIMER_TAMR_TAMR_PERIOD; /* Configure for periodic mode */
WTIMER0_TAPR_R = TIMER_0_PRESCALER; /* 1us timer0A */
WTIMER0_ICR_R = 0x00000001; /* clear timer0A timeout flag */
WTIMER0_IMR_R |= 0x00000001; /* arm timeout interrupt */
ROM_IntPrioritySet(INT_WTIMER0A, 32);
timer_irq_enable(dev);
timer_start(dev);
DEBUG("startTimeout Value=0x%lx\n", ROM_TimerValueGet(WTIMER0_BASE, TIMER_A));
return 1;
if (dev >= TIMER_NUMOF){
return -1;
}
return -1;
config[dev].cb = callback; /* User Function */
config[dev].diviser = us_per_tick * ROM_SysCtlClockGet()/1000000;
unsigned int sysctl_timer;
unsigned int timer_base;
unsigned int timer_side = TIMER_A;
unsigned int timer_cfg = TIMER_CFG_SPLIT_PAIR | TIMER_CFG_A_PERIODIC_UP;
unsigned int timer_max_val;
unsigned int timer_intbit = TIMER_TIMA_TIMEOUT | TIMER_TIMA_MATCH;
switch(dev){
#if TIMER_0_EN
case TIMER_0:
sysctl_timer = SYSCTL_PERIPH_WTIMER0;
timer_base = WTIMER0_BASE;
timer_max_val = TIMER_0_MAX_VALUE;
break;
#endif
#if TIMER_1_EN
case TIMER_1:
sysctl_timer = SYSCTL_PERIPH_WTIMER1;
timer_base = WTIMER1_BASE;
timer_max_val = TIMER_1_MAX_VALUE;
break;
#endif
default:
return -1; // unreachable
}
if (timer_side == TIMER_A) {
timer_cfg |= TIMER_TAMR_TAMIE;
} else if (timer_side == TIMER_B){
timer_cfg |= TIMER_TBMR_TBMIE;
}
ROM_SysCtlPeripheralEnable(sysctl_timer);
ROM_TimerDisable(timer_base, timer_side);
// WTIMER0_CTL_R &= ~0x00000001; /* Disable timer0A during setup */
ROM_TimerConfigure(timer_base, timer_cfg);
unsigned long long lltimer_val_max = _scaled_to_ll_value(timer_max_val, config[dev].diviser);
ROM_TimerPrescaleSet(timer_base, timer_side, lltimer_val_max >> 32);
ROM_TimerLoadSet(timer_base, timer_side, lltimer_val_max & 0xFFFFFFFF);
//WTIMER0_TAPR_R = TIMER_0_PRESCALER; /* 1us timer0A */
ROM_TimerIntClear(timer_base, timer_intbit);
//WTIMER0_ICR_R = 0x00000001; /* clear timer0A timeout flag */
//WTIMER0_IMR_R |= 0x00000001; /* arm timeout interrupt */
ROM_TimerIntEnable(timer_base, timer_intbit);
timer_irq_enable(dev);
timer_start(dev);
return 1;
}
int timer_set(tim_t dev, int channel, unsigned int timeout)
{
if (dev == TIMER_0) {
unsigned int now = timer_read(dev);
DEBUG("timer_set now=0x%x\n",now);
DEBUG("timer_set timeout=0x%x\n", timeout);
return timer_set_absolute(dev, channel, now+timeout);
if (dev >= TIMER_NUMOF){
return -1;
}
return -1;
switch(dev){
#if TIMER_0_EN
case TIMER_0:
break;
#endif
#if TIMER_1_EN
case TIMER_1:
break;
#endif
default:
return -1; // unreachable
}
unsigned int correct_now = timer_read(dev);
unsigned long long uncorrected_now = _scaled_to_ll_value(correct_now, config[dev].diviser);
int r = timer_set_absolute(dev, channel, uncorrected_now+timeout);
return r;
}
int timer_set_absolute(tim_t dev, int channel, unsigned int value)
{
if (dev == TIMER_0) {
WTIMER0_TAILR_R = 0x00000000 | value; /* period; Reload value */
DEBUG("Setting timer absolute value=0x%x\n", value);
return 1;
}
unsigned int timer_base;
unsigned int timer_side = TIMER_A;
if (dev >= TIMER_NUMOF){
return -1;
}
switch(dev){
#if TIMER_0_EN
case TIMER_0:
timer_base = WTIMER0_BASE;
break;
#endif
#if TIMER_1_EN
case TIMER_1:
timer_base = WTIMER1_BASE;
break;
#endif
default:
return -1; // unreachable
break;
}
ROM_TimerDisable(timer_base, timer_side);
unsigned long long scaledv = _scaled_to_ll_value(value, config[dev].diviser);
if (scaledv>>32){
ROM_TimerPrescaleMatchSet(timer_base, timer_side, scaledv >> 32);
} else {
ROM_TimerPrescaleMatchSet(timer_base, timer_side, 0);
}
ROM_TimerMatchSet(timer_base, timer_side, (unsigned long) (scaledv & 0xFFFFFFFF));
//WTIMER0_TAILR_R = 0x00000000 | value; /* period; Reload value */
ROM_TimerEnable(timer_base, timer_side);
return 1;
}
int timer_clear(tim_t dev, int channel)
{
if (dev == TIMER_0){
WTIMER0_ICR_R = TIMER_ICR_TATOCINT;
return 1;
unsigned int timer_intbit = TIMER_TIMA_TIMEOUT;
unsigned int timer_base;
if (dev >= TIMER_NUMOF){
return -1;
}
return -1;
switch(dev){
#if TIMER_0_EN
case TIMER_0:
timer_base = WTIMER0_BASE;
break;
#endif
#if TIMER_1_EN
case TIMER_1:
timer_base = WTIMER1_BASE;
break;
#endif
default:
return -1; // unreachable
break;
}
ROM_TimerIntClear(timer_base, timer_intbit);
// WTIMER0_ICR_R = TIMER_ICR_TATOCINT;
return 1;
}
unsigned int timer_read(tim_t dev)
{
if (dev == TIMER_0) {
unsigned int currTimer0Val=0;
unsigned int loadTimer0Val=0;
currTimer0Val = (unsigned int)ROM_TimerValueGet(WTIMER0_BASE, TIMER_A);
loadTimer0Val = (unsigned int)ROM_TimerLoadGet(WTIMER0_BASE, TIMER_A);
DEBUG("WTIMER0_TAILR_R=0x%lx\t currTimer0Val=0x%x\t loadTimer0Val=0x%x\n", WTIMER0_TAILR_R, currTimer0Val, loadTimer0Val);
return (loadTimer0Val - currTimer0Val);
}
return 0;
unsigned int timer_base;
unsigned int timer_side = TIMER_A;
if (dev >= TIMER_NUMOF){
return -1;
}
switch(dev){
#if TIMER_0_EN
case TIMER_0:
timer_base = WTIMER0_BASE;
break;
#endif
#if TIMER_1_EN
case TIMER_1:
timer_base = WTIMER1_BASE;
break;
#endif
default:
return -1; // unreachable
break;
}
unsigned long long high_bits = ((unsigned long long)PRIV_TimerPrescaleSnapshotGet(timer_base, timer_side)) << 32;
unsigned long long low_bits = (unsigned long long)ROM_TimerValueGet(timer_base, timer_side);
unsigned long long total = high_bits + low_bits;
DEBUG("Combined %lx:%lx\n", (unsigned long) (total>>32), (unsigned long) (total & 0xFFFFFFFF));
unsigned int scaled_value = _llvalue_to_scaled_value(total, config[dev].diviser);
return scaled_value;
}
void timer_start(tim_t dev)
{
if (dev == TIMER_0) {
ROM_TimerEnable(WTIMER0_BASE, TIMER_A);
unsigned int timer_base;
unsigned int timer_side = TIMER_A;
if (dev >= TIMER_NUMOF){
return ;
}
switch(dev){
#if TIMER_0_EN
case TIMER_0:
timer_base = WTIMER0_BASE;
break;
#endif
#if TIMER_1_EN
case TIMER_1:
timer_base = WTIMER1_BASE;
break;
#endif
default:
return; // unreachable
}
ROM_TimerEnable(timer_base, timer_side);
}
void timer_stop(tim_t dev)
{
if (dev == TIMER_0) {
ROM_TimerDisable(WTIMER0_BASE, TIMER_A);
unsigned int timer_base;
unsigned int timer_side = TIMER_A;
if (dev >= TIMER_NUMOF){
return;
}
switch(dev){
#if TIMER_0_EN
case TIMER_0:
timer_base = WTIMER0_BASE;
break;
#endif
#if TIMER_1_EN
case TIMER_1:
timer_base = WTIMER1_BASE;
break;
#endif
default:
return; // unreachable
}
ROM_TimerDisable(timer_base, timer_side);
}
void timer_irq_enable(tim_t dev)
{
if (dev == TIMER_0) {
ROM_IntEnable(INT_WTIMER0A);
ROM_TimerIntEnable(WTIMER0_BASE, TIMER_TIMA_TIMEOUT);
}
if (dev >= TIMER_NUMOF){
return;
}
unsigned int timer_intbase;
switch(dev){
#if TIMER_0_EN
case TIMER_0:
timer_intbase = INT_WTIMER0A;
break;
#endif
#if TIMER_1_EN
case TIMER_1:
timer_intbase = INT_WTIMER1A;
break;
#endif
default:
return; // unreachable
}
ROM_IntPrioritySet(timer_intbase, 32);
ROM_IntEnable(timer_intbase);
}
void timer_irq_disable(tim_t dev)
{
if (dev == TIMER_0) {
ROM_IntDisable(INT_WTIMER0A);
}
if (dev >= TIMER_NUMOF){
return;
}
unsigned int timer_base;
unsigned int timer_intbit = TIMER_TIMA_TIMEOUT;
unsigned int timer_intbase;
switch(dev){
#if TIMER_0_EN
case TIMER_0:
timer_base = WTIMER0_BASE;
timer_intbase = INT_WTIMER0A;
break;
#endif
#if TIMER_1_EN
case TIMER_1:
timer_base = WTIMER1_BASE;
timer_intbase = INT_WTIMER1A;
break;
#endif
default:
return; // unreachable
}
ROM_IntEnable(timer_intbase);
ROM_TimerIntDisable(timer_base, timer_intbit);
}
void timer_reset(tim_t dev)
{
if (dev == TIMER_0) {
/* Performs a software reset of a peripheral */
ROM_SysCtlPeripheralReset(SYSCTL_PERIPH_WTIMER0);
if (dev >= TIMER_NUMOF){
return;
}
unsigned int sysctl_timer;
switch(dev){
#if TIMER_0_EN
case TIMER_0:
sysctl_timer = SYSCTL_PERIPH_WTIMER0;
break;
#endif
#if TIMER_1_EN
case TIMER_1:
sysctl_timer = SYSCTL_PERIPH_WTIMER1;
break;
#endif
default:
return; // unreachable
}
/* Performs a software reset of a peripheral */
ROM_SysCtlPeripheralReset(sysctl_timer);
}
#if TIMER_0_EN
void isr_timer0a(void)
void isr_wtimer0a(void)
{
TIMER0_ICR_R = TIMER_ICR_TATOCINT;
config[TIMER_0].cb(0);
// unsigned long status = ROM_TimerIntStatus(WTIMER0_BASE, TIMER_TIMA_TIMEOUT | TIMER_TIMA_MATCH);
// printf("Timeout : %lx, Match : %lx\n", status & TIMER_TIMA_TIMEOUT, status & TIMER_TIMA_MATCH);
// Clears both IT
ROM_TimerIntClear(WTIMER0_BASE, TIMER_TIMA_TIMEOUT | TIMER_TIMA_MATCH);
// WTIMER0_ICR_R = TIMER_ICR_TATOCINT;
config[TIMER_0].cb(0);
if (sched_context_switch_request){
thread_yield();
}
}
void isr_wtimer0a(void)
#endif /* TIMER_0_EN */
#if TIMER_1_EN
void isr_wtimer1a(void)
{
WTIMER0_ICR_R = TIMER_ICR_TATOCINT;
ROM_TimerIntClear(WTIMER1_BASE, TIMER_TIMA_TIMEOUT | TIMER_TIMA_MATCH);
// WTIMER0_ICR_R = TIMER_ICR_TATOCINT;
config[TIMER_0].cb(0);
config[TIMER_1].cb(0);
if (sched_context_switch_request){
thread_yield();
}
}
#endif /* TIMER_0_EN */
#endif /* TIMER_1_EN */
#endif /* TIMER_0_EN */
/** @} */

346
cpu/stellaris_common/include/cortex-m4-def.h

@ -73,133 +73,165 @@ extern "C" {
#define WATCHDOG1_TEST_R (*((volatile unsigned long *)0x40001418))
#define WATCHDOG1_LOCK_R (*((volatile unsigned long *)0x40001C00))
//*****************************************************************************
//
// GPIO registers offset
//
//*****************************************************************************
#define GPIO_DATA_R_OFF (0x3FCUL))
#define GPIO_DIR_R_OFF (0x400UL)
#define GPIO_IS_R_OFF (0x404UL)
#define GPIO_IBE_R_OFF (0x408UL)
#define GPIO_IEV_R_OFF (0x40CUL)
#define GPIO_IM_R_OFF (0x410UL)
#define GPIO_RIS_R_OFF (0x414UL)
#define GPIO_MIS_R_OFF (0x418UL)
#define GPIO_ICR_R_OFF (0x41CUL)
#define GPIO_AFSEL_R_OFF (0x420UL)
#define GPIO_DR2R_R_OFF (0x500UL)
#define GPIO_DR4R_R_OFF (0x504UL)
#define GPIO_DR8R_R_OFF (0x508UL)
#define GPIO_ODR_R_OFF (0x50CUL)
#define GPIO_PUR_R_OFF (0x510UL)
#define GPIO_PDR_R_OFF (0x514UL)
#define GPIO_SLR_R_OFF (0x518UL)
#define GPIO_DEN_R_OFF (0x51CUL)
#define GPIO_LOCK_R_OFF (0x520UL)
#define GPIO_CR_R_OFF (0x524UL)
#define GPIO_AMSEL_R_OFF (0x528UL)
#define GPIO_PCTL_R_OFF (0x52CUL)
#define GPIO_ADCCTL_R_OFF (0x530UL)
#define GPIO_DMACTL_R_OFF (0x534UL)
#define GPIO_SI_R_OFF (0x538UL)
//*****************************************************************************
//
// GPIO registers (PORTA)
//
//*****************************************************************************
#define GPIO_PORTA_DATA_BITS_R ((volatile unsigned long *)0x40004000)
#define GPIO_PORTA_DATA_R (*((volatile unsigned long *)0x400043FC))
#define GPIO_PORTA_DIR_R (*((volatile unsigned long *)0x40004400))
#define GPIO_PORTA_IS_R (*((volatile unsigned long *)0x40004404))
#define GPIO_PORTA_IBE_R (*((volatile unsigned long *)0x40004408))
#define GPIO_PORTA_IEV_R (*((volatile unsigned long *)0x4000440C))
#define GPIO_PORTA_IM_R (*((volatile unsigned long *)0x40004410))
#define GPIO_PORTA_RIS_R (*((volatile unsigned long *)0x40004414))
#define GPIO_PORTA_MIS_R (*((volatile unsigned long *)0x40004418))
#define GPIO_PORTA_ICR_R (*((volatile unsigned long *)0x4000441C))
#define GPIO_PORTA_AFSEL_R (*((volatile unsigned long *)0x40004420))
#define GPIO_PORTA_DR2R_R (*((volatile unsigned long *)0x40004500))
#define GPIO_PORTA_DR4R_R (*((volatile unsigned long *)0x40004504))
#define GPIO_PORTA_DR8R_R (*((volatile unsigned long *)0x40004508))
#define GPIO_PORTA_ODR_R (*((volatile unsigned long *)0x4000450C))
#define GPIO_PORTA_PUR_R (*((volatile unsigned long *)0x40004510))
#define GPIO_PORTA_PDR_R (*((volatile unsigned long *)0x40004514))
#define GPIO_PORTA_SLR_R (*((volatile unsigned long *)0x40004518))
#define GPIO_PORTA_DEN_R (*((volatile unsigned long *)0x4000451C))
#define GPIO_PORTA_LOCK_R (*((volatile unsigned long *)0x40004520))
#define GPIO_PORTA_CR_R (*((volatile unsigned long *)0x40004524))
#define GPIO_PORTA_AMSEL_R (*((volatile unsigned long *)0x40004528))
#define GPIO_PORTA_PCTL_R (*((volatile unsigned long *)0x4000452C))
#define GPIO_PORTA_ADCCTL_R (*((volatile unsigned long *)0x40004530))
#define GPIO_PORTA_DMACTL_R (*((volatile unsigned long *)0x40004534))
#define GPIO_PORTA_SI_R (*((volatile unsigned long *)0x40004538))
#define GPIO_PORTA_DATA_BITS_R ((volatile unsigned long *) GPIO_PORTA_BASE)
#define GPIO_PORTA_DATA_R (*((volatile unsigned long *)(GPIO_PORTA_BASE + GPIO_DATA_R_OFF)))
#define GPIO_PORTA_DIR_R (*((volatile unsigned long *)(GPIO_PORTA_BASE + GPIO_DIR_R_OFF)))
#define GPIO_PORTA_IS_R (*((volatile unsigned long *)(GPIO_PORTA_BASE + GPIO_DIR_R_OFF)))
#define GPIO_PORTA_IBE_R (*((volatile unsigned long *)(GPIO_PORTA_BASE + GPIO_IBE_R_OFF)))
#define GPIO_PORTA_IEV_R (*((volatile unsigned long *)(GPIO_PORTA_BASE + GPIO_IEV_R_OFF)))
#define GPIO_PORTA_IM_R (*((volatile unsigned long *)(GPIO_PORTA_BASE + GPIO_IM_R_OFF)))
#define GPIO_PORTA_RIS_R (*((volatile unsigned long *)(GPIO_PORTA_BASE + GPIO_R_OFF)))
#define GPIO_PORTA_MIS_R (*((volatile unsigned long *)(GPIO_PORTA_BASE + GPIO_MIS_R_OFF)))
#define GPIO_PORTA_ICR_R (*((volatile unsigned long *)(GPIO_PORTA_BASE + GPIO_ICR_R_OFF)))
#define GPIO_PORTA_AFSEL_R (*((volatile unsigned long *)(GPIO_PORTA_BASE + GPIO_AFSEL_R_OFF)))
#define GPIO_PORTA_DR2R_R (*((volatile unsigned long *)(GPIO_PORTA_BASE + GPIO_DR2R_R_OFF)))
#define GPIO_PORTA_DR4R_R (*((volatile unsigned long *)(GPIO_PORTA_BASE + GPIO_DR4R_R_OFF)))
#define GPIO_PORTA_DR8R_R (*((volatile unsigned long *)(GPIO_PORTA_BASE + GPIO_DR8R_R_OFF)))
#define GPIO_PORTA_ODR_R (*((volatile unsigned long *)(GPIO_PORTA_BASE + GPIO_ODR_R_OFF)))
#define GPIO_PORTA_PUR_R (*((volatile unsigned long *)(GPIO_PORTA_BASE + GPIO_PUR_R_OFF)))
#define GPIO_PORTA_PDR_R (*((volatile unsigned long *)(GPIO_PORTA_BASE + GPIO_PDR_R_OFF)))
#define GPIO_PORTA_SLR_R (*((volatile unsigned long *)(GPIO_PORTA_BASE + GPIO_SLR_R_OFF)))
#define GPIO_PORTA_DEN_R (*((volatile unsigned long *)(GPIO_PORTA_BASE + GPIO_DEN_R_OFF)))
#define GPIO_PORTA_LOCK_R (*((volatile unsigned long *)(GPIO_PORTA_BASE + GPIO_LOCK_R_OFF)))
#define GPIO_PORTA_CR_R (*((volatile unsigned long *)(GPIO_PORTA_BASE + GPIO_CR_R_OFF)))
#define GPIO_PORTA_AMSEL_R (*((volatile unsigned long *)(GPIO_PORTA_BASE + GPIO_AMSEL_R_OFF)))
#define GPIO_PORTA_PCTL_R (*((volatile unsigned long *)(GPIO_PORTA_BASE + GPIO_PCTL_R_OFF)))
#define GPIO_PORTA_ADCCTL_R (*((volatile unsigned long *)(GPIO_PORTA_BASE + GPIO_ADCCTL_R_OFF)))
#define GPIO_PORTA_DMACTL_R (*((volatile unsigned long *)(GPIO_PORTA_BASE + GPIO_DMACTL_R_OFF)))
#define GPIO_PORTA_SI_R (*((volatile unsigned long *)(GPIO_PORTA_BASE + GPIO_SI_R_OFF)))
//*****************************************************************************
//
// GPIO registers (PORTB)
//
//*****************************************************************************
#define GPIO_PORTB_DATA_BITS_R ((volatile unsigned long *)0x40005000)
#define GPIO_PORTB_DATA_R (*((volatile unsigned long *)0x400053FC))
#define GPIO_PORTB_DIR_R (*((volatile unsigned long *)0x40005400))
#define GPIO_PORTB_IS_R (*((volatile unsigned long *)0x40005404))
#define GPIO_PORTB_IBE_R (*((volatile unsigned long *)0x40005408))
#define GPIO_PORTB_IEV_R (*((volatile unsigned long *)0x4000540C))
#define GPIO_PORTB_IM_R (*((volatile unsigned long *)0x40005410))
#define GPIO_PORTB_RIS_R (*((volatile unsigned long *)0x40005414))
#define GPIO_PORTB_MIS_R (*((volatile unsigned long *)0x40005418))
#define GPIO_PORTB_ICR_R (*((volatile unsigned long *)0x4000541C))
#define GPIO_PORTB_AFSEL_R (*((volatile unsigned long *)0x40005420))
#define GPIO_PORTB_DR2R_R (*((volatile unsigned long *)0x40005500))
#define GPIO_PORTB_DR4R_R (*((volatile unsigned long *)0x40005504))
#define GPIO_PORTB_DR8R_R (*((volatile unsigned long *)0x40005508))
#define GPIO_PORTB_ODR_R (*((volatile unsigned long *)0x4000550C))
#define GPIO_PORTB_PUR_R (*((volatile unsigned long *)0x40005510))
#define GPIO_PORTB_PDR_R (*((volatile unsigned long *)0x40005514))
#define GPIO_PORTB_SLR_R (*((volatile unsigned long *)0x40005518))
#define GPIO_PORTB_DEN_R (*((volatile unsigned long *)0x4000551C))
#define GPIO_PORTB_LOCK_R (*((volatile unsigned long *)0x40005520))
#define GPIO_PORTB_CR_R (*((volatile unsigned long *)0x40005524))
#define GPIO_PORTB_AMSEL_R (*((volatile unsigned long *)0x40005528))
#define GPIO_PORTB_PCTL_R (*((volatile unsigned long *)0x4000552C))
#define GPIO_PORTB_ADCCTL_R (*((volatile unsigned long *)0x40005530))
#define GPIO_PORTB_DMACTL_R (*((volatile unsigned long *)0x40005534))
#define GPIO_PORTB_SI_R (*((volatile unsigned long *)0x40005538))
#define GPIO_PORTB_DATA_BITS_R ((volatile unsigned long *) GPIO_PORTB_BASE)
#define GPIO_PORTB_DATA_R (*((volatile unsigned long *)(GPIO_PORTB_BASE + GPIO_DATA_R_OFF)))
#define GPIO_PORTB_DIR_R (*((volatile unsigned long *)(GPIO_PORTB_BASE + GPIO_DIR_R_OFF)))