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104 lines
3.4 KiB
104 lines
3.4 KiB
/* |
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* Copyright (C) 2014 Freie Universität Berlin |
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* |
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* This file is subject to the terms and conditions of the GNU Lesser General |
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* Public License v2.1. See the file LICENSE in the top level directory for more |
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* details. |
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*/ |
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/** |
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* @ingroup cpu_stm32l1 |
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* @{ |
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* |
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* @file |
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* @brief Implementation of the kernel cpu functions |
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* |
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* @author Thomas Eichinger <thomas.eichinger@fu-berlin.de> |
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* @author Nick van IJzendoorn <nijzendoorn@engineering-spirit.nl> |
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* |
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* @} |
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*/ |
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#include "cpu.h" |
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#include "board.h" |
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#include "periph_conf.h" |
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#include "periph/init.h" |
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/* Check the source to be used for the PLL */ |
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#if defined(CLOCK_HSI) && defined(CLOCK_HSE) |
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#error "Only provide one of two CLOCK_HSI/CLOCK_HSE" |
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#elif CLOCK_HSI |
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#define CLOCK_CR_SOURCE RCC_CR_HSION |
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#define CLOCK_CR_SOURCE_RDY RCC_CR_HSIRDY |
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#define CLOCK_PLL_SOURCE RCC_CFGR_PLLSRC_HSI |
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#elif CLOCK_HSE |
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#define CLOCK_CR_SOURCE RCC_CR_HSEON |
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#define CLOCK_CR_SOURCE_RDY RCC_CR_HSERDY |
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#define CLOCK_PLL_SOURCE RCC_CFGR_PLLSRC_HSE |
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#else |
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#error "Please provide CLOCK_HSI or CLOCK_HSE in boards/NAME/includes/perhip_cpu.h" |
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#endif |
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static void clk_init(void); |
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void cpu_init(void) |
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{ |
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/* initialize the Cortex-M core */ |
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cortexm_init(); |
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/* initialize system clocks */ |
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clk_init(); |
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/* trigger static peripheral initialization */ |
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periph_init(); |
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} |
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/** |
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* @brief Configure the clock system of the stm32f1 |
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*/ |
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static void clk_init(void) |
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{ |
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/* Reset the RCC clock configuration to the default reset state(for debug purpose) */ |
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/* Set MSION bit */ |
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RCC->CR |= RCC_CR_MSION; |
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/* Reset SW, HPRE, PPRE1, PPRE2, MCOSEL and MCOPRE bits */ |
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RCC->CFGR &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLDIV | RCC_CFGR_PLLMUL); |
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/* Reset HSION, HSEON, CSSON and PLLON bits */ |
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RCC->CR &= ~(RCC_CR_HSION | RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_CSSON | RCC_CR_PLLON); |
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/* Disable all interrupts */ |
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RCC->CIR = 0x0; |
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/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration */ |
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/* Enable high speed clock source */ |
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RCC->CR |= CLOCK_CR_SOURCE; |
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/* Wait till the high speed clock source is ready |
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* NOTE: the MCU will stay here forever if you use an external clock source and it's not connected */ |
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while (!(RCC->CR & CLOCK_CR_SOURCE_RDY)) {} |
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FLASH->ACR |= FLASH_ACR_ACC64; |
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/* Enable Prefetch Buffer */ |
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FLASH->ACR |= FLASH_ACR_PRFTEN; |
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/* Flash 1 wait state */ |
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FLASH->ACR |= CLOCK_FLASH_LATENCY; |
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/* Power enable */ |
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periph_clk_en(APB1, RCC_APB1ENR_PWREN); |
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/* Select the Voltage Range 1 (1.8 V) */ |
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PWR->CR = PWR_CR_VOS_0; |
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/* Wait Until the Voltage Regulator is ready */ |
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while((PWR->CSR & PWR_CSR_VOSF) != 0) {} |
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/* HCLK = SYSCLK */ |
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RCC->CFGR |= (uint32_t)CLOCK_AHB_DIV; |
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/* PCLK2 = HCLK */ |
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RCC->CFGR |= (uint32_t)CLOCK_APB2_DIV; |
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/* PCLK1 = HCLK */ |
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RCC->CFGR |= (uint32_t)CLOCK_APB1_DIV; |
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/* PLL configuration: PLLCLK = CLOCK_SOURCE / PLL_DIV * PLL_MUL */ |
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RCC->CFGR &= ~((uint32_t)(RCC_CFGR_PLLSRC | RCC_CFGR_PLLDIV | RCC_CFGR_PLLMUL)); |
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RCC->CFGR |= (uint32_t)(CLOCK_PLL_SOURCE | CLOCK_PLL_DIV | CLOCK_PLL_MUL); |
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/* Enable PLL */ |
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RCC->CR |= RCC_CR_PLLON; |
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/* Wait till PLL is ready */ |
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while ((RCC->CR & RCC_CR_PLLRDY) == 0) {} |
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/* Select PLL as system clock source */ |
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RCC->CFGR &= ~((uint32_t)(RCC_CFGR_SW)); |
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RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; |
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/* Wait till PLL is used as system clock source */ |
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while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) {} |
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}
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