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6675 lines
482 KiB
C
6675 lines
482 KiB
C
/**
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******************************************************************************
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* @file stm32l1xx.h
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* @author MCD Application Team
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* @version V1.3.2
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* @date 10-April-2014
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* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
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* This file contains all the peripheral register's definitions, bits
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* definitions and memory mapping for STM32L1xx High-density, Medium-density,
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* Medium-density and XL-density Plus devices.
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*
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* The file is the unique include file that the application programmer
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* is using in the C source code, usually in main.c. This file contains:
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* - Configuration section that allows to select:
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* - The device used in the target application
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* - To use or not the peripheralís drivers in application code(i.e.
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* code will be based on direct access to peripheralís registers
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* rather than drivers API), this option is controlled by
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* "#define USE_STDPERIPH_DRIVER"
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* - To change few application-specific parameters such as the HSE
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* crystal frequency
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* - Data structures and the address mapping for all peripherals
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* - Peripheral's registers declarations and bits definition
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* - Macros to access peripheralís registers hardware
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*
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
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*
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* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
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* You may not use this file except in compliance with the License.
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* You may obtain a copy of the License at:
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*
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* http://www.st.com/software_license_agreement_liberty_v2
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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******************************************************************************
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*/
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/** @addtogroup CMSIS
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* @{
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*/
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/** @addtogroup cpu_specific_stm32l1xx
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* @{
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*/
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#ifndef STM32L1XX_H
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#define STM32L1XX_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @addtogroup cpu_specific_Library_configuration_section
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* @{
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*/
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/* Uncomment the line below according to the target STM32L device used in your
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application
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*/
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#if !defined (STM32L1XX_MD) && !defined (STM32L1XX_MDP) && !defined (STM32L1XX_HD) && !defined (STM32L1XX_XL)
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/* #define STM32L1XX_MD */ /*!< - Ultra Low Power Medium-density devices: STM32L151x6xx, STM32L151x8xx,
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STM32L151xBxx, STM32L152x6xx, STM32L152x8xx, STM32L152xBxx,
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STM32L151x6xxA, STM32L151x8xxA, STM32L151xBxxA, STM32L152x6xxA,
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STM32L152x8xxA and STM32L152xBxxA.
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- Ultra Low Power Medium-density Value Line devices: STM32L100x6xx,
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STM32L100x8xx and STM32L100xBxx. */
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/* #define STM32L1XX_MDP */ /*!< - Ultra Low Power Medium-density Plus devices: STM32L151xCxx, STM32L152xCxx and STM32L162xCxx
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- Ultra Low Power Medium-density Plus Value Line devices: STM32L100xCxx */
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/* #define STM32L1XX_HD */ /*!< Ultra Low Power High-density devices: STM32L151xDxx, STM32L152xDxx and STM32L162xDxx */
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/* #define STM32L1XX_XL */ /*!< Ultra Low Power XL-density devices: STM32L151xExx, STM32L152xExx and STM32L162xExx */
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#endif
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/* Tip: To avoid modifying this file each time you need to switch between these
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devices, you can define the device in your toolchain compiler preprocessor.
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*/
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#define STM32L1XX_XL (1U)
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#if !defined (STM32L1XX_MD) && !defined (STM32L1XX_MDP) && !defined (STM32L1XX_HD) && !defined (STM32L1XX_XL)
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#error "Please select first the target STM32L1xx device used in your application (in stm32l1xx.h file)"
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#endif
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#if !defined USE_STDPERIPH_DRIVER
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/**
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* @brief Comment the line below if you will not use the peripherals drivers.
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In this case, these drivers will not be included and the application code will
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be based on direct access to peripherals registers
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*/
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/*#define USE_STDPERIPH_DRIVER*/
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#endif
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/**
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* @brief In the following line adjust the value of External High Speed oscillator (HSE)
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used in your application
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Tip: To avoid modifying this file each time you need to use different HSE, you
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can define the HSE value in your toolchain compiler preprocessor.
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*/
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#if !defined (HSE_VALUE)
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#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
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#endif
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/**
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* @brief In the following line adjust the External High Speed oscillator (HSE) Startup
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Timeout value
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*/
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#if !defined (HSE_STARTUP_TIMEOUT)
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#define HSE_STARTUP_TIMEOUT ((uint16_t)0x5000) /*!< Time out for HSE start up */
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#endif
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/**
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* @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
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Timeout value
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*/
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#if !defined (HSI_STARTUP_TIMEOUT)
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#define HSI_STARTUP_TIMEOUT ((uint16_t)0x5000) /*!< Time out for HSI start up */
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#endif
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#if !defined (HSI_VALUE)
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#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal High Speed oscillator in Hz.
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The real value may vary depending on the variations
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in voltage and temperature. */
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#endif
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#if !defined (LSI_VALUE)
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#define LSI_VALUE ((uint32_t)37000) /*!< Value of the Internal Low Speed oscillator in Hz
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The real value may vary depending on the variations
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in voltage and temperature. */
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#endif
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#if !defined (LSE_VALUE)
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#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */
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#endif
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/**
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* @brief STM32L1xx Standard Peripheral Library version number V1.3.2
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*/
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#define __STM32L1XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */
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#define __STM32L1XX_STDPERIPH_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
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#define __STM32L1XX_STDPERIPH_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
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#define __STM32L1XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
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#define __STM32L1XX_STDPERIPH_VERSION ( (__STM32L1XX_STDPERIPH_VERSION_MAIN << 24)\
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|(__STM32L1XX_STDPERIPH_VERSION_SUB1 << 16)\
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|(__STM32L1XX_STDPERIPH_VERSION_SUB2 << 8)\
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|(__STM32L1XX_STDPERIPH_VERSION_RC))
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/**
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* @}
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*/
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/** @addtogroup Configuration_section_for_CMSIS
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* @{
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*/
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/**
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* @brief STM32L1xx Interrupt Number Definition, according to the selected device
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* in @ref Library_configuration_section
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*/
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#define __CM3_REV 0x200 /*!< Cortex-M3 Revision r2p0 */
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#define __MPU_PRESENT 1 /*!< STM32L1 provides MPU */
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#define __NVIC_PRIO_BITS 4 /*!< STM32L1 uses 4 Bits for the Priority Levels */
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#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
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/*!< Interrupt Number Definition */
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typedef enum IRQn
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{
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/****** Cortex-M3 Processor Exceptions Numbers ******************************************************/
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NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
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MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
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BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
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UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
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SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
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DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
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PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
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SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
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/****** STM32L specific Interrupt Numbers ***********************************************************/
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WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
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PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
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TAMPER_STAMP_IRQn = 2, /*!< Tamper and Time Stamp through EXTI Line Interrupts */
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RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Timer through EXTI Line Interrupt */
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FLASH_IRQn = 4, /*!< FLASH global Interrupt */
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RCC_IRQn = 5, /*!< RCC global Interrupt */
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EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
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EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
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EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
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EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
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EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
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DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
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DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
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DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
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DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
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DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
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DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
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DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
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ADC1_IRQn = 18, /*!< ADC1 global Interrupt */
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USB_HP_IRQn = 19, /*!< USB High Priority Interrupt */
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USB_LP_IRQn = 20, /*!< USB Low Priority Interrupt */
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DAC_IRQn = 21, /*!< DAC Interrupt */
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COMP_IRQn = 22, /*!< Comparator through EXTI Line Interrupt */
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EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
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LCD_IRQn = 24, /*!< LCD Interrupt */
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TIM9_IRQn = 25, /*!< TIM9 global Interrupt */
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TIM10_IRQn = 26, /*!< TIM10 global Interrupt */
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TIM11_IRQn = 27, /*!< TIM11 global Interrupt */
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TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
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TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
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TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
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I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
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I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
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I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
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I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
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SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
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SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
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USART1_IRQn = 37, /*!< USART1 global Interrupt */
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USART2_IRQn = 38, /*!< USART2 global Interrupt */
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USART3_IRQn = 39, /*!< USART3 global Interrupt */
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EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
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RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
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USB_FS_WKUP_IRQn = 42, /*!< USB FS WakeUp from suspend through EXTI Line Interrupt */
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TIM6_IRQn = 43, /*!< TIM6 global Interrupt */
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#ifdef STM32L1XX_MD
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TIM7_IRQn = 44 /*!< TIM7 global Interrupt */
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#endif /* STM32L1XX_MD */
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#ifdef STM32L1XX_MDP
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TIM7_IRQn = 44, /*!< TIM7 global Interrupt */
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TIM5_IRQn = 46, /*!< TIM5 global Interrupt */
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SPI3_IRQn = 47, /*!< SPI3 global Interrupt */
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DMA2_Channel1_IRQn = 50, /*!< DMA2 Channel 1 global Interrupt */
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DMA2_Channel2_IRQn = 51, /*!< DMA2 Channel 2 global Interrupt */
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DMA2_Channel3_IRQn = 52, /*!< DMA2 Channel 3 global Interrupt */
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DMA2_Channel4_IRQn = 53, /*!< DMA2 Channel 4 global Interrupt */
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DMA2_Channel5_IRQn = 54, /*!< DMA2 Channel 5 global Interrupt */
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AES_IRQn = 55, /*!< AES global Interrupt */
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COMP_ACQ_IRQn = 56 /*!< Comparator Channel Acquisition global Interrupt */
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#endif /* STM32L1XX_MDP */
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#ifdef STM32L1XX_HD
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TIM7_IRQn = 44, /*!< TIM7 global Interrupt */
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SDIO_IRQn = 45, /*!< SDIO global Interrupt */
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TIM5_IRQn = 46, /*!< TIM5 global Interrupt */
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SPI3_IRQn = 47, /*!< SPI3 global Interrupt */
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UART4_IRQn = 48, /*!< UART4 global Interrupt */
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UART5_IRQn = 49, /*!< UART5 global Interrupt */
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DMA2_Channel1_IRQn = 50, /*!< DMA2 Channel 1 global Interrupt */
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DMA2_Channel2_IRQn = 51, /*!< DMA2 Channel 2 global Interrupt */
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DMA2_Channel3_IRQn = 52, /*!< DMA2 Channel 3 global Interrupt */
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DMA2_Channel4_IRQn = 53, /*!< DMA2 Channel 4 global Interrupt */
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DMA2_Channel5_IRQn = 54, /*!< DMA2 Channel 5 global Interrupt */
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AES_IRQn = 55, /*!< AES global Interrupt */
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COMP_ACQ_IRQn = 56 /*!< Comparator Channel Acquisition global Interrupt */
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#endif /* STM32L1XX_HD */
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#ifdef STM32L1XX_XL
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TIM7_IRQn = 44, /*!< TIM7 global Interrupt */
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TIM5_IRQn = 46, /*!< TIM5 global Interrupt */
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SPI3_IRQn = 47, /*!< SPI3 global Interrupt */
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UART4_IRQn = 48, /*!< UART4 global Interrupt */
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UART5_IRQn = 49, /*!< UART5 global Interrupt */
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DMA2_Channel1_IRQn = 50, /*!< DMA2 Channel 1 global Interrupt */
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DMA2_Channel2_IRQn = 51, /*!< DMA2 Channel 2 global Interrupt */
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DMA2_Channel3_IRQn = 52, /*!< DMA2 Channel 3 global Interrupt */
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DMA2_Channel4_IRQn = 53, /*!< DMA2 Channel 4 global Interrupt */
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DMA2_Channel5_IRQn = 54, /*!< DMA2 Channel 5 global Interrupt */
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AES_IRQn = 55, /*!< AES global Interrupt */
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COMP_ACQ_IRQn = 56 /*!< Comparator Channel Acquisition global Interrupt */
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#endif /* STM32L1XX_XL */
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} IRQn_Type;
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/**
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* @}
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*/
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#include "core_cm3.h"
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// #include "system_stm32l1xx.h"
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#include <stdint.h>
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/** @addtogroup cpu_specific_Exported_types
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* @{
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*/
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typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
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typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
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#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
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typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
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/**
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* @brief __RAM_FUNC definition
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*/
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#if defined ( __CC_ARM )
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/* ARM Compiler
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------------
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RAM functions are defined using the toolchain options.
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Functions that are executed in RAM should reside in a separate source module.
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Using the 'Options for File' dialog you can simply change the 'Code / Const'
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area of a module to a memory space in physical RAM.
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Available memory areas are declared in the 'Target' tab of the 'Options for Target'
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dialog.
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*/
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#define __RAM_FUNC FLASH_Status
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#elif defined ( __ICCARM__ )
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/* ICCARM Compiler
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---------------
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RAM functions are defined using a specific toolchain keyword "__ramfunc".
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*/
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#define __RAM_FUNC __ramfunc FLASH_Status
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#elif defined ( __GNUC__ )
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/* GNU Compiler
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------------
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RAM functions are defined using a specific toolchain attribute
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"__attribute__((section(".RamFunc")))".
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*/
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#define __RAM_FUNC FLASH_Status __attribute__((section(".RamFunc")))
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#elif defined ( __TASKING__ )
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/* TASKING Compiler
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----------------
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RAM functions are defined using a specific toolchain pragma. This pragma is
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defined in the stm32l1xx_flash_ramfunc.c
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*/
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#define __RAM_FUNC FLASH_Status
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#endif
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/**
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* @}
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*/
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/** @addtogroup cpu_specific_Peripheral_registers_structures
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* @{
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*/
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/**
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* @brief Analog to Digital Converter
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*/
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typedef struct
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{
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__IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
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__IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
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__IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
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__IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
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__IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
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__IO uint32_t SMPR3; /*!< ADC sample time register 3, Address offset: 0x14 */
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__IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x18 */
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__IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x1C */
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__IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x20 */
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__IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x24 */
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__IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x28 */
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__IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x2C */
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__IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
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__IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
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__IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
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__IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
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__IO uint32_t SQR5; /*!< ADC regular sequence register 5, Address offset: 0x40 */
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__IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x44 */
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__IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x48 */
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__IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x4C */
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__IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x50 */
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__IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x54 */
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__IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x58 */
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__IO uint32_t SMPR0; /*!< ADC sample time register 0, Address offset: 0x5C */
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} ADC_TypeDef;
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typedef struct
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{
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__IO uint32_t CSR; /*!< ADC common status register, Address offset: ADC1 base address + 0x300 */
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__IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
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} ADC_Common_TypeDef;
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/**
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* @brief AES hardware accelerator
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*/
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typedef struct
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{
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__IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */
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__IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */
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__IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */
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__IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */
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__IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */
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__IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */
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__IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */
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__IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */
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__IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */
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__IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */
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__IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */
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__IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */
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} AES_TypeDef;
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/**
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* @brief Comparator
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*/
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typedef struct
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{
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__IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x00 */
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} COMP_TypeDef;
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/**
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* @brief CRC calculation unit
|
|
*/
|
|
|
|
typedef struct
|
|
{
|
|
__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
|
|
__IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
|
|
uint8_t RESERVED0; /*!< Reserved, 0x05 */
|
|
uint16_t RESERVED1; /*!< Reserved, 0x06 */
|
|
__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
|
|
} CRC_TypeDef;
|
|
|
|
/**
|
|
* @brief Digital to Analog Converter
|
|
*/
|
|
|
|
typedef struct
|
|
{
|
|
__IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
|
|
__IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
|
|
__IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
|
|
__IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
|
|
__IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
|
|
__IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
|
|
__IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
|
|
__IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
|
|
__IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
|
|
__IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
|
|
__IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
|
|
__IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
|
|
__IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
|
|
__IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
|
|
} DAC_TypeDef;
|
|
|
|
/**
|
|
* @brief Debug MCU
|
|
*/
|
|
|
|
typedef struct
|
|
{
|
|
__IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
|
|
__IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
|
|
__IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
|
|
__IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
|
|
}DBGMCU_TypeDef;
|
|
|
|
/**
|
|
* @brief DMA Controller
|
|
*/
|
|
|
|
typedef struct
|
|
{
|
|
__IO uint32_t CCR; /*!< DMA channel x configuration register */
|
|
__IO uint32_t CNDTR; /*!< DMA channel x number of data register */
|
|
__IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
|
|
__IO uint32_t CMAR; /*!< DMA channel x memory address register */
|
|
} DMA_Channel_TypeDef;
|
|
|
|
typedef struct
|
|
{
|
|
__IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
|
|
__IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
|
|
} DMA_TypeDef;
|
|
|
|
/**
|
|
* @brief External Interrupt/Event Controller
|
|
*/
|
|
|
|
typedef struct
|
|
{
|
|
__IO uint32_t IMR; /*!< EXTI interrupt mask register, Address offset: 0x00 */
|
|
__IO uint32_t EMR; /*!< EXTI event mask register, Address offset: 0x04 */
|
|
__IO uint32_t RTSR; /*!< EXTI rising edge trigger selection register, Address offset: 0x08 */
|
|
__IO uint32_t FTSR; /*!< EXTI Falling edge trigger selection register, Address offset: 0x0C */
|
|
__IO uint32_t SWIER; /*!< EXTI software interrupt event register, Address offset: 0x10 */
|
|
__IO uint32_t PR; /*!< EXTI pending register, Address offset: 0x14 */
|
|
} EXTI_TypeDef;
|
|
|
|
/**
|
|
* @brief FLASH Registers
|
|
*/
|
|
|
|
typedef struct
|
|
{
|
|
__IO uint32_t ACR; /*!< Access control register, Address offset: 0x00 */
|
|
__IO uint32_t PECR; /*!< Program/erase control register, Address offset: 0x04 */
|
|
__IO uint32_t PDKEYR; /*!< Power down key register, Address offset: 0x08 */
|
|
__IO uint32_t PEKEYR; /*!< Program/erase key register, Address offset: 0x0c */
|
|
__IO uint32_t PRGKEYR; /*!< Program memory key register, Address offset: 0x10 */
|
|
__IO uint32_t OPTKEYR; /*!< Option byte key register, Address offset: 0x14 */
|
|
__IO uint32_t SR; /*!< Status register, Address offset: 0x18 */
|
|
__IO uint32_t OBR; /*!< Option byte register, Address offset: 0x1c */
|
|
__IO uint32_t WRPR; /*!< Write protection register, Address offset: 0x20 */
|
|
uint32_t RESERVED[23]; /*!< Reserved, 0x24 */
|
|
__IO uint32_t WRPR1; /*!< Write protection register 1, Address offset: 0x28 */
|
|
__IO uint32_t WRPR2; /*!< Write protection register 2, Address offset: 0x2C */
|
|
} FLASH_TypeDef;
|
|
|
|
/**
|
|
* @brief Option Bytes Registers
|
|
*/
|
|
|
|
typedef struct
|
|
{
|
|
__IO uint32_t RDP; /*!< Read protection register, Address offset: 0x00 */
|
|
__IO uint32_t USER; /*!< user register, Address offset: 0x04 */
|
|
__IO uint32_t WRP01; /*!< write protection register 0 1, Address offset: 0x08 */
|
|
__IO uint32_t WRP23; /*!< write protection register 2 3, Address offset: 0x0C */
|
|
__IO uint32_t WRP45; /*!< write protection register 4 5, Address offset: 0x10 */
|
|
__IO uint32_t WRP67; /*!< write protection register 6 7, Address offset: 0x14 */
|
|
__IO uint32_t WRP89; /*!< write protection register 8 9, Address offset: 0x18 */
|
|
__IO uint32_t WRP1011; /*!< write protection register 10 11, Address offset: 0x1C */
|
|
} OB_TypeDef;
|
|
|
|
/**
|
|
* @brief Operational Amplifier (OPAMP)
|
|
*/
|
|
|
|
typedef struct
|
|
{
|
|
__IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */
|
|
__IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */
|
|
__IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
|
|
} OPAMP_TypeDef;
|
|
|
|
/**
|
|
* @brief Flexible Static Memory Controller
|
|
*/
|
|
|
|
typedef struct
|
|
{
|
|
__IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
|
|
} FSMC_Bank1_TypeDef;
|
|
|
|
/**
|
|
* @brief Flexible Static Memory Controller Bank1E
|
|
*/
|
|
|
|
typedef struct
|
|
{
|
|
__IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
|
|
} FSMC_Bank1E_TypeDef;
|
|
|
|
/**
|
|
* @brief General Purpose IO
|
|
*/
|
|
|
|
typedef struct
|
|
{
|
|
__IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
|
|
__IO uint16_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
|
|
uint16_t RESERVED0; /*!< Reserved, 0x06 */
|
|
__IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
|
|
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
|
|
__IO uint16_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
|
|
uint16_t RESERVED1; /*!< Reserved, 0x12 */
|
|
__IO uint16_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
|
|
uint16_t RESERVED2; /*!< Reserved, 0x16 */
|
|
__IO uint16_t BSRRL; /*!< GPIO port bit set/reset low registerBSRR, Address offset: 0x18 */
|
|
__IO uint16_t BSRRH; /*!< GPIO port bit set/reset high registerBSRR, Address offset: 0x1A */
|
|
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
|
|
__IO uint32_t AFR[2]; /*!< GPIO alternate function low register, Address offset: 0x20-0x24 */
|
|
#if defined (STM32L1XX_HD) || defined (STM32L1XX_XL)
|
|
__IO uint16_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
|
|
uint16_t RESERVED3; /*!< Reserved, 0x2A */
|
|
#endif
|
|
} GPIO_TypeDef;
|
|
|
|
/**
|
|
* @brief SysTem Configuration
|
|
*/
|
|
|
|
typedef struct
|
|
{
|
|
__IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
|
|
__IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
|
|
__IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
|
|
} SYSCFG_TypeDef;
|
|
|
|
/**
|
|
* @brief Inter-integrated Circuit Interface
|
|
*/
|
|
|
|
typedef struct
|
|
{
|
|
__IO uint16_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
|
|
uint16_t RESERVED0; /*!< Reserved, 0x02 */
|
|
__IO uint16_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
|
|
uint16_t RESERVED1; /*!< Reserved, 0x06 */
|
|
__IO uint16_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
|
|
uint16_t RESERVED2; /*!< Reserved, 0x0A */
|
|
__IO uint16_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
|
|
uint16_t RESERVED3; /*!< Reserved, 0x0E */
|
|
__IO uint16_t DR; /*!< I2C Data register, Address offset: 0x10 */
|
|
uint16_t RESERVED4; /*!< Reserved, 0x12 */
|
|
__IO uint16_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
|
|
uint16_t RESERVED5; /*!< Reserved, 0x16 */
|
|
__IO uint16_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
|
|
uint16_t RESERVED6; /*!< Reserved, 0x1A */
|
|
__IO uint16_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
|
|
uint16_t RESERVED7; /*!< Reserved, 0x1E */
|
|
__IO uint16_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
|
|
uint16_t RESERVED8; /*!< Reserved, 0x22 */
|
|
} I2C_TypeDef;
|
|
|
|
/**
|
|
* @brief Independent WATCHDOG
|
|
*/
|
|
|
|
typedef struct
|
|
{
|
|
__IO uint32_t KR; /*!< Key register, Address offset: 0x00 */
|
|
__IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */
|
|
__IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */
|
|
__IO uint32_t SR; /*!< Status register, Address offset: 0x0C */
|
|
} IWDG_TypeDef;
|
|
|
|
|
|
/**
|
|
* @brief LCD
|
|
*/
|
|
|
|
typedef struct
|
|
{
|
|
__IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */
|
|
__IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */
|
|
__IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */
|
|
__IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */
|
|
uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */
|
|
__IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */
|
|
} LCD_TypeDef;
|
|
|
|
/**
|
|
* @brief Power Control
|
|
*/
|
|
|
|
typedef struct
|
|
{
|
|
__IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
|
|
__IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
|
|
} PWR_TypeDef;
|
|
|
|
/**
|
|
* @brief Reset and Clock Control
|
|
*/
|
|
|
|
typedef struct
|
|
{
|
|
__IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
|
|
__IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Address offset: 0x04 */
|
|
__IO uint32_t CFGR; /*!< RCC Clock configuration register, Address offset: 0x08 */
|
|
__IO uint32_t CIR; /*!< RCC Clock interrupt register, Address offset: 0x0C */
|
|
__IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x10 */
|
|
__IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x14 */
|
|
__IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x18 */
|
|
__IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Address offset: 0x1C */
|
|
__IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x20 */
|
|
__IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x24 */
|
|
__IO uint32_t AHBLPENR; /*!< RCC AHB peripheral clock enable in low power mode register, Address offset: 0x28 */
|
|
__IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x2C */
|
|
__IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x30 */
|
|
__IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x34 */
|
|
} RCC_TypeDef;
|
|
|
|
/**
|
|
* @brief Routing Interface
|
|
*/
|
|
|
|
typedef struct
|
|
{
|
|
__IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x04 */
|
|
__IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x08 */
|
|
__IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x0C */
|
|
__IO uint32_t HYSCR1; /*!< RI hysteresis control register 1, Address offset: 0x10 */
|
|
__IO uint32_t HYSCR2; /*!< RI Hysteresis control register 2, Address offset: 0x14 */
|
|
__IO uint32_t HYSCR3; /*!< RI Hysteresis control register 3, Address offset: 0x18 */
|
|
__IO uint32_t HYSCR4; /*!< RI Hysteresis control register 4, Address offset: 0x1C */
|
|
__IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x20 */
|
|
__IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x24 */
|
|
__IO uint32_t CICR1; /*!< RI Channel identification for capture register 1, Address offset: 0x28 */
|
|
__IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x2C */
|
|
__IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x30 */
|
|
__IO uint32_t CICR2; /*!< RI Channel identification for capture register 2, Address offset: 0x34 */
|
|
__IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x38 */
|
|
__IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x3C */
|
|
__IO uint32_t CICR3; /*!< RI Channel identification for capture register3 , Address offset: 0x40 */
|
|
__IO uint32_t ASMR4; /*!< RI Analog switch mode register 4, Address offset: 0x44 */
|
|
__IO uint32_t CMR4; /*!< RI Channel mask register 4, Address offset: 0x48 */
|
|
__IO uint32_t CICR4; /*!< RI Channel identification for capture register 4, Address offset: 0x4C */
|
|
__IO uint32_t ASMR5; /*!< RI Analog switch mode register 5, Address offset: 0x50 */
|
|
__IO uint32_t CMR5; /*!< RI Channel mask register 5, Address offset: 0x54 */
|
|
__IO uint32_t CICR5; /*!< RI Channel identification for capture register 5, Address offset: 0x58 */
|
|
} RI_TypeDef;
|
|
|
|
/**
|
|
* @brief Real-Time Clock
|
|
*/
|
|
|
|
typedef struct
|
|
{
|
|
__IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
|
|
__IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
|
|
__IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
|
|
__IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
|
|
__IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
|
|
__IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
|
|
__IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
|
|
__IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
|
|
__IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
|
|
__IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
|
|
__IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
|
|
__IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
|
|
__IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
|
|
__IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
|
|
__IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
|
|
__IO uint32_t CALR; /*!< RRTC calibration register, Address offset: 0x3C */
|
|
__IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
|
|
__IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
|
|
__IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
|
|
uint32_t RESERVED7; /*!< Reserved, 0x4C */
|
|
__IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
|
|
__IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
|
|
__IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
|
|
__IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
|
|
__IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
|
|
__IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
|
|
__IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
|
|
__IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
|
|
__IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
|
|
__IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
|
|
__IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
|
|
__IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
|
|
__IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
|
|
__IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
|
|
__IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
|
|
__IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
|
|
__IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
|
|
__IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
|
|
__IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
|
|
__IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
|
|
__IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */
|
|
__IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */
|
|
__IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */
|
|
__IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */
|
|
__IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */
|
|
__IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */
|
|
__IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */
|
|
__IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */
|
|
__IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */
|
|
__IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */
|
|
__IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */
|
|
__IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
|
|
} RTC_TypeDef;
|
|
|
|
/**
|
|
* @brief SD host Interface
|
|
*/
|
|
|
|
typedef struct
|
|
{
|
|
__IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
|
|
__IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
|
|
__IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
|
|
__IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
|
|
__I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
|
|
__I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
|
|
__I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
|
|
__I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
|
|
__I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
|
|
__IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
|
|
__IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
|
|
__IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
|
|
__I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
|
|
__I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
|
|
__IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
|
|
__IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
|
|
uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
|
|
__I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
|
|
uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
|
|
__IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
|
|
} SDIO_TypeDef;
|
|
|
|
/**
|
|
* @brief Serial Peripheral Interface
|
|
*/
|
|
|
|
typedef struct
|
|
{
|
|
__IO uint16_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
|
|
uint16_t RESERVED0; /*!< Reserved, 0x02 */
|
|
__IO uint16_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
|
|
uint16_t RESERVED1; /*!< Reserved, 0x06 */
|
|
__IO uint16_t SR; /*!< SPI status register, Address offset: 0x08 */
|
|
uint16_t RESERVED2; /*!< Reserved, 0x0A */
|
|
__IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */
|
|
uint16_t RESERVED3; /*!< Reserved, 0x0E */
|
|
__IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
|
|
uint16_t RESERVED4; /*!< Reserved, 0x12 */
|
|
__IO uint16_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
|
|
uint16_t RESERVED5; /*!< Reserved, 0x16 */
|
|
__IO uint16_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
|
|
uint16_t RESERVED6; /*!< Reserved, 0x1A */
|
|
__IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
|
|
uint16_t RESERVED7; /*!< Reserved, 0x1E */
|
|
__IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
|
|
uint16_t RESERVED8; /*!< Reserved, 0x22 */
|
|
} SPI_TypeDef;
|
|
|
|
/**
|
|
* @brief TIM
|
|
*/
|
|
|
|
typedef struct
|
|
{
|
|
__IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
|
|
uint16_t RESERVED0; /*!< Reserved, 0x02 */
|
|
__IO uint16_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
|
|
uint16_t RESERVED1; /*!< Reserved, 0x06 */
|
|
__IO uint16_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
|
|
uint16_t RESERVED2; /*!< Reserved, 0x0A */
|
|
__IO uint16_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
|
|
uint16_t RESERVED3; /*!< Reserved, 0x0E */
|
|
__IO uint16_t SR; /*!< TIM status register, Address offset: 0x10 */
|
|
uint16_t RESERVED4; /*!< Reserved, 0x12 */
|
|
__IO uint16_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
|
|
uint16_t RESERVED5; /*!< Reserved, 0x16 */
|
|
__IO uint16_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
|
|
uint16_t RESERVED6; /*!< Reserved, 0x1A */
|
|
__IO uint16_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
|
|
uint16_t RESERVED7; /*!< Reserved, 0x1E */
|
|
__IO uint16_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
|
|
uint16_t RESERVED8; /*!< Reserved, 0x22 */
|
|
__IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
|
|
__IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
|
|
uint16_t RESERVED10; /*!< Reserved, 0x2A */
|
|
__IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
|
|
uint32_t RESERVED12; /*!< Reserved, 0x30 */
|
|
__IO uint32_t CCR[4]; /*!< TIM capture/compare registers 1-4, Address offset: 0x34 ++ */
|
|
uint32_t RESERVED17; /*!< Reserved, 0x44 */
|
|
__IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
|
|
uint16_t RESERVED18; /*!< Reserved, 0x4A */
|
|
__IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
|
|
uint16_t RESERVED19; /*!< Reserved, 0x4E */
|
|
__IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */
|
|
uint16_t RESERVED20; /*!< Reserved, 0x52 */
|
|
} TIM_TypeDef;
|
|
|
|
/**
|
|
* @brief Universal Synchronous Asynchronous Receiver Transmitter
|
|
*/
|
|
|
|
typedef struct
|
|
{
|
|
__IO uint16_t SR; /*!< USART Status register, Address offset: 0x00 */
|
|
uint16_t RESERVED0; /*!< Reserved, 0x02 */
|
|
__IO uint16_t DR; /*!< USART Data register, Address offset: 0x04 */
|
|
uint16_t RESERVED1; /*!< Reserved, 0x06 */
|
|
__IO uint16_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
|
|
uint16_t RESERVED2; /*!< Reserved, 0x0A */
|
|
__IO uint16_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
|
|
uint16_t RESERVED3; /*!< Reserved, 0x0E */
|
|
__IO uint16_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
|
|
uint16_t RESERVED4; /*!< Reserved, 0x12 */
|
|
__IO uint16_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
|
|
uint16_t RESERVED5; /*!< Reserved, 0x16 */
|
|
__IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
|
|
uint16_t RESERVED6; /*!< Reserved, 0x1A */
|
|
} USART_TypeDef;
|
|
|
|
/**
|
|
* @brief Window WATCHDOG
|
|
*/
|
|
|
|
typedef struct
|
|
{
|
|
__IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
|
|
__IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
|
|
__IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
|
|
} WWDG_TypeDef;
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @addtogroup cpu_specific_Peripheral_memory_map
|
|
* @{
|
|
*/
|
|
|
|
#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
|
|
#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
|
|
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
|
|
|
|
#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
|
|
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
|
|
|
|
#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */
|
|
|
|
/*!< Peripheral memory map */
|
|
#define APB1PERIPH_BASE PERIPH_BASE
|
|
#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
|
|
#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
|
|
|
|
#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
|
|
#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
|
|
#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
|
|
#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
|
|
#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
|
|
#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
|
|
#define LCD_BASE (APB1PERIPH_BASE + 0x2400)
|
|
#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
|
|
#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
|
|
#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
|
|
#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
|
|
#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
|
|
#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
|
|
#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
|
|
#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
|
|
#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
|
|
#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
|
|
#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
|
|
#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
|
|
#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
|
|
#define COMP_BASE (APB1PERIPH_BASE + 0x7C00)
|
|
#define RI_BASE (APB1PERIPH_BASE + 0x7C04)
|
|
#define OPAMP_BASE (APB1PERIPH_BASE + 0x7C5C)
|
|
|
|
#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000)
|
|
#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
|
|
#define TIM9_BASE (APB2PERIPH_BASE + 0x0800)
|
|
#define TIM10_BASE (APB2PERIPH_BASE + 0x0C00)
|
|
#define TIM11_BASE (APB2PERIPH_BASE + 0x1000)
|
|
#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
|
|
#define ADC_BASE (APB2PERIPH_BASE + 0x2700)
|
|
#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00)
|
|
#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
|
|
#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
|
|
|
|
#define GPIOA_BASE (AHBPERIPH_BASE + 0x0000)
|
|
#define GPIOB_BASE (AHBPERIPH_BASE + 0x0400)
|
|
#define GPIOC_BASE (AHBPERIPH_BASE + 0x0800)
|
|
#define GPIOD_BASE (AHBPERIPH_BASE + 0x0C00)
|
|
#define GPIOE_BASE (AHBPERIPH_BASE + 0x1000)
|
|
#define GPIOH_BASE (AHBPERIPH_BASE + 0x1400)
|
|
#define GPIOF_BASE (AHBPERIPH_BASE + 0x1800)
|
|
#define GPIOG_BASE (AHBPERIPH_BASE + 0x1C00)
|
|
#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
|
|
#define RCC_BASE (AHBPERIPH_BASE + 0x3800)
|
|
|
|
|
|
#define FLASH_R_BASE (AHBPERIPH_BASE + 0x3C00) /*!< FLASH registers base address */
|
|
#define OB_BASE ((uint32_t)0x1FF80000) /*!< FLASH Option Bytes base address */
|
|
|
|
#define DMA1_BASE (AHBPERIPH_BASE + 0x6000)
|
|
#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008)
|
|
#define DMA1_Channel2_BASE (DMA1_BASE + 0x001C)
|
|
#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030)
|
|
#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044)
|
|
#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058)
|
|
#define DMA1_Channel6_BASE (DMA1_BASE + 0x006C)
|
|
#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080)
|
|
|
|
#define DMA2_BASE (AHBPERIPH_BASE + 0x6400)
|
|
#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008)
|
|
#define DMA2_Channel2_BASE (DMA2_BASE + 0x001C)
|
|
#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030)
|
|
#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044)
|
|
#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058)
|
|
|
|
#define AES_BASE ((uint32_t)0x50060000)
|
|
|
|
#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */
|
|
#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */
|
|
|
|
#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @addtogroup cpu_specific_Peripheral_declaration
|
|
* @{
|
|
*/
|
|
|
|
#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
|
|
#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
|
|
#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
|
|
#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
|
|
#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
|
|
#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
|
|
#define LCD ((LCD_TypeDef *) LCD_BASE)
|
|
#define RTC ((RTC_TypeDef *) RTC_BASE)
|
|
#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
|
|
#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
|
|
#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
|
|
#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
|
|
#define USART2 ((USART_TypeDef *) USART2_BASE)
|
|
#define USART3 ((USART_TypeDef *) USART3_BASE)
|
|
#define UART4 ((USART_TypeDef *) UART4_BASE)
|
|
#define UART5 ((USART_TypeDef *) UART5_BASE)
|
|
#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
|
|
#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
|
|
#define PWR ((PWR_TypeDef *) PWR_BASE)
|
|
#define DAC ((DAC_TypeDef *) DAC_BASE)
|
|
#define COMP ((COMP_TypeDef *) COMP_BASE)
|
|
#define RI ((RI_TypeDef *) RI_BASE)
|
|
#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
|
|
#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
|
|
#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
|
|
|
|
#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
|
|
#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
|
|
#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
|
|
#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
|
|
#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
|
|
#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
|
|
#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
|
|
#define USART1 ((USART_TypeDef *) USART1_BASE)
|
|
#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
|
|
#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
|
|
#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
|
|
#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
|
|
#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
|
|
#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
|
|
#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
|
|
#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
|
|
|
|
#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
|
|
#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
|
|
#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
|
|
#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
|
|
#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
|
|
#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
|
|
|
|
#define RCC ((RCC_TypeDef *) RCC_BASE)
|
|
#define CRC ((CRC_TypeDef *) CRC_BASE)
|
|
|
|
#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
|
|
#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
|
|
#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
|
|
#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
|
|
#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
|
|
#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
|
|
#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
|
|
#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
|
|
|
|
#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
|
|
#define OB ((OB_TypeDef *) OB_BASE)
|
|
|
|
#define AES ((AES_TypeDef *) AES_BASE)
|
|
|
|
#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
|
|
#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
|
|
|
|
#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @addtogroup cpu_specific_Exported_constants
|
|
* @{
|
|
*/
|
|
|
|
/** @addtogroup cpu_specific_Peripheral_Registers_Bits_Definition
|
|
* @{
|
|
*/
|
|
|
|
/******************************************************************************/
|
|
/* Peripheral Registers Bits Definition */
|
|
/******************************************************************************/
|
|
/******************************************************************************/
|
|
/* */
|
|
/* Analog to Digital Converter (ADC) */
|
|
/* */
|
|
/******************************************************************************/
|
|
|
|
/******************** Bit definition for ADC_SR register ********************/
|
|
#define ADC_SR_AWD ((uint32_t)0x00000001) /*!< Analog watchdog flag */
|
|
#define ADC_SR_EOC ((uint32_t)0x00000002) /*!< End of conversion */
|
|
#define ADC_SR_JEOC ((uint32_t)0x00000004) /*!< Injected channel end of conversion */
|
|
#define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!< Injected channel Start flag */
|
|
#define ADC_SR_STRT ((uint32_t)0x00000010) /*!< Regular channel Start flag */
|
|
#define ADC_SR_OVR ((uint32_t)0x00000020) /*!< Overrun flag */
|
|
#define ADC_SR_ADONS ((uint32_t)0x00000040) /*!< ADC ON status */
|
|
#define ADC_SR_RCNR ((uint32_t)0x00000100) /*!< Regular channel not ready flag */
|
|
#define ADC_SR_JCNR ((uint32_t)0x00000200) /*!< Injected channel not ready flag */
|
|
|
|
/******************* Bit definition for ADC_CR1 register ********************/
|
|
#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
|
|
#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!< Bit 0 */
|
|
#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!< Bit 1 */
|
|
#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!< Bit 2 */
|
|
#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!< Bit 3 */
|
|
#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!< Bit 4 */
|
|
|
|
#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!< Interrupt enable for EOC */
|
|
#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!< Analog Watchdog interrupt enable */
|
|
#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!< Interrupt enable for injected channels */
|
|
#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!< Scan mode */
|
|
#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!< Enable the watchdog on a single channel in scan mode */
|
|
#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!< Automatic injected group conversion */
|
|
#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!< Discontinuous mode on regular channels */
|
|
#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!< Discontinuous mode on injected channels */
|
|
|
|
#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */
|
|
#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!< Bit 0 */
|
|
#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!< Bit 1 */
|
|
#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!< Bit 2 */
|
|
|
|
#define ADC_CR1_PDD ((uint32_t)0x00010000) /*!< Power Down during Delay phase */
|
|
#define ADC_CR1_PDI ((uint32_t)0x00020000) /*!< Power Down during Idle phase */
|
|
|
|
#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!< Analog watchdog enable on injected channels */
|
|
#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */
|
|
|
|
#define ADC_CR1_RES ((uint32_t)0x03000000) /*!< RES[1:0] bits (Resolution) */
|
|
#define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!< Bit 0 */
|
|
#define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!< Bit 1 */
|
|
|
|
#define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!< Overrun interrupt enable */
|
|
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/******************* Bit definition for ADC_CR2 register ********************/
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#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */
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#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!< Continuous Conversion */
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#define ADC_CR2_CFG ((uint32_t)0x00000004) /*!< ADC Configuration */
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#define ADC_CR2_DELS ((uint32_t)0x00000070) /*!< DELS[2:0] bits (Delay selection) */
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#define ADC_CR2_DELS_0 ((uint32_t)0x00000010) /*!< Bit 0 */
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#define ADC_CR2_DELS_1 ((uint32_t)0x00000020) /*!< Bit 1 */
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#define ADC_CR2_DELS_2 ((uint32_t)0x00000040) /*!< Bit 2 */
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#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!< Direct Memory access mode */
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#define ADC_CR2_DDS ((uint32_t)0x00000200) /*!< DMA disable selection (Single ADC) */
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#define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!< End of conversion selection */
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#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!< Data Alignment */
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#define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!< JEXTSEL[3:0] bits (External event select for injected group) */
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#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!< Bit 0 */
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#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!< Bit 1 */
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#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!< Bit 2 */
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#define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!< Bit 3 */
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#define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!< JEXTEN[1:0] bits (External Trigger Conversion mode for injected channels) */
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#define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!< Bit 0 */
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#define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!< Bit 1 */
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#define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!< Start Conversion of injected channels */
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#define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!< EXTSEL[3:0] bits (External Event Select for regular group) */
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#define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!< Bit 0 */
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#define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!< Bit 1 */
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#define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!< Bit 2 */
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#define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!< Bit 3 */
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#define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
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#define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!< Bit 0 */
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#define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!< Bit 1 */
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#define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!< Start Conversion of regular channels */
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/****************** Bit definition for ADC_SMPR1 register *******************/
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#define ADC_SMPR1_SMP20 ((uint32_t)0x00000007) /*!< SMP20[2:0] bits (Channel 20 Sample time selection) */
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#define ADC_SMPR1_SMP20_0 ((uint32_t)0x00000001) /*!< Bit 0 */
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#define ADC_SMPR1_SMP20_1 ((uint32_t)0x00000002) /*!< Bit 1 */
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#define ADC_SMPR1_SMP20_2 ((uint32_t)0x00000004) /*!< Bit 2 */
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#define ADC_SMPR1_SMP21 ((uint32_t)0x00000038) /*!< SMP21[2:0] bits (Channel 21 Sample time selection) */
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#define ADC_SMPR1_SMP21_0 ((uint32_t)0x00000008) /*!< Bit 0 */
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#define ADC_SMPR1_SMP21_1 ((uint32_t)0x00000010) /*!< Bit 1 */
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#define ADC_SMPR1_SMP21_2 ((uint32_t)0x00000020) /*!< Bit 2 */
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#define ADC_SMPR1_SMP22 ((uint32_t)0x000001C0) /*!< SMP22[2:0] bits (Channel 22 Sample time selection) */
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#define ADC_SMPR1_SMP22_0 ((uint32_t)0x00000040) /*!< Bit 0 */
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#define ADC_SMPR1_SMP22_1 ((uint32_t)0x00000080) /*!< Bit 1 */
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#define ADC_SMPR1_SMP22_2 ((uint32_t)0x00000100) /*!< Bit 2 */
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#define ADC_SMPR1_SMP23 ((uint32_t)0x00000E00) /*!< SMP23[2:0] bits (Channel 23 Sample time selection) */
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#define ADC_SMPR1_SMP23_0 ((uint32_t)0x00000200) /*!< Bit 0 */
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#define ADC_SMPR1_SMP23_1 ((uint32_t)0x00000400) /*!< Bit 1 */
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#define ADC_SMPR1_SMP23_2 ((uint32_t)0x00000800) /*!< Bit 2 */
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#define ADC_SMPR1_SMP24 ((uint32_t)0x00007000) /*!< SMP24[2:0] bits (Channel 24 Sample time selection) */
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#define ADC_SMPR1_SMP24_0 ((uint32_t)0x00001000) /*!< Bit 0 */
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#define ADC_SMPR1_SMP24_1 ((uint32_t)0x00002000) /*!< Bit 1 */
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#define ADC_SMPR1_SMP24_2 ((uint32_t)0x00004000) /*!< Bit 2 */
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#define ADC_SMPR1_SMP25 ((uint32_t)0x00038000) /*!< SMP25[2:0] bits (Channel 25 Sample time selection) */
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#define ADC_SMPR1_SMP25_0 ((uint32_t)0x00008000) /*!< Bit 0 */
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#define ADC_SMPR1_SMP25_1 ((uint32_t)0x00010000) /*!< Bit 1 */
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#define ADC_SMPR1_SMP25_2 ((uint32_t)0x00020000) /*!< Bit 2 */
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#define ADC_SMPR1_SMP26 ((uint32_t)0x001C0000) /*!< SMP26[2:0] bits (Channel 26 Sample time selection) */
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#define ADC_SMPR1_SMP26_0 ((uint32_t)0x00040000) /*!< Bit 0 */
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#define ADC_SMPR1_SMP26_1 ((uint32_t)0x00080000) /*!< Bit 1 */
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#define ADC_SMPR1_SMP26_2 ((uint32_t)0x00100000) /*!< Bit 2 */
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#define ADC_SMPR1_SMP27 ((uint32_t)0x00E00000) /*!< SMP27[2:0] bits (Channel 27 Sample time selection) */
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#define ADC_SMPR1_SMP27_0 ((uint32_t)0x00200000) /*!< Bit 0 */
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#define ADC_SMPR1_SMP27_1 ((uint32_t)0x00400000) /*!< Bit 1 */
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#define ADC_SMPR1_SMP27_2 ((uint32_t)0x00800000) /*!< Bit 2 */
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#define ADC_SMPR1_SMP28 ((uint32_t)0x07000000) /*!< SMP28[2:0] bits (Channel 28 Sample time selection) */
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#define ADC_SMPR1_SMP28_0 ((uint32_t)0x01000000) /*!< Bit 0 */
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#define ADC_SMPR1_SMP28_1 ((uint32_t)0x02000000) /*!< Bit 1 */
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#define ADC_SMPR1_SMP28_2 ((uint32_t)0x04000000) /*!< Bit 2 */
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#define ADC_SMPR1_SMP29 ((uint32_t)0x38000000) /*!< SMP29[2:0] bits (Channel 29 Sample time selection) */
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#define ADC_SMPR1_SMP29_0 ((uint32_t)0x08000000) /*!< Bit 0 */
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#define ADC_SMPR1_SMP29_1 ((uint32_t)0x10000000) /*!< Bit 1 */
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#define ADC_SMPR1_SMP29_2 ((uint32_t)0x20000000) /*!< Bit 2 */
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/****************** Bit definition for ADC_SMPR2 register *******************/
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#define ADC_SMPR2_SMP10 ((uint32_t)0x00000007) /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */
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#define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001) /*!< Bit 0 */
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#define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002) /*!< Bit 1 */
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#define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004) /*!< Bit 2 */
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#define ADC_SMPR2_SMP11 ((uint32_t)0x00000038) /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */
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#define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008) /*!< Bit 0 */
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#define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010) /*!< Bit 1 */
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#define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020) /*!< Bit 2 */
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#define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0) /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */
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#define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040) /*!< Bit 0 */
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#define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080) /*!< Bit 1 */
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#define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100) /*!< Bit 2 */
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#define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00) /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */
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#define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200) /*!< Bit 0 */
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#define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400) /*!< Bit 1 */
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#define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800) /*!< Bit 2 */
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#define ADC_SMPR2_SMP14 ((uint32_t)0x00007000) /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */
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#define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000) /*!< Bit 0 */
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#define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000) /*!< Bit 1 */
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#define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000) /*!< Bit 2 */
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#define ADC_SMPR2_SMP15 ((uint32_t)0x00038000) /*!< SMP15[2:0] bits (Channel 5 Sample time selection) */
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#define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000) /*!< Bit 0 */
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#define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000) /*!< Bit 1 */
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#define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000) /*!< Bit 2 */
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#define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000) /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */
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#define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000) /*!< Bit 0 */
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#define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000) /*!< Bit 1 */
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#define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000) /*!< Bit 2 */
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#define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000) /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */
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#define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000) /*!< Bit 0 */
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#define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000) /*!< Bit 1 */
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#define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000) /*!< Bit 2 */
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#define ADC_SMPR2_SMP18 ((uint32_t)0x07000000) /*!< SMP18[2:0] bits (Channel 18 Sample time selection) */
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#define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000) /*!< Bit 0 */
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#define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000) /*!< Bit 1 */
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#define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000) /*!< Bit 2 */
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#define ADC_SMPR2_SMP19 ((uint32_t)0x38000000) /*!< SMP19[2:0] bits (Channel 19 Sample time selection) */
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#define ADC_SMPR2_SMP19_0 ((uint32_t)0x08000000) /*!< Bit 0 */
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#define ADC_SMPR2_SMP19_1 ((uint32_t)0x10000000) /*!< Bit 1 */
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#define ADC_SMPR2_SMP19_2 ((uint32_t)0x20000000) /*!< Bit 2 */
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/****************** Bit definition for ADC_SMPR3 register *******************/
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#define ADC_SMPR3_SMP0 ((uint32_t)0x00000007) /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */
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#define ADC_SMPR3_SMP0_0 ((uint32_t)0x00000001) /*!< Bit 0 */
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#define ADC_SMPR3_SMP0_1 ((uint32_t)0x00000002) /*!< Bit 1 */
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#define ADC_SMPR3_SMP0_2 ((uint32_t)0x00000004) /*!< Bit 2 */
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#define ADC_SMPR3_SMP1 ((uint32_t)0x00000038) /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */
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#define ADC_SMPR3_SMP1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
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#define ADC_SMPR3_SMP1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
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#define ADC_SMPR3_SMP1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
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#define ADC_SMPR3_SMP2 ((uint32_t)0x000001C0) /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */
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#define ADC_SMPR3_SMP2_0 ((uint32_t)0x00000040) /*!< Bit 0 */
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#define ADC_SMPR3_SMP2_1 ((uint32_t)0x00000080) /*!< Bit 1 */
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#define ADC_SMPR3_SMP2_2 ((uint32_t)0x00000100) /*!< Bit 2 */
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#define ADC_SMPR3_SMP3 ((uint32_t)0x00000E00) /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */
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#define ADC_SMPR3_SMP3_0 ((uint32_t)0x00000200) /*!< Bit 0 */
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#define ADC_SMPR3_SMP3_1 ((uint32_t)0x00000400) /*!< Bit 1 */
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#define ADC_SMPR3_SMP3_2 ((uint32_t)0x00000800) /*!< Bit 2 */
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#define ADC_SMPR3_SMP4 ((uint32_t)0x00007000) /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */
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#define ADC_SMPR3_SMP4_0 ((uint32_t)0x00001000) /*!< Bit 0 */
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#define ADC_SMPR3_SMP4_1 ((uint32_t)0x00002000) /*!< Bit 1 */
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#define ADC_SMPR3_SMP4_2 ((uint32_t)0x00004000) /*!< Bit 2 */
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#define ADC_SMPR3_SMP5 ((uint32_t)0x00038000) /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */
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#define ADC_SMPR3_SMP5_0 ((uint32_t)0x00008000) /*!< Bit 0 */
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#define ADC_SMPR3_SMP5_1 ((uint32_t)0x00010000) /*!< Bit 1 */
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#define ADC_SMPR3_SMP5_2 ((uint32_t)0x00020000) /*!< Bit 2 */
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#define ADC_SMPR3_SMP6 ((uint32_t)0x001C0000) /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */
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#define ADC_SMPR3_SMP6_0 ((uint32_t)0x00040000) /*!< Bit 0 */
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#define ADC_SMPR3_SMP6_1 ((uint32_t)0x00080000) /*!< Bit 1 */
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#define ADC_SMPR3_SMP6_2 ((uint32_t)0x00100000) /*!< Bit 2 */
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#define ADC_SMPR3_SMP7 ((uint32_t)0x00E00000) /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */
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#define ADC_SMPR3_SMP7_0 ((uint32_t)0x00200000) /*!< Bit 0 */
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#define ADC_SMPR3_SMP7_1 ((uint32_t)0x00400000) /*!< Bit 1 */
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#define ADC_SMPR3_SMP7_2 ((uint32_t)0x00800000) /*!< Bit 2 */
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#define ADC_SMPR3_SMP8 ((uint32_t)0x07000000) /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */
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#define ADC_SMPR3_SMP8_0 ((uint32_t)0x01000000) /*!< Bit 0 */
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#define ADC_SMPR3_SMP8_1 ((uint32_t)0x02000000) /*!< Bit 1 */
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#define ADC_SMPR3_SMP8_2 ((uint32_t)0x04000000) /*!< Bit 2 */
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#define ADC_SMPR3_SMP9 ((uint32_t)0x38000000) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */
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#define ADC_SMPR3_SMP9_0 ((uint32_t)0x08000000) /*!< Bit 0 */
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#define ADC_SMPR3_SMP9_1 ((uint32_t)0x10000000) /*!< Bit 1 */
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#define ADC_SMPR3_SMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */
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/****************** Bit definition for ADC_JOFR1 register *******************/
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#define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 1 */
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/****************** Bit definition for ADC_JOFR2 register *******************/
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#define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 2 */
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/****************** Bit definition for ADC_JOFR3 register *******************/
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#define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 3 */
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/****************** Bit definition for ADC_JOFR4 register *******************/
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#define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 4 */
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/******************* Bit definition for ADC_HTR register ********************/
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#define ADC_HTR_HT ((uint32_t)0x00000FFF) /*!< Analog watchdog high threshold */
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/******************* Bit definition for ADC_LTR register ********************/
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#define ADC_LTR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */
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/******************* Bit definition for ADC_SQR1 register *******************/
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#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!< L[3:0] bits (Regular channel sequence length) */
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#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!< Bit 0 */
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#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!< Bit 1 */
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#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!< Bit 2 */
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#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!< Bit 3 */
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#define ADC_SQR1_SQ28 ((uint32_t)0x000F8000) /*!< SQ28[4:0] bits (25th conversion in regular sequence) */
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#define ADC_SQR1_SQ28_0 ((uint32_t)0x00008000) /*!< Bit 0 */
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#define ADC_SQR1_SQ28_1 ((uint32_t)0x00010000) /*!< Bit 1 */
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#define ADC_SQR1_SQ28_2 ((uint32_t)0x00020000) /*!< Bit 2 */
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#define ADC_SQR1_SQ28_3 ((uint32_t)0x00040000) /*!< Bit 3 */
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#define ADC_SQR1_SQ28_4 ((uint32_t)0x00080000) /*!< Bit 4 */
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#define ADC_SQR1_SQ27 ((uint32_t)0x00007C00) /*!< SQ27[4:0] bits (27th conversion in regular sequence) */
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#define ADC_SQR1_SQ27_0 ((uint32_t)0x00000400) /*!< Bit 0 */
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#define ADC_SQR1_SQ27_1 ((uint32_t)0x00000800) /*!< Bit 1 */
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#define ADC_SQR1_SQ27_2 ((uint32_t)0x00001000) /*!< Bit 2 */
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#define ADC_SQR1_SQ27_3 ((uint32_t)0x00002000) /*!< Bit 3 */
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#define ADC_SQR1_SQ27_4 ((uint32_t)0x00004000) /*!< Bit 4 */
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#define ADC_SQR1_SQ26 ((uint32_t)0x000003E0) /*!< SQ26[4:0] bits (26th conversion in regular sequence) */
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#define ADC_SQR1_SQ26_0 ((uint32_t)0x00000020) /*!< Bit 0 */
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#define ADC_SQR1_SQ26_1 ((uint32_t)0x00000040) /*!< Bit 1 */
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#define ADC_SQR1_SQ26_2 ((uint32_t)0x00000080) /*!< Bit 2 */
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#define ADC_SQR1_SQ26_3 ((uint32_t)0x00000100) /*!< Bit 3 */
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#define ADC_SQR1_SQ26_4 ((uint32_t)0x00000200) /*!< Bit 4 */
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#define ADC_SQR1_SQ25 ((uint32_t)0x0000001F) /*!< SQ25[4:0] bits (25th conversion in regular sequence) */
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#define ADC_SQR1_SQ25_0 ((uint32_t)0x00000001) /*!< Bit 0 */
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#define ADC_SQR1_SQ25_1 ((uint32_t)0x00000002) /*!< Bit 1 */
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#define ADC_SQR1_SQ25_2 ((uint32_t)0x00000004) /*!< Bit 2 */
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#define ADC_SQR1_SQ25_3 ((uint32_t)0x00000008) /*!< Bit 3 */
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#define ADC_SQR1_SQ25_4 ((uint32_t)0x00000010) /*!< Bit 4 */
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/******************* Bit definition for ADC_SQR2 register *******************/
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#define ADC_SQR2_SQ19 ((uint32_t)0x0000001F) /*!< SQ19[4:0] bits (19th conversion in regular sequence) */
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#define ADC_SQR2_SQ19_0 ((uint32_t)0x00000001) /*!< Bit 0 */
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#define ADC_SQR2_SQ19_1 ((uint32_t)0x00000002) /*!< Bit 1 */
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#define ADC_SQR2_SQ19_2 ((uint32_t)0x00000004) /*!< Bit 2 */
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#define ADC_SQR2_SQ19_3 ((uint32_t)0x00000008) /*!< Bit 3 */
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#define ADC_SQR2_SQ19_4 ((uint32_t)0x00000010) /*!< Bit 4 */
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#define ADC_SQR2_SQ20 ((uint32_t)0x000003E0) /*!< SQ20[4:0] bits (20th conversion in regular sequence) */
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#define ADC_SQR2_SQ20_0 ((uint32_t)0x00000020) /*!< Bit 0 */
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#define ADC_SQR2_SQ20_1 ((uint32_t)0x00000040) /*!< Bit 1 */
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#define ADC_SQR2_SQ20_2 ((uint32_t)0x00000080) /*!< Bit 2 */
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#define ADC_SQR2_SQ20_3 ((uint32_t)0x00000100) /*!< Bit 3 */
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#define ADC_SQR2_SQ20_4 ((uint32_t)0x00000200) /*!< Bit 4 */
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#define ADC_SQR2_SQ21 ((uint32_t)0x00007C00) /*!< SQ21[4:0] bits (21th conversion in regular sequence) */
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#define ADC_SQR2_SQ21_0 ((uint32_t)0x00000400) /*!< Bit 0 */
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#define ADC_SQR2_SQ21_1 ((uint32_t)0x00000800) /*!< Bit 1 */
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#define ADC_SQR2_SQ21_2 ((uint32_t)0x00001000) /*!< Bit 2 */
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#define ADC_SQR2_SQ21_3 ((uint32_t)0x00002000) /*!< Bit 3 */
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#define ADC_SQR2_SQ21_4 ((uint32_t)0x00004000) /*!< Bit 4 */
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#define ADC_SQR2_SQ22 ((uint32_t)0x000F8000) /*!< SQ22[4:0] bits (22th conversion in regular sequence) */
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#define ADC_SQR2_SQ22_0 ((uint32_t)0x00008000) /*!< Bit 0 */
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#define ADC_SQR2_SQ22_1 ((uint32_t)0x00010000) /*!< Bit 1 */
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#define ADC_SQR2_SQ22_2 ((uint32_t)0x00020000) /*!< Bit 2 */
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#define ADC_SQR2_SQ22_3 ((uint32_t)0x00040000) /*!< Bit 3 */
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#define ADC_SQR2_SQ22_4 ((uint32_t)0x00080000) /*!< Bit 4 */
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#define ADC_SQR2_SQ23 ((uint32_t)0x01F00000) /*!< SQ23[4:0] bits (23th conversion in regular sequence) */
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#define ADC_SQR2_SQ23_0 ((uint32_t)0x00100000) /*!< Bit 0 */
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#define ADC_SQR2_SQ23_1 ((uint32_t)0x00200000) /*!< Bit 1 */
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#define ADC_SQR2_SQ23_2 ((uint32_t)0x00400000) /*!< Bit 2 */
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#define ADC_SQR2_SQ23_3 ((uint32_t)0x00800000) /*!< Bit 3 */
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#define ADC_SQR2_SQ23_4 ((uint32_t)0x01000000) /*!< Bit 4 */
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#define ADC_SQR2_SQ24 ((uint32_t)0x3E000000) /*!< SQ24[4:0] bits (24th conversion in regular sequence) */
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#define ADC_SQR2_SQ24_0 ((uint32_t)0x02000000) /*!< Bit 0 */
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#define ADC_SQR2_SQ24_1 ((uint32_t)0x04000000) /*!< Bit 1 */
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#define ADC_SQR2_SQ24_2 ((uint32_t)0x08000000) /*!< Bit 2 */
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#define ADC_SQR2_SQ24_3 ((uint32_t)0x10000000) /*!< Bit 3 */
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#define ADC_SQR2_SQ24_4 ((uint32_t)0x20000000) /*!< Bit 4 */
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/******************* Bit definition for ADC_SQR3 register *******************/
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#define ADC_SQR3_SQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */
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#define ADC_SQR3_SQ13_0 ((uint32_t)0x00000001) /*!< Bit 0 */
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#define ADC_SQR3_SQ13_1 ((uint32_t)0x00000002) /*!< Bit 1 */
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#define ADC_SQR3_SQ13_2 ((uint32_t)0x00000004) /*!< Bit 2 */
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#define ADC_SQR3_SQ13_3 ((uint32_t)0x00000008) /*!< Bit 3 */
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#define ADC_SQR3_SQ13_4 ((uint32_t)0x00000010) /*!< Bit 4 */
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#define ADC_SQR3_SQ14 ((uint32_t)0x000003E0) /*!< SQ14[4:0] bits (14th conversion in regular sequence) */
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#define ADC_SQR3_SQ14_0 ((uint32_t)0x00000020) /*!< Bit 0 */
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#define ADC_SQR3_SQ14_1 ((uint32_t)0x00000040) /*!< Bit 1 */
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#define ADC_SQR3_SQ14_2 ((uint32_t)0x00000080) /*!< Bit 2 */
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#define ADC_SQR3_SQ14_3 ((uint32_t)0x00000100) /*!< Bit 3 */
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#define ADC_SQR3_SQ14_4 ((uint32_t)0x00000200) /*!< Bit 4 */
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#define ADC_SQR3_SQ15 ((uint32_t)0x00007C00) /*!< SQ15[4:0] bits (15th conversion in regular sequence) */
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#define ADC_SQR3_SQ15_0 ((uint32_t)0x00000400) /*!< Bit 0 */
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#define ADC_SQR3_SQ15_1 ((uint32_t)0x00000800) /*!< Bit 1 */
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#define ADC_SQR3_SQ15_2 ((uint32_t)0x00001000) /*!< Bit 2 */
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#define ADC_SQR3_SQ15_3 ((uint32_t)0x00002000) /*!< Bit 3 */
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#define ADC_SQR3_SQ15_4 ((uint32_t)0x00004000) /*!< Bit 4 */
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#define ADC_SQR3_SQ16 ((uint32_t)0x000F8000) /*!< SQ16[4:0] bits (16th conversion in regular sequence) */
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#define ADC_SQR3_SQ16_0 ((uint32_t)0x00008000) /*!< Bit 0 */
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#define ADC_SQR3_SQ16_1 ((uint32_t)0x00010000) /*!< Bit 1 */
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#define ADC_SQR3_SQ16_2 ((uint32_t)0x00020000) /*!< Bit 2 */
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#define ADC_SQR3_SQ16_3 ((uint32_t)0x00040000) /*!< Bit 3 */
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#define ADC_SQR3_SQ16_4 ((uint32_t)0x00080000) /*!< Bit 4 */
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#define ADC_SQR3_SQ17 ((uint32_t)0x01F00000) /*!< SQ17[4:0] bits (17th conversion in regular sequence) */
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#define ADC_SQR3_SQ17_0 ((uint32_t)0x00100000) /*!< Bit 0 */
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#define ADC_SQR3_SQ17_1 ((uint32_t)0x00200000) /*!< Bit 1 */
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#define ADC_SQR3_SQ17_2 ((uint32_t)0x00400000) /*!< Bit 2 */
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#define ADC_SQR3_SQ17_3 ((uint32_t)0x00800000) /*!< Bit 3 */
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#define ADC_SQR3_SQ17_4 ((uint32_t)0x01000000) /*!< Bit 4 */
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#define ADC_SQR3_SQ18 ((uint32_t)0x3E000000) /*!< SQ18[4:0] bits (18th conversion in regular sequence) */
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#define ADC_SQR3_SQ18_0 ((uint32_t)0x02000000) /*!< Bit 0 */
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#define ADC_SQR3_SQ18_1 ((uint32_t)0x04000000) /*!< Bit 1 */
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#define ADC_SQR3_SQ18_2 ((uint32_t)0x08000000) /*!< Bit 2 */
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#define ADC_SQR3_SQ18_3 ((uint32_t)0x10000000) /*!< Bit 3 */
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#define ADC_SQR3_SQ18_4 ((uint32_t)0x20000000) /*!< Bit 4 */
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/******************* Bit definition for ADC_SQR4 register *******************/
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#define ADC_SQR4_SQ7 ((uint32_t)0x0000001F) /*!< SQ7[4:0] bits (7th conversion in regular sequence) */
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#define ADC_SQR4_SQ7_0 ((uint32_t)0x00000001) /*!< Bit 0 */
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#define ADC_SQR4_SQ7_1 ((uint32_t)0x00000002) /*!< Bit 1 */
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#define ADC_SQR4_SQ7_2 ((uint32_t)0x00000004) /*!< Bit 2 */
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#define ADC_SQR4_SQ7_3 ((uint32_t)0x00000008) /*!< Bit 3 */
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#define ADC_SQR4_SQ7_4 ((uint32_t)0x00000010) /*!< Bit 4 */
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#define ADC_SQR4_SQ8 ((uint32_t)0x000003E0) /*!< SQ8[4:0] bits (8th conversion in regular sequence) */
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#define ADC_SQR4_SQ8_0 ((uint32_t)0x00000020) /*!< Bit 0 */
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#define ADC_SQR4_SQ8_1 ((uint32_t)0x00000040) /*!< Bit 1 */
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#define ADC_SQR4_SQ8_2 ((uint32_t)0x00000080) /*!< Bit 2 */
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#define ADC_SQR4_SQ8_3 ((uint32_t)0x00000100) /*!< Bit 3 */
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#define ADC_SQR4_SQ8_4 ((uint32_t)0x00000200) /*!< Bit 4 */
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#define ADC_SQR4_SQ9 ((uint32_t)0x00007C00) /*!< SQ9[4:0] bits (9th conversion in regular sequence) */
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#define ADC_SQR4_SQ9_0 ((uint32_t)0x00000400) /*!< Bit 0 */
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#define ADC_SQR4_SQ9_1 ((uint32_t)0x00000800) /*!< Bit 1 */
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#define ADC_SQR4_SQ9_2 ((uint32_t)0x00001000) /*!< Bit 2 */
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#define ADC_SQR4_SQ9_3 ((uint32_t)0x00002000) /*!< Bit 3 */
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#define ADC_SQR4_SQ9_4 ((uint32_t)0x00004000) /*!< Bit 4 */
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#define ADC_SQR4_SQ10 ((uint32_t)0x000F8000) /*!< SQ10[4:0] bits (10th conversion in regular sequence) */
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#define ADC_SQR4_SQ10_0 ((uint32_t)0x00008000) /*!< Bit 0 */
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#define ADC_SQR4_SQ10_1 ((uint32_t)0x00010000) /*!< Bit 1 */
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#define ADC_SQR4_SQ10_2 ((uint32_t)0x00020000) /*!< Bit 2 */
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#define ADC_SQR4_SQ10_3 ((uint32_t)0x00040000) /*!< Bit 3 */
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#define ADC_SQR4_SQ10_4 ((uint32_t)0x00080000) /*!< Bit 4 */
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#define ADC_SQR4_SQ11 ((uint32_t)0x01F00000) /*!< SQ11[4:0] bits (11th conversion in regular sequence) */
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#define ADC_SQR4_SQ11_0 ((uint32_t)0x00100000) /*!< Bit 0 */
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#define ADC_SQR4_SQ11_1 ((uint32_t)0x00200000) /*!< Bit 1 */
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#define ADC_SQR4_SQ11_2 ((uint32_t)0x00400000) /*!< Bit 2 */
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#define ADC_SQR4_SQ11_3 ((uint32_t)0x00800000) /*!< Bit 3 */
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#define ADC_SQR4_SQ11_4 ((uint32_t)0x01000000) /*!< Bit 4 */
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#define ADC_SQR4_SQ12 ((uint32_t)0x3E000000) /*!< SQ12[4:0] bits (12th conversion in regular sequence) */
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#define ADC_SQR4_SQ12_0 ((uint32_t)0x02000000) /*!< Bit 0 */
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#define ADC_SQR4_SQ12_1 ((uint32_t)0x04000000) /*!< Bit 1 */
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#define ADC_SQR4_SQ12_2 ((uint32_t)0x08000000) /*!< Bit 2 */
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#define ADC_SQR4_SQ12_3 ((uint32_t)0x10000000) /*!< Bit 3 */
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#define ADC_SQR4_SQ12_4 ((uint32_t)0x20000000) /*!< Bit 4 */
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/******************* Bit definition for ADC_SQR5 register *******************/
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#define ADC_SQR5_SQ1 ((uint32_t)0x0000001F) /*!< SQ1[4:0] bits (1st conversion in regular sequence) */
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#define ADC_SQR5_SQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
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#define ADC_SQR5_SQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
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#define ADC_SQR5_SQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
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#define ADC_SQR5_SQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
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#define ADC_SQR5_SQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */
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#define ADC_SQR5_SQ2 ((uint32_t)0x000003E0) /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */
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#define ADC_SQR5_SQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */
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#define ADC_SQR5_SQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */
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#define ADC_SQR5_SQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */
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#define ADC_SQR5_SQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */
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#define ADC_SQR5_SQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */
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#define ADC_SQR5_SQ3 ((uint32_t)0x00007C00) /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */
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#define ADC_SQR5_SQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */
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#define ADC_SQR5_SQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */
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#define ADC_SQR5_SQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */
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#define ADC_SQR5_SQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */
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#define ADC_SQR5_SQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */
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#define ADC_SQR5_SQ4 ((uint32_t)0x000F8000) /*!< SQ4[4:0] bits (4th conversion in regular sequence) */
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#define ADC_SQR5_SQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */
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#define ADC_SQR5_SQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */
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#define ADC_SQR5_SQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */
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#define ADC_SQR5_SQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */
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#define ADC_SQR5_SQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */
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#define ADC_SQR5_SQ5 ((uint32_t)0x01F00000) /*!< SQ5[4:0] bits (5th conversion in regular sequence) */
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#define ADC_SQR5_SQ5_0 ((uint32_t)0x00100000) /*!< Bit 0 */
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#define ADC_SQR5_SQ5_1 ((uint32_t)0x00200000) /*!< Bit 1 */
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#define ADC_SQR5_SQ5_2 ((uint32_t)0x00400000) /*!< Bit 2 */
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#define ADC_SQR5_SQ5_3 ((uint32_t)0x00800000) /*!< Bit 3 */
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#define ADC_SQR5_SQ5_4 ((uint32_t)0x01000000) /*!< Bit 4 */
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#define ADC_SQR5_SQ6 ((uint32_t)0x3E000000) /*!< SQ6[4:0] bits (6th conversion in regular sequence) */
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#define ADC_SQR5_SQ6_0 ((uint32_t)0x02000000) /*!< Bit 0 */
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#define ADC_SQR5_SQ6_1 ((uint32_t)0x04000000) /*!< Bit 1 */
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#define ADC_SQR5_SQ6_2 ((uint32_t)0x08000000) /*!< Bit 2 */
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#define ADC_SQR5_SQ6_3 ((uint32_t)0x10000000) /*!< Bit 3 */
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#define ADC_SQR5_SQ6_4 ((uint32_t)0x20000000) /*!< Bit 4 */
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/******************* Bit definition for ADC_JSQR register *******************/
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#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */
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#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
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#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
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#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
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#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
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#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */
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#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */
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#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */
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#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */
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#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */
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#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */
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#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */
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#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */
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#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */
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#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */
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#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */
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#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */
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#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */
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#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */
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#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */
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#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */
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#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */
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#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */
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#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */
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#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!< JL[1:0] bits (Injected Sequence length) */
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#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!< Bit 0 */
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#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!< Bit 1 */
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/******************* Bit definition for ADC_JDR1 register *******************/
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#define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */
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/******************* Bit definition for ADC_JDR2 register *******************/
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#define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */
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/******************* Bit definition for ADC_JDR3 register *******************/
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#define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */
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/******************* Bit definition for ADC_JDR4 register *******************/
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#define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */
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/******************** Bit definition for ADC_DR register ********************/
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#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */
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/****************** Bit definition for ADC_SMPR0 register *******************/
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#define ADC_SMPR3_SMP30 ((uint32_t)0x00000007) /*!< SMP30[2:0] bits (Channel 30 Sample time selection) */
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#define ADC_SMPR3_SMP30_0 ((uint32_t)0x00000001) /*!< Bit 0 */
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#define ADC_SMPR3_SMP30_1 ((uint32_t)0x00000002) /*!< Bit 1 */
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#define ADC_SMPR3_SMP30_2 ((uint32_t)0x00000004) /*!< Bit 2 */
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#define ADC_SMPR3_SMP31 ((uint32_t)0x00000038) /*!< SMP31[2:0] bits (Channel 31 Sample time selection) */
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#define ADC_SMPR3_SMP31_0 ((uint32_t)0x00000008) /*!< Bit 0 */
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#define ADC_SMPR3_SMP31_1 ((uint32_t)0x00000010) /*!< Bit 1 */
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#define ADC_SMPR3_SMP31_2 ((uint32_t)0x00000020) /*!< Bit 2 */
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/******************* Bit definition for ADC_CSR register ********************/
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#define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!< ADC1 Analog watchdog flag */
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#define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!< ADC1 End of conversion */
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#define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!< ADC1 Injected channel end of conversion */
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#define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!< ADC1 Injected channel Start flag */
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#define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!< ADC1 Regular channel Start flag */
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#define ADC_CSR_OVR1 ((uint32_t)0x00000020) /*!< ADC1 overrun flag */
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#define ADC_CSR_ADONS1 ((uint32_t)0x00000040) /*!< ADON status of ADC1 */
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/******************* Bit definition for ADC_CCR register ********************/
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#define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!< ADC prescaler*/
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#define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!< Bit 0 */
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#define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!< Bit 1 */
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#define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!< Temperature Sensor and VREFINT Enable */
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/******************************************************************************/
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/* */
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/* Advanced Encryption Standard (AES) */
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/* */
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/******************************************************************************/
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/******************* Bit definition for AES_CR register *********************/
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#define AES_CR_EN ((uint32_t)0x00000001) /*!< AES Enable */
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#define AES_CR_DATATYPE ((uint32_t)0x00000006) /*!< Data type selection */
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#define AES_CR_DATATYPE_0 ((uint32_t)0x00000002) /*!< Bit 0 */
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#define AES_CR_DATATYPE_1 ((uint32_t)0x00000004) /*!< Bit 1 */
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#define AES_CR_MODE ((uint32_t)0x00000018) /*!< AES Mode Of Operation */
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#define AES_CR_MODE_0 ((uint32_t)0x00000008) /*!< Bit 0 */
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#define AES_CR_MODE_1 ((uint32_t)0x00000010) /*!< Bit 1 */
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#define AES_CR_CHMOD ((uint32_t)0x00000060) /*!< AES Chaining Mode */
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#define AES_CR_CHMOD_0 ((uint32_t)0x00000020) /*!< Bit 0 */
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#define AES_CR_CHMOD_1 ((uint32_t)0x00000040) /*!< Bit 1 */
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#define AES_CR_CCFC ((uint32_t)0x00000080) /*!< Computation Complete Flag Clear */
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#define AES_CR_ERRC ((uint32_t)0x00000100) /*!< Error Clear */
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#define AES_CR_CCIE ((uint32_t)0x00000200) /*!< Computation Complete Interrupt Enable */
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#define AES_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */
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#define AES_CR_DMAINEN ((uint32_t)0x00000800) /*!< DMA ENable managing the data input phase */
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#define AES_CR_DMAOUTEN ((uint32_t)0x00001000) /*!< DMA Enable managing the data output phase */
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/******************* Bit definition for AES_SR register *********************/
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#define AES_SR_CCF ((uint32_t)0x00000001) /*!< Computation Complete Flag */
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#define AES_SR_RDERR ((uint32_t)0x00000002) /*!< Read Error Flag */
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#define AES_SR_WRERR ((uint32_t)0x00000004) /*!< Write Error Flag */
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/******************* Bit definition for AES_DINR register *******************/
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#define AES_DINR ((uint32_t)0x0000FFFF) /*!< AES Data Input Register */
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/******************* Bit definition for AES_DOUTR register ******************/
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#define AES_DOUTR ((uint32_t)0x0000FFFF) /*!< AES Data Output Register */
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/******************* Bit definition for AES_KEYR0 register ******************/
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#define AES_KEYR0 ((uint32_t)0x0000FFFF) /*!< AES Key Register 0 */
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/******************* Bit definition for AES_KEYR1 register ******************/
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#define AES_KEYR1 ((uint32_t)0x0000FFFF) /*!< AES Key Register 1 */
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/******************* Bit definition for AES_KEYR2 register ******************/
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#define AES_KEYR2 ((uint32_t)0x0000FFFF) /*!< AES Key Register 2 */
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/******************* Bit definition for AES_KEYR3 register ******************/
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#define AES_KEYR3 ((uint32_t)0x0000FFFF) /*!< AES Key Register 3 */
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/******************* Bit definition for AES_IVR0 register *******************/
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#define AES_IVR0 ((uint32_t)0x0000FFFF) /*!< AES Initialization Vector Register 0 */
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/******************* Bit definition for AES_IVR1 register *******************/
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#define AES_IVR1 ((uint32_t)0x0000FFFF) /*!< AES Initialization Vector Register 1 */
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/******************* Bit definition for AES_IVR2 register *******************/
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#define AES_IVR2 ((uint32_t)0x0000FFFF) /*!< AES Initialization Vector Register 2 */
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/******************* Bit definition for AES_IVR3 register *******************/
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#define AES_IVR3 ((uint32_t)0x0000FFFF) /*!< AES Initialization Vector Register 3 */
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/******************************************************************************/
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/* */
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/* Analog Comparators (COMP) */
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/* */
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/******************************************************************************/
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/****************** Bit definition for COMP_CSR register ********************/
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#define COMP_CSR_10KPU ((uint32_t)0x00000001) /*!< 10K pull-up resistor */
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#define COMP_CSR_400KPU ((uint32_t)0x00000002) /*!< 400K pull-up resistor */
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#define COMP_CSR_10KPD ((uint32_t)0x00000004) /*!< 10K pull-down resistor */
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#define COMP_CSR_400KPD ((uint32_t)0x00000008) /*!< 400K pull-down resistor */
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#define COMP_CSR_CMP1EN ((uint32_t)0x00000010) /*!< Comparator 1 enable */
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#define COMP_CSR_SW1 ((uint32_t)0x00000020) /*!< SW1 analog switch enable */
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#define COMP_CSR_CMP1OUT ((uint32_t)0x00000080) /*!< Comparator 1 output */
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#define COMP_CSR_SPEED ((uint32_t)0x00001000) /*!< Comparator 2 speed */
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#define COMP_CSR_CMP2OUT ((uint32_t)0x00002000) /*!< Comparator 2 ouput */
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#define COMP_CSR_VREFOUTEN ((uint32_t)0x00010000) /*!< Comparator Vref Enable */
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#define COMP_CSR_WNDWE ((uint32_t)0x00020000) /*!< Window mode enable */
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#define COMP_CSR_INSEL ((uint32_t)0x001C0000) /*!< INSEL[2:0] Inversion input Selection */
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#define COMP_CSR_INSEL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
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#define COMP_CSR_INSEL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
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#define COMP_CSR_INSEL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
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#define COMP_CSR_OUTSEL ((uint32_t)0x00E00000) /*!< OUTSEL[2:0] comparator 2 output redirection */
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#define COMP_CSR_OUTSEL_0 ((uint32_t)0x00200000) /*!< Bit 0 */
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#define COMP_CSR_OUTSEL_1 ((uint32_t)0x00400000) /*!< Bit 1 */
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#define COMP_CSR_OUTSEL_2 ((uint32_t)0x00800000) /*!< Bit 2 */
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#define COMP_CSR_FCH3 ((uint32_t)0x04000000) /*!< Bit 26 */
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#define COMP_CSR_FCH8 ((uint32_t)0x08000000) /*!< Bit 27 */
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#define COMP_CSR_RCH13 ((uint32_t)0x10000000) /*!< Bit 28 */
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#define COMP_CSR_CAIE ((uint32_t)0x20000000) /*!< Bit 29 */
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#define COMP_CSR_CAIF ((uint32_t)0x40000000) /*!< Bit 30 */
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#define COMP_CSR_TSUSP ((uint32_t)0x80000000) /*!< Bit 31 */
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/******************************************************************************/
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/* */
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/* Operational Amplifier (OPAMP) */
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/* */
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/******************************************************************************/
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/******************* Bit definition for OPAMP_CSR register ******************/
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#define OPAMP_CSR_OPA1PD ((uint32_t)0x00000001) /*!< OPAMP1 disable */
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#define OPAMP_CSR_S3SEL1 ((uint32_t)0x00000002) /*!< Switch 3 for OPAMP1 Enable */
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#define OPAMP_CSR_S4SEL1 ((uint32_t)0x00000004) /*!< Switch 4 for OPAMP1 Enable */
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#define OPAMP_CSR_S5SEL1 ((uint32_t)0x00000008) /*!< Switch 5 for OPAMP1 Enable */
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#define OPAMP_CSR_S6SEL1 ((uint32_t)0x00000010) /*!< Switch 6 for OPAMP1 Enable */
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#define OPAMP_CSR_OPA1CAL_L ((uint32_t)0x00000020) /*!< OPAMP1 Offset calibration for P differential pair */
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#define OPAMP_CSR_OPA1CAL_H ((uint32_t)0x00000040) /*!< OPAMP1 Offset calibration for N differential pair */
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#define OPAMP_CSR_OPA1LPM ((uint32_t)0x00000080) /*!< OPAMP1 Low power enable */
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#define OPAMP_CSR_OPA2PD ((uint32_t)0x00000100) /*!< OPAMP2 disable */
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#define OPAMP_CSR_S3SEL2 ((uint32_t)0x00000200) /*!< Switch 3 for OPAMP2 Enable */
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#define OPAMP_CSR_S4SEL2 ((uint32_t)0x00000400) /*!< Switch 4 for OPAMP2 Enable */
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#define OPAMP_CSR_S5SEL2 ((uint32_t)0x00000800) /*!< Switch 5 for OPAMP2 Enable */
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#define OPAMP_CSR_S6SEL2 ((uint32_t)0x00001000) /*!< Switch 6 for OPAMP2 Enable */
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#define OPAMP_CSR_OPA2CAL_L ((uint32_t)0x00002000) /*!< OPAMP2 Offset calibration for P differential pair */
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#define OPAMP_CSR_OPA2CAL_H ((uint32_t)0x00004000) /*!< OPAMP2 Offset calibration for N differential pair */
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#define OPAMP_CSR_OPA2LPM ((uint32_t)0x00008000) /*!< OPAMP2 Low power enable */
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#define OPAMP_CSR_OPA3PD ((uint32_t)0x00010000) /*!< OPAMP3 disable */
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#define OPAMP_CSR_S3SEL3 ((uint32_t)0x00020000) /*!< Switch 3 for OPAMP3 Enable */
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#define OPAMP_CSR_S4SEL3 ((uint32_t)0x00040000) /*!< Switch 4 for OPAMP3 Enable */
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#define OPAMP_CSR_S5SEL3 ((uint32_t)0x00080000) /*!< Switch 5 for OPAMP3 Enable */
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#define OPAMP_CSR_S6SEL3 ((uint32_t)0x00100000) /*!< Switch 6 for OPAMP3 Enable */
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#define OPAMP_CSR_OPA3CAL_L ((uint32_t)0x00200000) /*!< OPAMP3 Offset calibration for P differential pair */
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#define OPAMP_CSR_OPA3CAL_H ((uint32_t)0x00400000) /*!< OPAMP3 Offset calibration for N differential pair */
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#define OPAMP_CSR_OPA3LPM ((uint32_t)0x00800000) /*!< OPAMP3 Low power enable */
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#define OPAMP_CSR_ANAWSEL1 ((uint32_t)0x01000000) /*!< Switch ANA Enable for OPAMP1 */
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#define OPAMP_CSR_ANAWSEL2 ((uint32_t)0x02000000) /*!< Switch ANA Enable for OPAMP2 */
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#define OPAMP_CSR_ANAWSEL3 ((uint32_t)0x04000000) /*!< Switch ANA Enable for OPAMP3 */
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#define OPAMP_CSR_S7SEL2 ((uint32_t)0x08000000) /*!< Switch 7 for OPAMP2 Enable */
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#define OPAMP_CSR_AOP_RANGE ((uint32_t)0x10000000) /*!< Power range selection */
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#define OPAMP_CSR_OPA1CALOUT ((uint32_t)0x20000000) /*!< OPAMP1 calibration output */
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#define OPAMP_CSR_OPA2CALOUT ((uint32_t)0x40000000) /*!< OPAMP2 calibration output */
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#define OPAMP_CSR_OPA3CALOUT ((uint32_t)0x80000000) /*!< OPAMP3 calibration output */
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/******************* Bit definition for OPAMP_OTR register ******************/
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#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM ((uint32_t)0x000003FF) /*!< Offset trim for OPAMP1 */
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#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM ((uint32_t)0x000FFC00) /*!< Offset trim for OPAMP2 */
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#define OPAMP_OTR_AO3_OPT_OFFSET_TRIM ((uint32_t)0x3FF00000) /*!< Offset trim for OPAMP2 */
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#define OPAMP_OTR_OT_USER ((uint32_t)0x80000000) /*!< Switch to OPAMP offset user trimmed values */
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/******************* Bit definition for OPAMP_LPOTR register ****************/
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#define OPAMP_LP_OTR_AO1_OPT_OFFSET_TRIM_LP ((uint32_t)0x000003FF) /*!< Offset trim in low power for OPAMP1 */
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#define OPAMP_LP_OTR_AO2_OPT_OFFSET_TRIM_LP ((uint32_t)0x000FFC00) /*!< Offset trim in low power for OPAMP2 */
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#define OPAMP_LP_OTR_AO3_OPT_OFFSET_TRIM_LP ((uint32_t)0x3FF00000) /*!< Offset trim in low power for OPAMP3 */
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/******************************************************************************/
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/* */
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/* CRC calculation unit (CRC) */
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/* */
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/******************************************************************************/
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/******************* Bit definition for CRC_DR register *********************/
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#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
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/******************* Bit definition for CRC_IDR register ********************/
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#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
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/******************** Bit definition for CRC_CR register ********************/
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#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET bit */
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/******************************************************************************/
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/* */
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/* Digital to Analog Converter (DAC) */
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/* */
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/******************************************************************************/
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/******************** Bit definition for DAC_CR register ********************/
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#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */
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#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */
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#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */
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#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
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#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
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#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
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#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
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#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
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#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */
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#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */
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#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
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#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */
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#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */
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#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */
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#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */
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#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */
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#define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun interrupt enable */
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#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */
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#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */
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#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */
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#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
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#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */
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#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */
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#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */
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#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
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#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */
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#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */
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#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
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#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
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#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
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#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
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#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
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#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */
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#define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun interrupt enable */
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/***************** Bit definition for DAC_SWTRIGR register ******************/
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#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!<DAC channel1 software trigger */
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#define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /*!<DAC channel2 software trigger */
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/***************** Bit definition for DAC_DHR12R1 register ******************/
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#define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */
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/***************** Bit definition for DAC_DHR12L1 register ******************/
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#define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */
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/****************** Bit definition for DAC_DHR8R1 register ******************/
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#define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */
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/***************** Bit definition for DAC_DHR12R2 register ******************/
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#define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */
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/***************** Bit definition for DAC_DHR12L2 register ******************/
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#define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */
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/****************** Bit definition for DAC_DHR8R2 register ******************/
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#define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */
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/***************** Bit definition for DAC_DHR12RD register ******************/
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#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */
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#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */
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/***************** Bit definition for DAC_DHR12LD register ******************/
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#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */
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#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */
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/****************** Bit definition for DAC_DHR8RD register ******************/
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#define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */
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#define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */
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/******************* Bit definition for DAC_DOR1 register *******************/
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#define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*!<DAC channel1 data output */
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/******************* Bit definition for DAC_DOR2 register *******************/
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#define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!<DAC channel2 data output */
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/******************** Bit definition for DAC_SR register ********************/
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#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */
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#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */
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/******************************************************************************/
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/* */
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/* Debug MCU (DBGMCU) */
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/* */
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/******************************************************************************/
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|
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/**************** Bit definition for DBGMCU_IDCODE register *****************/
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#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */
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#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */
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#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */
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#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */
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#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */
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#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */
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#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */
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#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */
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#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */
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#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */
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#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */
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#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */
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#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */
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#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */
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#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */
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#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */
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#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */
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#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */
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/****************** Bit definition for DBGMCU_CR register *******************/
|
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#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /*!< Debug Sleep Mode */
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#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */
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#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */
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#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) /*!< Trace Pin Assignment Control */
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#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
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#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /*!< Bit 0 */
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#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /*!< Bit 1 */
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/****************** Bit definition for DBGMCU_APB1_FZ register **************/
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#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) /*!< TIM2 counter stopped when core is halted */
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#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) /*!< TIM3 counter stopped when core is halted */
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#define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004) /*!< TIM4 counter stopped when core is halted */
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#define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008) /*!< TIM5 counter stopped when core is halted */
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#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) /*!< TIM6 counter stopped when core is halted */
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#define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020) /*!< TIM7 counter stopped when core is halted */
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#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) /*!< RTC Counter stopped when Core is halted */
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#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) /*!< Debug Window Watchdog stopped when Core is halted */
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#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) /*!< Debug Independent Watchdog stopped when Core is halted */
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#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) /*!< SMBUS timeout mode stopped when Core is halted */
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#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000) /*!< SMBUS timeout mode stopped when Core is halted */
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/****************** Bit definition for DBGMCU_APB2_FZ register **************/
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#define DBGMCU_APB2_FZ_DBG_TIM9_STOP ((uint32_t)0x00000004) /*!< TIM9 counter stopped when core is halted */
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#define DBGMCU_APB2_FZ_DBG_TIM10_STOP ((uint32_t)0x00000008) /*!< TIM10 counter stopped when core is halted */
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#define DBGMCU_APB2_FZ_DBG_TIM11_STOP ((uint32_t)0x00000010) /*!< TIM11 counter stopped when core is halted */
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|
|
/******************************************************************************/
|
|
/* */
|
|
/* DMA Controller (DMA) */
|
|
/* */
|
|
/******************************************************************************/
|
|
|
|
/******************* Bit definition for DMA_ISR register ********************/
|
|
#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
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#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
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#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
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#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
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#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
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#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
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#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
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#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
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#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
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#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
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#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
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#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
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#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
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#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
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#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
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#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
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#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
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#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
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#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
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#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
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#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */
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#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */
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#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */
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#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */
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#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */
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#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */
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#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */
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#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */
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/******************* Bit definition for DMA_IFCR register *******************/
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#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clearr */
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#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
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#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
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#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
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#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
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#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
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#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
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#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
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#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
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#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
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#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
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#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
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#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
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#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
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#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
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#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
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#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
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#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
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#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
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#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
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#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */
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#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */
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#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */
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#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */
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#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */
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#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */
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#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */
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#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */
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/******************* Bit definition for DMA_CCR1 register *******************/
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#define DMA_CCR1_EN ((uint16_t)0x0001) /*!< Channel enable*/
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#define DMA_CCR1_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
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#define DMA_CCR1_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
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#define DMA_CCR1_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
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#define DMA_CCR1_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
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#define DMA_CCR1_CIRC ((uint16_t)0x0020) /*!< Circular mode */
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#define DMA_CCR1_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
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#define DMA_CCR1_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
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#define DMA_CCR1_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
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#define DMA_CCR1_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
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#define DMA_CCR1_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
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#define DMA_CCR1_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
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#define DMA_CCR1_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
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#define DMA_CCR1_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
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#define DMA_CCR1_PL ((uint16_t)0x3000) /*!< PL[1:0] bits(Channel Priority level) */
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#define DMA_CCR1_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
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#define DMA_CCR1_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
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#define DMA_CCR1_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
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/******************* Bit definition for DMA_CCR2 register *******************/
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#define DMA_CCR2_EN ((uint16_t)0x0001) /*!< Channel enable */
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#define DMA_CCR2_TCIE ((uint16_t)0x0002) /*!< ransfer complete interrupt enable */
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#define DMA_CCR2_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
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#define DMA_CCR2_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
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#define DMA_CCR2_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
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#define DMA_CCR2_CIRC ((uint16_t)0x0020) /*!< Circular mode */
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#define DMA_CCR2_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
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#define DMA_CCR2_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
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#define DMA_CCR2_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
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#define DMA_CCR2_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
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#define DMA_CCR2_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
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#define DMA_CCR2_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
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#define DMA_CCR2_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
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#define DMA_CCR2_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
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#define DMA_CCR2_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
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#define DMA_CCR2_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
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#define DMA_CCR2_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
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#define DMA_CCR2_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
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/******************* Bit definition for DMA_CCR3 register *******************/
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#define DMA_CCR3_EN ((uint16_t)0x0001) /*!< Channel enable */
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#define DMA_CCR3_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
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#define DMA_CCR3_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
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#define DMA_CCR3_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
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#define DMA_CCR3_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
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#define DMA_CCR3_CIRC ((uint16_t)0x0020) /*!< Circular mode */
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#define DMA_CCR3_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
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#define DMA_CCR3_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
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#define DMA_CCR3_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
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#define DMA_CCR3_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
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#define DMA_CCR3_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
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#define DMA_CCR3_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
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#define DMA_CCR3_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
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#define DMA_CCR3_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
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#define DMA_CCR3_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
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#define DMA_CCR3_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
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#define DMA_CCR3_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
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#define DMA_CCR3_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
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/*!<****************** Bit definition for DMA_CCR4 register *******************/
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#define DMA_CCR4_EN ((uint16_t)0x0001) /*!< Channel enable */
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#define DMA_CCR4_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
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#define DMA_CCR4_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
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#define DMA_CCR4_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
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#define DMA_CCR4_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
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#define DMA_CCR4_CIRC ((uint16_t)0x0020) /*!< Circular mode */
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#define DMA_CCR4_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
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#define DMA_CCR4_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
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#define DMA_CCR4_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
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#define DMA_CCR4_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
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#define DMA_CCR4_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
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#define DMA_CCR4_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
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#define DMA_CCR4_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
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#define DMA_CCR4_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
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#define DMA_CCR4_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
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#define DMA_CCR4_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
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#define DMA_CCR4_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
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#define DMA_CCR4_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
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/****************** Bit definition for DMA_CCR5 register *******************/
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#define DMA_CCR5_EN ((uint16_t)0x0001) /*!< Channel enable */
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#define DMA_CCR5_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
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#define DMA_CCR5_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
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#define DMA_CCR5_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
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#define DMA_CCR5_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
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#define DMA_CCR5_CIRC ((uint16_t)0x0020) /*!< Circular mode */
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#define DMA_CCR5_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
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#define DMA_CCR5_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
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#define DMA_CCR5_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
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#define DMA_CCR5_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
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#define DMA_CCR5_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
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#define DMA_CCR5_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
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#define DMA_CCR5_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
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#define DMA_CCR5_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
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#define DMA_CCR5_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
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#define DMA_CCR5_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
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#define DMA_CCR5_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
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#define DMA_CCR5_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */
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/******************* Bit definition for DMA_CCR6 register *******************/
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#define DMA_CCR6_EN ((uint16_t)0x0001) /*!< Channel enable */
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#define DMA_CCR6_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
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#define DMA_CCR6_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
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#define DMA_CCR6_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
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#define DMA_CCR6_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
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#define DMA_CCR6_CIRC ((uint16_t)0x0020) /*!< Circular mode */
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#define DMA_CCR6_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
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#define DMA_CCR6_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
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#define DMA_CCR6_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
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#define DMA_CCR6_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
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#define DMA_CCR6_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
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#define DMA_CCR6_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
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#define DMA_CCR6_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
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#define DMA_CCR6_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
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#define DMA_CCR6_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
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#define DMA_CCR6_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
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#define DMA_CCR6_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
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#define DMA_CCR6_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
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/******************* Bit definition for DMA_CCR7 register *******************/
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#define DMA_CCR7_EN ((uint16_t)0x0001) /*!< Channel enable */
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#define DMA_CCR7_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
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#define DMA_CCR7_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
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#define DMA_CCR7_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
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#define DMA_CCR7_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
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#define DMA_CCR7_CIRC ((uint16_t)0x0020) /*!< Circular mode */
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#define DMA_CCR7_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
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#define DMA_CCR7_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
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#define DMA_CCR7_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
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#define DMA_CCR7_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
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#define DMA_CCR7_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
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#define DMA_CCR7_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
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#define DMA_CCR7_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
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#define DMA_CCR7_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
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#define DMA_CCR7_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
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#define DMA_CCR7_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
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#define DMA_CCR7_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
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#define DMA_CCR7_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */
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/****************** Bit definition for DMA_CNDTR1 register ******************/
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#define DMA_CNDTR1_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
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/****************** Bit definition for DMA_CNDTR2 register ******************/
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#define DMA_CNDTR2_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
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/****************** Bit definition for DMA_CNDTR3 register ******************/
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#define DMA_CNDTR3_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
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/****************** Bit definition for DMA_CNDTR4 register ******************/
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#define DMA_CNDTR4_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
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/****************** Bit definition for DMA_CNDTR5 register ******************/
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#define DMA_CNDTR5_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
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/****************** Bit definition for DMA_CNDTR6 register ******************/
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#define DMA_CNDTR6_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
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/****************** Bit definition for DMA_CNDTR7 register ******************/
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#define DMA_CNDTR7_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
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/****************** Bit definition for DMA_CPAR1 register *******************/
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#define DMA_CPAR1_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
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/****************** Bit definition for DMA_CPAR2 register *******************/
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#define DMA_CPAR2_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
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/****************** Bit definition for DMA_CPAR3 register *******************/
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#define DMA_CPAR3_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
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/****************** Bit definition for DMA_CPAR4 register *******************/
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#define DMA_CPAR4_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
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/****************** Bit definition for DMA_CPAR5 register *******************/
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#define DMA_CPAR5_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
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/****************** Bit definition for DMA_CPAR6 register *******************/
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#define DMA_CPAR6_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
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/****************** Bit definition for DMA_CPAR7 register *******************/
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#define DMA_CPAR7_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
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/****************** Bit definition for DMA_CMAR1 register *******************/
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#define DMA_CMAR1_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
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/****************** Bit definition for DMA_CMAR2 register *******************/
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#define DMA_CMAR2_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
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/****************** Bit definition for DMA_CMAR3 register *******************/
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#define DMA_CMAR3_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
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/****************** Bit definition for DMA_CMAR4 register *******************/
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#define DMA_CMAR4_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
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/****************** Bit definition for DMA_CMAR5 register *******************/
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#define DMA_CMAR5_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
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/****************** Bit definition for DMA_CMAR6 register *******************/
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#define DMA_CMAR6_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
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/****************** Bit definition for DMA_CMAR7 register *******************/
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#define DMA_CMAR7_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
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/******************************************************************************/
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/* */
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/* External Interrupt/Event Controller (EXTI) */
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/* */
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/******************************************************************************/
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/******************* Bit definition for EXTI_IMR register *******************/
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#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
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#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
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#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
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#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
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#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
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#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
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#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
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#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
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#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
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#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
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#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
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#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
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#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
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#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
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#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
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#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
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#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
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#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
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#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
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#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
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#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
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#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
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#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
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#define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
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/******************* Bit definition for EXTI_EMR register *******************/
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#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
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#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
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#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
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#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
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#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
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#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
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#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
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#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
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#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
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#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
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#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
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#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
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#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
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#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
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#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
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#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
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#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
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#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
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#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
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#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
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#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
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#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
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#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
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#define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
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/****************** Bit definition for EXTI_RTSR register *******************/
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#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
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#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
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#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
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#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
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#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
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#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
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#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
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#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
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#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
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#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
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#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
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#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
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#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
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#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
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#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
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#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
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#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
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#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
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#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
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#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
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#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
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#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
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#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
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#define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */
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/****************** Bit definition for EXTI_FTSR register *******************/
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#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
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#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
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#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
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#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
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#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
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#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
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#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
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#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
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#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
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#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
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#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
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#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
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#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
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#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
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#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
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#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
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#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
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#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
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#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
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#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
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#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
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#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
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#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
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#define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */
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/****************** Bit definition for EXTI_SWIER register ******************/
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#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
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#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
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#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
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#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
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#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
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#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
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#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
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#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
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#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
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#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
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#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
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#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
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#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
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#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
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#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
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#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
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#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
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#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
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#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
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#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
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#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
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#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
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#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
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#define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */
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/******************* Bit definition for EXTI_PR register ********************/
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#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit 0 */
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#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit 1 */
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#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit 2 */
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#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit 3 */
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#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit 4 */
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#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit 5 */
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#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit 6 */
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#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit 7 */
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#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit 8 */
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#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit 9 */
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#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit 10 */
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#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit 11 */
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#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit 12 */
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#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit 13 */
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#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit 14 */
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#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit 15 */
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#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit 16 */
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#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit 17 */
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#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit 18 */
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#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit 19 */
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#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit 20 */
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#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit 21 */
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#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit 22 */
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#define EXTI_PR_PR23 ((uint32_t)0x00800000) /*!< Pending bit 23 */
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/******************************************************************************/
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/* */
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/* FLASH, DATA EEPROM and Option Bytes Registers */
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/* (FLASH, DATA_EEPROM, OB) */
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/* */
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/******************************************************************************/
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/******************* Bit definition for FLASH_ACR register ******************/
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#define FLASH_ACR_LATENCY ((uint32_t)0x00000001) /*!< Latency */
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#define FLASH_ACR_PRFTEN ((uint32_t)0x00000002) /*!< Prefetch Buffer Enable */
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#define FLASH_ACR_ACC64 ((uint32_t)0x00000004) /*!< Access 64 bits */
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#define FLASH_ACR_SLEEP_PD ((uint32_t)0x00000008) /*!< Flash mode during sleep mode */
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#define FLASH_ACR_RUN_PD ((uint32_t)0x00000010) /*!< Flash mode during RUN mode */
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/******************* Bit definition for FLASH_PECR register ******************/
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#define FLASH_PECR_PELOCK ((uint32_t)0x00000001) /*!< FLASH_PECR and Flash data Lock */
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#define FLASH_PECR_PRGLOCK ((uint32_t)0x00000002) /*!< Program matrix Lock */
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#define FLASH_PECR_OPTLOCK ((uint32_t)0x00000004) /*!< Option byte matrix Lock */
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#define FLASH_PECR_PROG ((uint32_t)0x00000008) /*!< Program matrix selection */
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#define FLASH_PECR_DATA ((uint32_t)0x00000010) /*!< Data matrix selection */
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#define FLASH_PECR_FTDW ((uint32_t)0x00000100) /*!< Fixed Time Data write for Word/Half Word/Byte programming */
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#define FLASH_PECR_ERASE ((uint32_t)0x00000200) /*!< Page erasing mode */
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#define FLASH_PECR_FPRG ((uint32_t)0x00000400) /*!< Fast Page/Half Page programming mode */
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#define FLASH_PECR_PARALLBANK ((uint32_t)0x00008000) /*!< Parallel Bank mode */
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#define FLASH_PECR_EOPIE ((uint32_t)0x00010000) /*!< End of programming interrupt */
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#define FLASH_PECR_ERRIE ((uint32_t)0x00020000) /*!< Error interrupt */
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#define FLASH_PECR_OBL_LAUNCH ((uint32_t)0x00040000) /*!< Launch the option byte loading */
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/****************** Bit definition for FLASH_PDKEYR register ******************/
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#define FLASH_PDKEYR_PDKEYR ((uint32_t)0xFFFFFFFF) /*!< FLASH_PEC and data matrix Key */
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/****************** Bit definition for FLASH_PEKEYR register ******************/
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#define FLASH_PEKEYR_PEKEYR ((uint32_t)0xFFFFFFFF) /*!< FLASH_PEC and data matrix Key */
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/****************** Bit definition for FLASH_PRGKEYR register ******************/
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#define FLASH_PRGKEYR_PRGKEYR ((uint32_t)0xFFFFFFFF) /*!< Program matrix Key */
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/****************** Bit definition for FLASH_OPTKEYR register ******************/
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#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option bytes matrix Key */
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/****************** Bit definition for FLASH_SR register *******************/
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#define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */
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#define FLASH_SR_EOP ((uint32_t)0x00000002) /*!< End Of Programming*/
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#define FLASH_SR_ENHV ((uint32_t)0x00000004) /*!< End of high voltage */
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#define FLASH_SR_READY ((uint32_t)0x00000008) /*!< Flash ready after low power mode */
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#define FLASH_SR_WRPERR ((uint32_t)0x00000100) /*!< Write protected error */
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#define FLASH_SR_PGAERR ((uint32_t)0x00000200) /*!< Programming Alignment Error */
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#define FLASH_SR_SIZERR ((uint32_t)0x00000400) /*!< Size error */
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#define FLASH_SR_OPTVERR ((uint32_t)0x00000800) /*!< Option validity error */
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#define FLASH_SR_OPTVERRUSR ((uint32_t)0x00001000) /*!< Option User validity error */
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#define FLASH_SR_RDERR ((uint32_t)0x00002000) /*!< Read protected error */
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/****************** Bit definition for FLASH_OBR register *******************/
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#define FLASH_OBR_RDPRT ((uint32_t)0x000000AA) /*!< Read Protection */
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#define FLASH_OBR_SPRMOD ((uint32_t)0x00000100) /*!< Selection of protection mode of WPRi bits
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(available only in STM32L1xx Medium-density Plus devices) */
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#define FLASH_OBR_BOR_LEV ((uint32_t)0x000F0000) /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
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#define FLASH_OBR_IWDG_SW ((uint32_t)0x00100000) /*!< IWDG_SW */
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#define FLASH_OBR_nRST_STOP ((uint32_t)0x00200000) /*!< nRST_STOP */
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#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00400000) /*!< nRST_STDBY */
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#define FLASH_OBR_BFB2 ((uint32_t)0x00800000) /*!< BFB2(available only in STM32L1xx High-density devices) */
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/****************** Bit definition for FLASH_WRPR register ******************/
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#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protection bits */
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/****************** Bit definition for FLASH_WRPR1 register *****************/
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#define FLASH_WRPR1_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protection bits (available only in STM32L1xx
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Medium-density Plus and High-density devices) */
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/****************** Bit definition for FLASH_WRPR2 register *****************/
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#define FLASH_WRPR2_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protection bits (available only in STM32L1xx
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High-density devices) */
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/******************************************************************************/
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/* */
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/* Flexible Static Memory Controller */
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/* */
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/******************************************************************************/
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/****************** Bit definition for FSMC_BCR1 register *******************/
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#define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */
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#define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */
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#define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */
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#define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */
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#define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */
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#define FSMC_BCR1_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */
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#define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */
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#define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */
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#define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */
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#define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */
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#define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */
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#define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */
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#define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */
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#define FSMC_BCR1_WREN ((uint32_t)0x00001000) /*!< Write enable bit */
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#define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */
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#define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */
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#define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */
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#define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */
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/****************** Bit definition for FSMC_BCR2 register *******************/
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#define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */
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#define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */
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#define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */
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#define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */
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#define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */
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#define FSMC_BCR2_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */
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#define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */
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#define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */
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#define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */
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#define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */
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#define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */
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#define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */
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#define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */
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#define FSMC_BCR2_WREN ((uint32_t)0x00001000) /*!< Write enable bit */
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#define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */
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#define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */
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#define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */
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#define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */
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/****************** Bit definition for FSMC_BCR3 register *******************/
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#define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */
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#define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */
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#define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */
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#define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */
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#define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */
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#define FSMC_BCR3_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */
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#define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */
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#define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */
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#define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */
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#define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */
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#define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit. */
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#define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */
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#define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */
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#define FSMC_BCR3_WREN ((uint32_t)0x00001000) /*!< Write enable bit */
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#define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */
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#define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */
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#define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */
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#define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */
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/****************** Bit definition for FSMC_BCR4 register *******************/
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#define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */
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#define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */
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#define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */
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#define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */
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#define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */
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#define FSMC_BCR4_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */
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#define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */
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#define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */
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#define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */
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#define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */
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#define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */
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#define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */
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#define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */
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#define FSMC_BCR4_WREN ((uint32_t)0x00001000) /*!< Write enable bit */
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#define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */
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#define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */
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#define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */
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#define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */
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/****************** Bit definition for FSMC_BTR1 register ******************/
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#define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
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#define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
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#define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
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#define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
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#define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
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#define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
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#define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
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#define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
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#define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
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#define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
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#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
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#define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
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#define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
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#define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
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#define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
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#define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
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#define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */
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#define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */
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#define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */
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#define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */
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#define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
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#define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
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#define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
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#define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
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#define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
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#define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
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#define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
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#define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
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#define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
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#define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
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#define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
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#define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
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#define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
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/****************** Bit definition for FSMC_BTR2 register *******************/
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#define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
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#define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
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#define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
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#define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
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#define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
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#define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
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#define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
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#define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
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#define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
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#define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
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#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
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#define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
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#define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
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#define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
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#define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
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#define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
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#define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */
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#define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */
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#define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */
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#define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */
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#define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
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#define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
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#define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
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#define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
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#define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
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#define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
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#define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
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#define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
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#define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
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#define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
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#define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
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#define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
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#define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
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/******************* Bit definition for FSMC_BTR3 register *******************/
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#define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
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#define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
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#define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
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#define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
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#define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
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#define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
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#define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
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#define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
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#define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
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#define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
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#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
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