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288 lines
15 KiB
288 lines
15 KiB
//***************************************************************************** |
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// |
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// hw_ssi.h - Macros used when accessing the SSI hardware. |
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// |
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// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved. |
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// Software License Agreement |
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// |
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// Redistribution and use in source and binary forms, with or without |
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// modification, are permitted provided that the following conditions |
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// are met: |
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// |
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// Redistributions of source code must retain the above copyright |
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// notice, this list of conditions and the following disclaimer. |
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// |
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// Redistributions in binary form must reproduce the above copyright |
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// notice, this list of conditions and the following disclaimer in the |
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// documentation and/or other materials provided with the |
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// distribution. |
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// |
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// Neither the name of Texas Instruments Incorporated nor the names of |
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// its contributors may be used to endorse or promote products derived |
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// from this software without specific prior written permission. |
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// |
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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// |
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// This is part of revision 2.0.1.11577 of the Tiva Firmware Development Package. |
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// |
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//***************************************************************************** |
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#ifndef STELLARIS_HW_SSI_H |
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#define STELLARIS_HW_SSI_H |
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//***************************************************************************** |
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// |
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// The following are defines for the SSI register offsets. |
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// |
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//***************************************************************************** |
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#define SSI_O_CR0 0x00000000 // SSI Control 0 |
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#define SSI_O_CR1 0x00000004 // SSI Control 1 |
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#define SSI_O_DR 0x00000008 // SSI Data |
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#define SSI_O_SR 0x0000000C // SSI Status |
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#define SSI_O_CPSR 0x00000010 // SSI Clock Prescale |
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#define SSI_O_IM 0x00000014 // SSI Interrupt Mask |
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#define SSI_O_RIS 0x00000018 // SSI Raw Interrupt Status |
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#define SSI_O_MIS 0x0000001C // SSI Masked Interrupt Status |
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#define SSI_O_ICR 0x00000020 // SSI Interrupt Clear |
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#define SSI_O_DMACTL 0x00000024 // SSI DMA Control |
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#define SSI_O_PP 0x00000FC0 // SSI Peripheral Properties |
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#define SSI_O_CC 0x00000FC8 // SSI Clock Configuration |
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//***************************************************************************** |
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// |
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// The following are defines for the bit fields in the SSI_O_CR0 register. |
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// |
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//***************************************************************************** |
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#define SSI_CR0_SCR_M 0x0000FF00 // SSI Serial Clock Rate |
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#define SSI_CR0_SPH 0x00000080 // SSI Serial Clock Phase |
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#define SSI_CR0_SPO 0x00000040 // SSI Serial Clock Polarity |
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#define SSI_CR0_FRF_M 0x00000030 // SSI Frame Format Select |
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#define SSI_CR0_FRF_MOTO 0x00000000 // Freescale SPI Frame Format |
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#define SSI_CR0_FRF_TI 0x00000010 // Texas Instruments Synchronous |
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// Serial Frame Format |
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#define SSI_CR0_FRF_NMW 0x00000020 // MICROWIRE Frame Format |
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#define SSI_CR0_DSS_M 0x0000000F // SSI Data Size Select |
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#define SSI_CR0_DSS_4 0x00000003 // 4-bit data |
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#define SSI_CR0_DSS_5 0x00000004 // 5-bit data |
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#define SSI_CR0_DSS_6 0x00000005 // 6-bit data |
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#define SSI_CR0_DSS_7 0x00000006 // 7-bit data |
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#define SSI_CR0_DSS_8 0x00000007 // 8-bit data |
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#define SSI_CR0_DSS_9 0x00000008 // 9-bit data |
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#define SSI_CR0_DSS_10 0x00000009 // 10-bit data |
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#define SSI_CR0_DSS_11 0x0000000A // 11-bit data |
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#define SSI_CR0_DSS_12 0x0000000B // 12-bit data |
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#define SSI_CR0_DSS_13 0x0000000C // 13-bit data |
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#define SSI_CR0_DSS_14 0x0000000D // 14-bit data |
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#define SSI_CR0_DSS_15 0x0000000E // 15-bit data |
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#define SSI_CR0_DSS_16 0x0000000F // 16-bit data |
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#define SSI_CR0_SCR_S 8 |
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//***************************************************************************** |
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// |
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// The following are defines for the bit fields in the SSI_O_CR1 register. |
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// |
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//***************************************************************************** |
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#define SSI_CR1_EOM 0x00000800 // Stop Frame (End of Message) |
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#define SSI_CR1_FSSHLDFRM 0x00000400 // FSS Hold Frame |
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#define SSI_CR1_HSCLKEN 0x00000200 // High Speed Clock Enable |
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#define SSI_CR1_DIR 0x00000100 // SSI Direction of Operation |
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#define SSI_CR1_MODE_M 0x000000C0 // SSI Mode |
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#define SSI_CR1_MODE_LEGACY 0x00000000 // Legacy SSI mode |
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#define SSI_CR1_MODE_BI 0x00000040 // Bi-SSI mode |
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#define SSI_CR1_MODE_QUAD 0x00000080 // Quad-SSI Mode |
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#define SSI_CR1_MODE_ADVANCED 0x000000C0 // Advanced SSI Mode |
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#define SSI_CR1_EOT 0x00000010 // End of Transmission |
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#define SSI_CR1_SOD 0x00000008 // SSI Slave Mode Output Disable |
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#define SSI_CR1_MS 0x00000004 // SSI Master/Slave Select |
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#define SSI_CR1_SSE 0x00000002 // SSI Synchronous Serial Port |
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// Enable |
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#define SSI_CR1_LBM 0x00000001 // SSI Loopback Mode |
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//***************************************************************************** |
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// |
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// The following are defines for the bit fields in the SSI_O_DR register. |
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// |
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//***************************************************************************** |
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#define SSI_DR_DATA_M 0x0000FFFF // SSI Receive/Transmit Data |
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#define SSI_DR_DATA_S 0 |
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//***************************************************************************** |
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// |
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// The following are defines for the bit fields in the SSI_O_SR register. |
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// |
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//***************************************************************************** |
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#define SSI_SR_BSY 0x00000010 // SSI Busy Bit |
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#define SSI_SR_RFF 0x00000008 // SSI Receive FIFO Full |
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#define SSI_SR_RNE 0x00000004 // SSI Receive FIFO Not Empty |
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#define SSI_SR_TNF 0x00000002 // SSI Transmit FIFO Not Full |
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#define SSI_SR_TFE 0x00000001 // SSI Transmit FIFO Empty |
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//***************************************************************************** |
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// |
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// The following are defines for the bit fields in the SSI_O_CPSR register. |
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// |
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//***************************************************************************** |
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#define SSI_CPSR_CPSDVSR_M 0x000000FF // SSI Clock Prescale Divisor |
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#define SSI_CPSR_CPSDVSR_S 0 |
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//***************************************************************************** |
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// |
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// The following are defines for the bit fields in the SSI_O_IM register. |
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// |
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//***************************************************************************** |
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#define SSI_IM_EOTIM 0x00000040 // End of Transmit Interrupt Mask |
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#define SSI_IM_DMATXIM 0x00000020 // SSI Transmit DMA Interrupt Mask |
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#define SSI_IM_DMARXIM 0x00000010 // SSI Receive DMA Interrupt Mask |
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#define SSI_IM_TXIM 0x00000008 // SSI Transmit FIFO Interrupt Mask |
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#define SSI_IM_RXIM 0x00000004 // SSI Receive FIFO Interrupt Mask |
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#define SSI_IM_RTIM 0x00000002 // SSI Receive Time-Out Interrupt |
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// Mask |
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#define SSI_IM_RORIM 0x00000001 // SSI Receive Overrun Interrupt |
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// Mask |
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//***************************************************************************** |
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// |
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// The following are defines for the bit fields in the SSI_O_RIS register. |
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// |
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//***************************************************************************** |
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#define SSI_RIS_EOTRIS 0x00000040 // End of Transmit Raw Interrupt |
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// Status |
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#define SSI_RIS_DMATXRIS 0x00000020 // SSI Transmit DMA Raw Interrupt |
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// Status |
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#define SSI_RIS_DMARXRIS 0x00000010 // SSI Receive DMA Raw Interrupt |
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// Status |
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#define SSI_RIS_TXRIS 0x00000008 // SSI Transmit FIFO Raw Interrupt |
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// Status |
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#define SSI_RIS_RXRIS 0x00000004 // SSI Receive FIFO Raw Interrupt |
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// Status |
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#define SSI_RIS_RTRIS 0x00000002 // SSI Receive Time-Out Raw |
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// Interrupt Status |
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#define SSI_RIS_RORRIS 0x00000001 // SSI Receive Overrun Raw |
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// Interrupt Status |
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//***************************************************************************** |
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// |
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// The following are defines for the bit fields in the SSI_O_MIS register. |
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// |
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//***************************************************************************** |
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#define SSI_MIS_EOTMIS 0x00000040 // End of Transmit Masked Interrupt |
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// Status |
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#define SSI_MIS_DMATXMIS 0x00000020 // SSI Transmit DMA Masked |
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// Interrupt Status |
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#define SSI_MIS_DMARXMIS 0x00000010 // SSI Receive DMA Masked Interrupt |
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// Status |
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#define SSI_MIS_TXMIS 0x00000008 // SSI Transmit FIFO Masked |
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// Interrupt Status |
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#define SSI_MIS_RXMIS 0x00000004 // SSI Receive FIFO Masked |
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// Interrupt Status |
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#define SSI_MIS_RTMIS 0x00000002 // SSI Receive Time-Out Masked |
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// Interrupt Status |
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#define SSI_MIS_RORMIS 0x00000001 // SSI Receive Overrun Masked |
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// Interrupt Status |
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//***************************************************************************** |
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// |
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// The following are defines for the bit fields in the SSI_O_ICR register. |
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// |
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//***************************************************************************** |
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#define SSI_ICR_EOTIC 0x00000040 // End of Transmit Interrupt Clear |
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#define SSI_ICR_DMATXIC 0x00000020 // SSI Transmit DMA Interrupt Clear |
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#define SSI_ICR_DMARXIC 0x00000010 // SSI Receive DMA Interrupt Clear |
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#define SSI_ICR_RTIC 0x00000002 // SSI Receive Time-Out Interrupt |
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// Clear |
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#define SSI_ICR_RORIC 0x00000001 // SSI Receive Overrun Interrupt |
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// Clear |
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//***************************************************************************** |
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// |
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// The following are defines for the bit fields in the SSI_O_DMACTL register. |
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// |
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//***************************************************************************** |
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#define SSI_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable |
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#define SSI_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable |
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//***************************************************************************** |
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// |
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// The following are defines for the bit fields in the SSI_O_PP register. |
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// |
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//***************************************************************************** |
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#define SSI_PP_FSSHLDFRM 0x00000008 // FSS Hold Frame Capability |
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#define SSI_PP_MODE_M 0x00000006 // Mode of Operation |
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#define SSI_PP_MODE_LEGACY 0x00000000 // Legacy SSI mode |
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#define SSI_PP_MODE_ADVBI 0x00000002 // Advanced SSI and Bi-SSI |
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#define SSI_PP_MODE_ADVBIQUAD 0x00000004 // Advanced, Bi- and Quad-SSI |
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#define SSI_PP_HSCLK 0x00000001 // High Speed Capability |
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//***************************************************************************** |
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// |
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// The following are defines for the bit fields in the SSI_O_CC register. |
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// |
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//***************************************************************************** |
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#define SSI_CC_CS_M 0x0000000F // SSI Baud Clock Source |
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#define SSI_CC_CS_SYSPLL 0x00000000 // Either the system clock (if the |
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// PLL bypass is in effect) or the |
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// PLL output (default) |
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#define SSI_CC_CS_PIOSC 0x00000005 // PIOSC |
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//***************************************************************************** |
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// |
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// The following definitions are deprecated. |
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// |
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//***************************************************************************** |
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#ifndef DEPRECATED |
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//***************************************************************************** |
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// |
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// The following are deprecated defines for the bit fields in the SSI_O_CR0 |
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// register. |
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// |
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//***************************************************************************** |
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#define SSI_CR0_SCR 0x0000FF00 // Serial clock rate |
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#define SSI_CR0_FRF_MASK 0x00000030 // Frame format mask |
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#define SSI_CR0_DSS 0x0000000F // Data size select |
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//***************************************************************************** |
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// |
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// The following are deprecated defines for the bit fields in the SSI_O_CPSR |
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// register. |
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// |
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//***************************************************************************** |
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#define SSI_CPSR_CPSDVSR_MASK 0x000000FF // Clock prescale |
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//***************************************************************************** |
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// |
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// The following are deprecated defines for the SSI controller's FIFO size. |
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// |
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//***************************************************************************** |
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#define TX_FIFO_SIZE (8) // Number of entries in the TX FIFO |
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#define RX_FIFO_SIZE (8) // Number of entries in the RX FIFO |
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//***************************************************************************** |
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// |
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// The following are deprecated defines for the bit fields in the interrupt |
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// mask set and clear, raw interrupt, masked interrupt, and interrupt clear |
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// registers. |
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// |
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//***************************************************************************** |
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#define SSI_INT_TXFF 0x00000008 // TX FIFO interrupt |
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#define SSI_INT_RXFF 0x00000004 // RX FIFO interrupt |
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#define SSI_INT_RXTO 0x00000002 // RX timeout interrupt |
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#define SSI_INT_RXOR 0x00000001 // RX overrun interrupt |
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#endif |
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#ifdef __cplusplus |
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} |
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#endif |
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#endif /* STELLARIS_HW_SSI_H */
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