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192 lines
5.4 KiB
192 lines
5.4 KiB
/* |
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* Copyright (C) 2015 Rakendra Thapa <rakendrathapa@gmail.com> |
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* Copyright (C) 2017 Marc Poulhiès <dkm@kataplop.net> |
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* |
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* This file is subject to the terms and conditions of the GNU Lesser |
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* General Public License v2.1. See the file LICENSE in the top level |
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* directory for more details. |
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*/ |
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/** |
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* @ingroup cpu_lm4f120 |
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* @{ |
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* |
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* @file |
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* @brief CPU specific definitions for internal peripheral handling |
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* |
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* @author Rakendra Thapa <rakendrathapa@gmail.com> |
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* @author Marc Poulhiès <dkm@kataplop.net> |
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*/ |
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#ifndef PERIPH_CPU_H |
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#define PERIPH_CPU_H |
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#include "cpu_conf.h" |
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#ifdef __cplusplus |
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extern "C" { |
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#endif |
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/** |
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* @brief Overwrite the default gpio_t type definition |
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* @{ |
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*/ |
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#define HAVE_GPIO_T |
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typedef uint32_t gpio_t; |
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#define GPIO_PIN(x,y) ((gpio_t)((x<<4) | y)) |
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/** @} */ |
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#ifndef DOXYGEN |
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/** |
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* @brief Override GPIO modes |
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* @{ |
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*/ |
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#define HAVE_GPIO_MODE_T |
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typedef enum { |
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GPIO_IN = (GPIO_DIR_MODE_IN | (GPIO_PIN_TYPE_STD << 4)), /**< IN */ |
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GPIO_IN_PD = (GPIO_DIR_MODE_IN | (GPIO_PIN_TYPE_STD_WPD << 4)), /**< IN with pull-down */ |
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GPIO_IN_PU = (GPIO_DIR_MODE_IN | (GPIO_PIN_TYPE_STD_WPU << 4)), /**< IN with pull-up */ |
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GPIO_OUT = (GPIO_DIR_MODE_OUT | (GPIO_PIN_TYPE_STD << 4)), /**< OUT (push-pull) */ |
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GPIO_OD = (GPIO_DIR_MODE_OUT | (GPIO_PIN_TYPE_OD << 4)), /**< OD */ |
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GPIO_OD_PU = (GPIO_DIR_MODE_OUT | (GPIO_PIN_TYPE_OD_WPU << 4)), /**< OD with pull-up */ |
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} gpio_mode_t; |
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/** @} */ |
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#endif /* ndef DOXYGEN */ |
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/** |
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* @brief Override values for pin direction configuration |
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* @{ |
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*/ |
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#define HAVE_GPIO_DIR_T |
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typedef enum { |
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GPIO_DIR_IN = GPIO_DIR_MODE_IN, /**< configure pin as input */ |
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GPIO_DIR_OUT = GPIO_DIR_MODE_OUT /**< configure pin as output */ |
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} gpio_dir_t; |
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/** @} */ |
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#ifndef DOXYGEN |
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/** |
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* @brief Override active flank configuration values |
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* @{ |
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*/ |
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#define HAVE_GPIO_FLANK_T |
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typedef enum { |
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GPIO_FALLING = GPIO_FALLING_EDGE, /**< emit interrupt on falling flank */ |
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GPIO_RISING = GPIO_RISING_EDGE, /**< emit interrupt on rising flank */ |
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GPIO_BOTH = GPIO_BOTH_EDGES /**< emit interrupt on both flanks */ |
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} gpio_flank_t; |
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/** @} */ |
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#endif /* ndef DOXYGEN */ |
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/** |
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* @brief Available ports on the LM4F120 |
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*/ |
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enum { |
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PORT_A = 0, /**< port A */ |
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PORT_B = 1, /**< port B */ |
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PORT_C = 2, /**< port C */ |
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PORT_D = 3, /**< port D */ |
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PORT_E = 4, /**< port E */ |
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PORT_F = 5, /**< port F */ |
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}; |
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/** |
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* @name PWM configuration |
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* @{ |
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*/ |
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#define PWM_NUMOF (8) |
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#define PWM_0_EN 1 |
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#define PWM_1_EN 1 |
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#define PWM_2_EN 1 |
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#define PWM_3_EN 1 |
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#define PWM_4_EN 1 |
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#define PWM_5_EN 1 |
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#define PWM_6_EN 1 |
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#define PWM_7_EN 1 |
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#define PWM_MAX_CHANNELS 1 |
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/** @} */ |
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/** |
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* @brief Override resolution options |
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*/ |
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#ifndef DOXYGEN |
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#define HAVE_ADC_RES_T |
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typedef enum { |
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ADC_RES_6BIT = 0xa00, /**< not supported by hardware */ |
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ADC_RES_8BIT = 0xb00, /**< not supported by hardware */ |
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ADC_RES_10BIT = ADC_RES_10BIT_S, /**< ADC resolution: 10 bit */ |
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ADC_RES_12BIT = ADC_RES_12BIT_S, /**< ADC resolution: 12 bit */ |
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ADC_RES_14BIT = 0xc00, /**< not supported by hardware */ |
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ADC_RES_16BIT = 0xd00, /**< not supported by hardware */ |
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} adc_res_t; |
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#endif /* ndef DOXYGEN */ |
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/** |
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* @brief Override SPI hardware chip select macro |
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* |
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* As of now, we do not support HW CS, so we always set it to a fixed value |
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*/ |
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#define SPI_HWCS(x) (UINT_MAX - 1) |
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/** |
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* @brief SPI configuration data structure |
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* @{ |
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*/ |
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typedef struct { |
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unsigned long ssi_sysctl; /**< SSI device in sysctl */ |
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unsigned long ssi_base; /**< SSI base address */ |
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unsigned long gpio_sysctl; /**< GPIO device in sysctl */ |
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unsigned long gpio_port; /**< GPIO port */ |
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struct { |
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unsigned long clk; /**< pin used for SCK */ |
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unsigned long fss; /**< pin used for FSS */ |
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unsigned long rx; /**< pin used for MISO */ |
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unsigned long tx; /**< pin used for MOSI */ |
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unsigned long mask; /**< Pin mask */ |
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} pins; /**< Pin setting */ |
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} spi_conf_t; |
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/** @} */ |
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/** |
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* @brief declare needed generic SPI functions |
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* @{ |
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*/ |
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#define PERIPH_SPI_NEEDS_TRANSFER_BYTE 1 |
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#define PERIPH_SPI_NEEDS_TRANSFER_REG 1 |
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#define PERIPH_SPI_NEEDS_TRANSFER_REGS 1 |
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#define PERIPH_SPI_NEEDS_INIT_CS 1 |
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/** @} */ |
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/** |
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* @brief Override SPI clock speed values |
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* @{ |
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*/ |
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#define HAVE_SPI_CLK_T 1 |
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typedef enum { |
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SPI_CLK_100KHZ = 100000, /**< drive the SPI bus with 100KHz */ |
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SPI_CLK_400KHZ = 400000, /**< drive the SPI bus with 400KHz */ |
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SPI_CLK_1MHZ = 1000000, /**< drive the SPI bus with 1MHz */ |
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SPI_CLK_4MHZ = 4000000, /**< drive the SPI bus with 4MHz */ |
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SPI_CLK_5MHZ = 5000000, /**< drive the SPI bus with 5MHz */ |
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SPI_CLK_10MHZ = 10000000, /**< drive the SPI bus with 10MHz */ |
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} spi_clk_t; |
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/** @} */ |
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/** |
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* @brief Override SPI mode settings |
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* @{ |
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*/ |
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#define HAVE_SPI_MODE_T 1 |
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typedef enum { |
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SPI_MODE_0 = SSI_FRF_MOTO_MODE_0, /**< CPOL=0, CPHA=0 */ |
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SPI_MODE_1 = SSI_FRF_MOTO_MODE_1, /**< CPOL=0, CPHA=1 */ |
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SPI_MODE_2 = SSI_FRF_MOTO_MODE_2, /**< CPOL=1, CPHA=0 */ |
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SPI_MODE_3 = SSI_FRF_MOTO_MODE_0, /**< CPOL=1, CPHA=1 */ |
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} spi_mode_t; |
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/** @} */ |
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#ifdef __cplusplus |
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} |
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#endif |
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#endif /* PERIPH_CPU_H */ |
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/** @} */
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