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/*
** ###################################################################
** Compilers: Keil ARM C/C++ Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** GNU C Compiler - CodeSourcery Sourcery G++
** IAR ANSI C/C++ Compiler for ARM
**
** Reference manual: K60P144M100SF2V2RM Rev. 2, Jun 2012
** Version: rev. 1.8, 2014-10-14
** Build: b141015
**
** Abstract:
** CMSIS Peripheral Access Layer for MK60D10
**
** Copyright (c) 1997 - 2014 Freescale Semiconductor, Inc.
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** o Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** o Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** Revisions:
** - rev. 1.0 (2012-01-03)
** Initial version
** - rev. 1.1 (2012-04-13)
** Added new #define symbol MCU_MEM_MAP_VERSION_MINOR.
** Added new #define symbols <peripheralType>_BASE_PTRS.
** - rev. 1.2 (2012-07-09)
** UART0 - Fixed register definition - CEA709.1-B (LON) registers added.
** - rev. 1.3 (2012-10-29)
** Registers updated according to the new reference manual revision - Rev. 2, Jun 2012
** - rev. 1.4 (2013-04-05)
** Changed start of doxygen comment.
** - rev. 1.5 (2013-06-24)
** NV_FOPT register - NMI_DIS bit added.
** SPI - PCSIS bit group in MCR register updated.
** - rev. 1.6 (2014-07-23)
** Delay of 1 ms added to SystemInit() to ensure stable FLL output in FEI and FEE MCG modes.
** Predefined SystemInit() implementation updated:
** - External clock sources available on TWR board used.
** - Added 1 ms waiting loop after entering FLL engaged MCG mode.
** - rev. 1.7 (2014-08-28)
** Update of startup files - possibility to override DefaultISR added.
** - rev. 1.8 (2014-10-14)
** Renamed interrupt vector Watchdog to WDOG_EWM and LPTimer to LPTMR0
** - rev. 1.8-jg (2015-05-18)
** Removed BITBAND_REG macro.
**
** ###################################################################
*/
/*!
* @file MK60D10.h
* @version 1.8-jg
* @date 2015-05-18
* @brief CMSIS Peripheral Access Layer for MK60D10
*
* CMSIS Peripheral Access Layer for MK60D10
*/
#ifdef __cplusplus
extern "C"
{
#endif
/* ----------------------------------------------------------------------------
-- MCU activation
---------------------------------------------------------------------------- */
/* Prevention from multiple including the same memory map */
#if !defined(MK60D10_H_) /* Check if memory map has not been already included */
#define MK60D10_H_
#define MCU_MK60D10
/* Check if another memory map has not been also included */
#if (defined(MCU_ACTIVE))
#error MK60D10 memory map: There is already included another memory map. Only one memory map can be included.
#endif /* (defined(MCU_ACTIVE)) */
#define MCU_ACTIVE
#include <stdint.h>
/** Memory map major version (memory maps with equal major version number are
* compatible) */
#define MCU_MEM_MAP_VERSION 0x0100u
/** Memory map minor version */
#define MCU_MEM_MAP_VERSION_MINOR 0x0008u
/**
* @brief Macro to calculate address of an aliased word in the peripheral
* bitband area for a peripheral register and bit (bit band region 0x40000000 to
* 0x400FFFFF).
* @param Reg Register to access.
* @param Bit Bit number to access.
* @return Address of the aliased word in the peripheral bitband area.
*/
#define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))
/**
* @brief Macro to access a single bit of a peripheral register (bit band region
* 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
* be used for peripherals with 32bit access allowed.
* @param Reg Register to access.
* @param Bit Bit number to access.
* @return Value of the targeted bit in the bit band region.
*/
#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
/**
* @brief Macro to access a single bit of a peripheral register (bit band region
* 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
* be used for peripherals with 16bit access allowed.
* @param Reg Register to access.
* @param Bit Bit number to access.
* @return Value of the targeted bit in the bit band region.
*/
#define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
/**
* @brief Macro to access a single bit of a peripheral register (bit band region
* 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
* be used for peripherals with 8bit access allowed.
* @param Reg Register to access.
* @param Bit Bit number to access.
* @return Value of the targeted bit in the bit band region.
*/
#define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
/* ----------------------------------------------------------------------------
-- Interrupt vector numbers
---------------------------------------------------------------------------- */
/*!
* @addtogroup Interrupt_vector_numbers Interrupt vector numbers
* @{
*/
/** Interrupt Number Definitions */
#define NUMBER_OF_INT_VECTORS 120 /**< Number of interrupts in the Vector table */
typedef enum IRQn {
/* Auxiliary constants */
NotAvail_IRQn = -128, /**< Not available device specific interrupt */
/* Core interrupts */
NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */
MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
/* Device specific interrupts */
DMA0_IRQn = 0, /**< DMA channel 0 transfer complete */
DMA1_IRQn = 1, /**< DMA channel 1 transfer complete */
DMA2_IRQn = 2, /**< DMA channel 2 transfer complete */
DMA3_IRQn = 3, /**< DMA channel 3 transfer complete */
DMA4_IRQn = 4, /**< DMA channel 4 transfer complete */
DMA5_IRQn = 5, /**< DMA channel 5 transfer complete */
DMA6_IRQn = 6, /**< DMA channel 6 transfer complete */
DMA7_IRQn = 7, /**< DMA channel 7 transfer complete */
DMA8_IRQn = 8, /**< DMA channel 8 transfer complete */
DMA9_IRQn = 9, /**< DMA channel 9 transfer complete */
DMA10_IRQn = 10, /**< DMA channel 10 transfer complete */
DMA11_IRQn = 11, /**< DMA channel 11 transfer complete */
DMA12_IRQn = 12, /**< DMA channel 12 transfer complete */
DMA13_IRQn = 13, /**< DMA channel 13 transfer complete */
DMA14_IRQn = 14, /**< DMA channel 14 transfer complete */
DMA15_IRQn = 15, /**< DMA channel 15 transfer complete */
DMA_Error_IRQn = 16, /**< DMA channel 0 - 15 error */
MCM_IRQn = 17, /**< MCM normal interrupt */
FTFL_IRQn = 18, /**< FTFL command complete */
Read_Collision_IRQn = 19, /**< FTFL read collision */
LVD_LVW_IRQn = 20, /**< PMC controller low-voltage detect, low-voltage warning */
LLW_IRQn = 21, /**< Low leakage wakeup */
WDOG_EWM_IRQn = 22, /**< Single interrupt vector for WDOG and EWM */
RNG_IRQn = 23, /**< Randon number generator */
I2C0_IRQn = 24, /**< Inter-integrated circuit 0 */
I2C1_IRQn = 25, /**< Inter-integrated circuit 1 */
SPI0_IRQn = 26, /**< Serial peripheral Interface 0 */
SPI1_IRQn = 27, /**< Serial peripheral Interface 1 */
SPI2_IRQn = 28, /**< Serial peripheral Interface 1 */
CAN0_ORed_Message_buffer_IRQn = 29, /**< CAN0 ORed message buffers */
CAN0_Bus_Off_IRQn = 30, /**< CAN0 bus off */
CAN0_Error_IRQn = 31, /**< CAN0 error */
CAN0_Tx_Warning_IRQn = 32, /**< CAN0 Tx warning */
CAN0_Rx_Warning_IRQn = 33, /**< CAN0 Rx warning */
CAN0_Wake_Up_IRQn = 34, /**< CAN0 wake up */
I2S0_Tx_IRQn = 35, /**< Integrated interchip sound 0 transmit interrupt */
I2S0_Rx_IRQn = 36, /**< Integrated interchip sound 0 receive interrupt */
CAN1_ORed_Message_buffer_IRQn = 37, /**< CAN1 OR'd message buffers interrupt */
CAN1_Bus_Off_IRQn = 38, /**< CAN1 bus off interrupt */
CAN1_Error_IRQn = 39, /**< CAN1 error interrupt */
CAN1_Tx_Warning_IRQn = 40, /**< CAN1 Tx warning interrupt */
CAN1_Rx_Warning_IRQn = 41, /**< CAN1 Rx warning interrupt */
CAN1_Wake_Up_IRQn = 42, /**< CAN1 wake up interrupt */
Reserved59_IRQn = 43, /**< Reserved interrupt */
UART0_LON_IRQn = 44, /**< UART0 LON */
UART0_RX_TX_IRQn = 45, /**< UART0 receive/transmit interrupt */
UART0_ERR_IRQn = 46, /**< UART0 error interrupt */
UART1_RX_TX_IRQn = 47, /**< UART1 receive/transmit interrupt */
UART1_ERR_IRQn = 48, /**< UART1 error interrupt */
UART2_RX_TX_IRQn = 49, /**< UART2 receive/transmit interrupt */
UART2_ERR_IRQn = 50, /**< UART2 error interrupt */
UART3_RX_TX_IRQn = 51, /**< UART3 receive/transmit interrupt */
UART3_ERR_IRQn = 52, /**< UART3 error interrupt */
UART4_RX_TX_IRQn = 53, /**< UART4 receive/transmit interrupt */
UART4_ERR_IRQn = 54, /**< UART4 error interrupt */
UART5_RX_TX_IRQn = 55, /**< UART5 receive/transmit interrupt */
UART5_ERR_IRQn = 56, /**< UART5 error interrupt */
ADC0_IRQn = 57, /**< Analog-to-digital converter 0 */
ADC1_IRQn = 58, /**< Analog-to-digital converter 1 */
CMP0_IRQn = 59, /**< Comparator 0 */
CMP1_IRQn = 60, /**< Comparator 1 */
CMP2_IRQn = 61, /**< Comparator 2 */
FTM0_IRQn = 62, /**< FlexTimer module 0 fault, overflow and channels interrupt */
FTM1_IRQn = 63, /**< FlexTimer module 1 fault, overflow and channels interrupt */
FTM2_IRQn = 64, /**< FlexTimer module 2 fault, overflow and channels interrupt */
CMT_IRQn = 65, /**< Carrier modulator transmitter */
RTC_IRQn = 66, /**< Real time clock */
RTC_Seconds_IRQn = 67, /**< Real time clock seconds */
PIT0_IRQn = 68, /**< Periodic interrupt timer channel 0 */
PIT1_IRQn = 69, /**< Periodic interrupt timer channel 1 */
PIT2_IRQn = 70, /**< Periodic interrupt timer channel 2 */
PIT3_IRQn = 71, /**< Periodic interrupt timer channel 3 */
PDB0_IRQn = 72, /**< Programmable delay block */
USB0_IRQn = 73, /**< USB OTG interrupt */
USBDCD_IRQn = 74, /**< USB charger detect */
ENET_1588_Timer_IRQn = 75, /**< Ethernet MAC IEEE 1588 timer */
ENET_Transmit_IRQn = 76, /**< Ethernet MAC transmit */
ENET_Receive_IRQn = 77, /**< Ethernet MAC receive */
ENET_Error_IRQn = 78, /**< Ethernet MAC error and miscelaneous */
Reserved95_IRQn = 79, /**< Reserved interrupt */
SDHC_IRQn = 80, /**< Secured digital host controller */
DAC0_IRQn = 81, /**< Digital-to-analog converter 0 */
DAC1_IRQn = 82, /**< Digital-to-analog converter 1 */
TSI0_IRQn = 83, /**< TSI0 Interrupt */
MCG_IRQn = 84, /**< Multipurpose clock generator */
LPTMR0_IRQn = 85, /**< Low power timer interrupt */
Reserved102_IRQn = 86, /**< Reserved interrupt */
PORTA_IRQn = 87, /**< Port A interrupt */
PORTB_IRQn = 88, /**< Port B interrupt */
PORTC_IRQn = 89, /**< Port C interrupt */
PORTD_IRQn = 90, /**< Port D interrupt */
PORTE_IRQn = 91, /**< Port E interrupt */
Reserved108_IRQn = 92, /**< Reserved interrupt */
Reserved109_IRQn = 93, /**< Reserved interrupt */
SWI_IRQn = 94, /**< Software interrupt */
Reserved111_IRQn = 95, /**< Reserved interrupt */
Reserved112_IRQn = 96, /**< Reserved interrupt */
Reserved113_IRQn = 97, /**< Reserved interrupt */
Reserved114_IRQn = 98, /**< Reserved interrupt */
Reserved115_IRQn = 99, /**< Reserved interrupt */
Reserved116_IRQn = 100, /**< Reserved interrupt */
Reserved117_IRQn = 101, /**< Reserved interrupt */
Reserved118_IRQn = 102, /**< Reserved interrupt */
Reserved119_IRQn = 103 /**< Reserved interrupt */
} IRQn_Type;
/*!
* @}
*/ /* end of group Interrupt_vector_numbers */
/* ----------------------------------------------------------------------------
-- Cortex M4 Core Configuration
---------------------------------------------------------------------------- */
/*!
* @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
* @{
*/
#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
#define __FPU_PRESENT 0 /**< Defines if an FPU is present or not */
#include "core_cm4.h" /* Core Peripheral Access Layer */
/*!
* @}
*/ /* end of group Cortex_Core_Configuration */
/* ----------------------------------------------------------------------------
-- Device Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup Peripheral_access_layer Device Peripheral Access Layer
* @{
*/
/*
** Start of section using anonymous unions
*/
#if defined(__ARMCC_VERSION)
#pragma push
#pragma anon_unions
#elif defined(__CWCC__)
#pragma push
#pragma cpp_extensions on
#elif defined(__GNUC__)
/* anonymous unions are enabled by default */
#elif defined(__IAR_SYSTEMS_ICC__)
#pragma language=extended
#else
#error Not supported compiler type
#endif
/* ----------------------------------------------------------------------------
-- ADC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
* @{
*/
/** ADC - Register Layout Typedef */
typedef struct {
__IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
__IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
__IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
__I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
__IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
__IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
__IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
__IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
__IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
__IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
__IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
__IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
__IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
__IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
__IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
__IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
__IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
__IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
__IO uint32_t PGA; /**< ADC PGA Register, offset: 0x50 */
__IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
__IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
__IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
__IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
__IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
__IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
__IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
} ADC_Type, *ADC_MemMapPtr;
/* ----------------------------------------------------------------------------
-- ADC - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
* @{
*/
/* ADC - Register accessors */
#define ADC_SC1_REG(base,index) ((base)->SC1[index])
#define ADC_CFG1_REG(base) ((base)->CFG1)
#define ADC_CFG2_REG(base) ((base)->CFG2)
#define ADC_R_REG(base,index) ((base)->R[index])
#define ADC_CV1_REG(base) ((base)->CV1)
#define ADC_CV2_REG(base) ((base)->CV2)
#define ADC_SC2_REG(base) ((base)->SC2)
#define ADC_SC3_REG(base) ((base)->SC3)
#define ADC_OFS_REG(base) ((base)->OFS)
#define ADC_PG_REG(base) ((base)->PG)
#define ADC_MG_REG(base) ((base)->MG)
#define ADC_CLPD_REG(base) ((base)->CLPD)
#define ADC_CLPS_REG(base) ((base)->CLPS)
#define ADC_CLP4_REG(base) ((base)->CLP4)
#define ADC_CLP3_REG(base) ((base)->CLP3)
#define ADC_CLP2_REG(base) ((base)->CLP2)
#define ADC_CLP1_REG(base) ((base)->CLP1)
#define ADC_CLP0_REG(base) ((base)->CLP0)
#define ADC_PGA_REG(base) ((base)->PGA)
#define ADC_CLMD_REG(base) ((base)->CLMD)
#define ADC_CLMS_REG(base) ((base)->CLMS)
#define ADC_CLM4_REG(base) ((base)->CLM4)
#define ADC_CLM3_REG(base) ((base)->CLM3)
#define ADC_CLM2_REG(base) ((base)->CLM2)
#define ADC_CLM1_REG(base) ((base)->CLM1)
#define ADC_CLM0_REG(base) ((base)->CLM0)
/*!
* @}
*/ /* end of group ADC_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- ADC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup ADC_Register_Masks ADC Register Masks
* @{
*/
/* SC1 Bit Fields */
#define ADC_SC1_ADCH_MASK 0x1Fu
#define ADC_SC1_ADCH_SHIFT 0
#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
#define ADC_SC1_DIFF_MASK 0x20u
#define ADC_SC1_DIFF_SHIFT 5
#define ADC_SC1_AIEN_MASK 0x40u
#define ADC_SC1_AIEN_SHIFT 6
#define ADC_SC1_COCO_MASK 0x80u
#define ADC_SC1_COCO_SHIFT 7
/* CFG1 Bit Fields */
#define ADC_CFG1_ADICLK_MASK 0x3u
#define ADC_CFG1_ADICLK_SHIFT 0
#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
#define ADC_CFG1_MODE_MASK 0xCu
#define ADC_CFG1_MODE_SHIFT 2
#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
#define ADC_CFG1_ADLSMP_MASK 0x10u
#define ADC_CFG1_ADLSMP_SHIFT 4
#define ADC_CFG1_ADIV_MASK 0x60u
#define ADC_CFG1_ADIV_SHIFT 5
#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
#define ADC_CFG1_ADLPC_MASK 0x80u
#define ADC_CFG1_ADLPC_SHIFT 7
/* CFG2 Bit Fields */
#define ADC_CFG2_ADLSTS_MASK 0x3u
#define ADC_CFG2_ADLSTS_SHIFT 0
#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
#define ADC_CFG2_ADHSC_MASK 0x4u
#define ADC_CFG2_ADHSC_SHIFT 2
#define ADC_CFG2_ADACKEN_MASK 0x8u
#define ADC_CFG2_ADACKEN_SHIFT 3
#define ADC_CFG2_MUXSEL_MASK 0x10u
#define ADC_CFG2_MUXSEL_SHIFT 4
/* R Bit Fields */
#define ADC_R_D_MASK 0xFFFFu
#define ADC_R_D_SHIFT 0
#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
/* CV1 Bit Fields */
#define ADC_CV1_CV_MASK 0xFFFFu
#define ADC_CV1_CV_SHIFT 0
#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
/* CV2 Bit Fields */
#define ADC_CV2_CV_MASK 0xFFFFu
#define ADC_CV2_CV_SHIFT 0
#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
/* SC2 Bit Fields */
#define ADC_SC2_REFSEL_MASK 0x3u
#define ADC_SC2_REFSEL_SHIFT 0
#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
#define ADC_SC2_DMAEN_MASK 0x4u
#define ADC_SC2_DMAEN_SHIFT 2
#define ADC_SC2_ACREN_MASK 0x8u
#define ADC_SC2_ACREN_SHIFT 3
#define ADC_SC2_ACFGT_MASK 0x10u
#define ADC_SC2_ACFGT_SHIFT 4
#define ADC_SC2_ACFE_MASK 0x20u
#define ADC_SC2_ACFE_SHIFT 5
#define ADC_SC2_ADTRG_MASK 0x40u
#define ADC_SC2_ADTRG_SHIFT 6
#define ADC_SC2_ADACT_MASK 0x80u
#define ADC_SC2_ADACT_SHIFT 7
/* SC3 Bit Fields */
#define ADC_SC3_AVGS_MASK 0x3u
#define ADC_SC3_AVGS_SHIFT 0
#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
#define ADC_SC3_AVGE_MASK 0x4u
#define ADC_SC3_AVGE_SHIFT 2
#define ADC_SC3_ADCO_MASK 0x8u
#define ADC_SC3_ADCO_SHIFT 3
#define ADC_SC3_CALF_MASK 0x40u
#define ADC_SC3_CALF_SHIFT 6
#define ADC_SC3_CAL_MASK 0x80u
#define ADC_SC3_CAL_SHIFT 7
/* OFS Bit Fields */
#define ADC_OFS_OFS_MASK 0xFFFFu
#define ADC_OFS_OFS_SHIFT 0
#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
/* PG Bit Fields */
#define ADC_PG_PG_MASK 0xFFFFu
#define ADC_PG_PG_SHIFT 0
#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
/* MG Bit Fields */
#define ADC_MG_MG_MASK 0xFFFFu
#define ADC_MG_MG_SHIFT 0
#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
/* CLPD Bit Fields */
#define ADC_CLPD_CLPD_MASK 0x3Fu
#define ADC_CLPD_CLPD_SHIFT 0
#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
/* CLPS Bit Fields */
#define ADC_CLPS_CLPS_MASK 0x3Fu
#define ADC_CLPS_CLPS_SHIFT 0
#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
/* CLP4 Bit Fields */
#define ADC_CLP4_CLP4_MASK 0x3FFu
#define ADC_CLP4_CLP4_SHIFT 0
#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
/* CLP3 Bit Fields */
#define ADC_CLP3_CLP3_MASK 0x1FFu
#define ADC_CLP3_CLP3_SHIFT 0
#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
/* CLP2 Bit Fields */
#define ADC_CLP2_CLP2_MASK 0xFFu
#define ADC_CLP2_CLP2_SHIFT 0
#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
/* CLP1 Bit Fields */
#define ADC_CLP1_CLP1_MASK 0x7Fu
#define ADC_CLP1_CLP1_SHIFT 0
#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
/* CLP0 Bit Fields */
#define ADC_CLP0_CLP0_MASK 0x3Fu
#define ADC_CLP0_CLP0_SHIFT 0
#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
/* PGA Bit Fields */
#define ADC_PGA_PGAG_MASK 0xF0000u
#define ADC_PGA_PGAG_SHIFT 16
#define ADC_PGA_PGAG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PGA_PGAG_SHIFT))&ADC_PGA_PGAG_MASK)
#define ADC_PGA_PGALPb_MASK 0x100000u
#define ADC_PGA_PGALPb_SHIFT 20
#define ADC_PGA_PGAEN_MASK 0x800000u
#define ADC_PGA_PGAEN_SHIFT 23
/* CLMD Bit Fields */
#define ADC_CLMD_CLMD_MASK 0x3Fu
#define ADC_CLMD_CLMD_SHIFT 0
#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
/* CLMS Bit Fields */
#define ADC_CLMS_CLMS_MASK 0x3Fu
#define ADC_CLMS_CLMS_SHIFT 0
#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
/* CLM4 Bit Fields */
#define ADC_CLM4_CLM4_MASK 0x3FFu
#define ADC_CLM4_CLM4_SHIFT 0
#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
/* CLM3 Bit Fields */
#define ADC_CLM3_CLM3_MASK 0x1FFu
#define ADC_CLM3_CLM3_SHIFT 0
#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
/* CLM2 Bit Fields */
#define ADC_CLM2_CLM2_MASK 0xFFu
#define ADC_CLM2_CLM2_SHIFT 0
#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
/* CLM1 Bit Fields */
#define ADC_CLM1_CLM1_MASK 0x7Fu
#define ADC_CLM1_CLM1_SHIFT 0
#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
/* CLM0 Bit Fields */
#define ADC_CLM0_CLM0_MASK 0x3Fu
#define ADC_CLM0_CLM0_SHIFT 0
#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
/*!
* @}
*/ /* end of group ADC_Register_Masks */
/* ADC - Peripheral instance base addresses */
/** Peripheral ADC0 base address */
#define ADC0_BASE (0x4003B000u)
/** Peripheral ADC0 base pointer */
#define ADC0 ((ADC_Type *)ADC0_BASE)
#define ADC0_BASE_PTR (ADC0)
/** Peripheral ADC1 base address */
#define ADC1_BASE (0x400BB000u)
/** Peripheral ADC1 base pointer */
#define ADC1 ((ADC_Type *)ADC1_BASE)
#define ADC1_BASE_PTR (ADC1)
/** Array initializer of ADC peripheral base addresses */
#define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE }
/** Array initializer of ADC peripheral base pointers */
#define ADC_BASE_PTRS { ADC0, ADC1 }
/** Interrupt vectors for the ADC peripheral type */
#define ADC_IRQS { ADC0_IRQn, ADC1_IRQn }
/* ----------------------------------------------------------------------------
-- ADC - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
* @{
*/
/* ADC - Register instance definitions */
/* ADC0 */
#define ADC0_SC1A ADC_SC1_REG(ADC0,0)
#define ADC0_SC1B ADC_SC1_REG(ADC0,1)
#define ADC0_CFG1 ADC_CFG1_REG(ADC0)
#define ADC0_CFG2 ADC_CFG2_REG(ADC0)
#define ADC0_RA ADC_R_REG(ADC0,0)
#define ADC0_RB ADC_R_REG(ADC0,1)
#define ADC0_CV1 ADC_CV1_REG(ADC0)
#define ADC0_CV2 ADC_CV2_REG(ADC0)
#define ADC0_SC2 ADC_SC2_REG(ADC0)
#define ADC0_SC3 ADC_SC3_REG(ADC0)
#define ADC0_OFS ADC_OFS_REG(ADC0)
#define ADC0_PG ADC_PG_REG(ADC0)
#define ADC0_MG ADC_MG_REG(ADC0)
#define ADC0_CLPD ADC_CLPD_REG(ADC0)
#define ADC0_CLPS ADC_CLPS_REG(ADC0)
#define ADC0_CLP4 ADC_CLP4_REG(ADC0)
#define ADC0_CLP3 ADC_CLP3_REG(ADC0)
#define ADC0_CLP2 ADC_CLP2_REG(ADC0)
#define ADC0_CLP1 ADC_CLP1_REG(ADC0)
#define ADC0_CLP0 ADC_CLP0_REG(ADC0)
#define ADC0_PGA ADC_PGA_REG(ADC0)
#define ADC0_CLMD ADC_CLMD_REG(ADC0)
#define ADC0_CLMS ADC_CLMS_REG(ADC0)
#define ADC0_CLM4 ADC_CLM4_REG(ADC0)
#define ADC0_CLM3 ADC_CLM3_REG(ADC0)
#define ADC0_CLM2 ADC_CLM2_REG(ADC0)
#define ADC0_CLM1 ADC_CLM1_REG(ADC0)
#define ADC0_CLM0 ADC_CLM0_REG(ADC0)
/* ADC1 */
#define ADC1_SC1A ADC_SC1_REG(ADC1,0)
#define ADC1_SC1B ADC_SC1_REG(ADC1,1)
#define ADC1_CFG1 ADC_CFG1_REG(ADC1)
#define ADC1_CFG2 ADC_CFG2_REG(ADC1)
#define ADC1_RA ADC_R_REG(ADC1,0)
#define ADC1_RB ADC_R_REG(ADC1,1)
#define ADC1_CV1 ADC_CV1_REG(ADC1)
#define ADC1_CV2 ADC_CV2_REG(ADC1)
#define ADC1_SC2 ADC_SC2_REG(ADC1)
#define ADC1_SC3 ADC_SC3_REG(ADC1)
#define ADC1_OFS ADC_OFS_REG(ADC1)
#define ADC1_PG ADC_PG_REG(ADC1)
#define ADC1_MG ADC_MG_REG(ADC1)
#define ADC1_CLPD ADC_CLPD_REG(ADC1)
#define ADC1_CLPS ADC_CLPS_REG(ADC1)
#define ADC1_CLP4 ADC_CLP4_REG(ADC1)
#define ADC1_CLP3 ADC_CLP3_REG(ADC1)
#define ADC1_CLP2 ADC_CLP2_REG(ADC1)
#define ADC1_CLP1 ADC_CLP1_REG(ADC1)
#define ADC1_CLP0 ADC_CLP0_REG(ADC1)
#define ADC1_PGA ADC_PGA_REG(ADC1)
#define ADC1_CLMD ADC_CLMD_REG(ADC1)
#define ADC1_CLMS ADC_CLMS_REG(ADC1)
#define ADC1_CLM4 ADC_CLM4_REG(ADC1)
#define ADC1_CLM3 ADC_CLM3_REG(ADC1)
#define ADC1_CLM2 ADC_CLM2_REG(ADC1)
#define ADC1_CLM1 ADC_CLM1_REG(ADC1)
#define ADC1_CLM0 ADC_CLM0_REG(ADC1)
/* ADC - Register array accessors */
#define ADC0_SC1(index) ADC_SC1_REG(ADC0,index)
#define ADC1_SC1(index) ADC_SC1_REG(ADC1,index)
#define ADC0_R(index) ADC_R_REG(ADC0,index)
#define ADC1_R(index) ADC_R_REG(ADC1,index)
/*!
* @}
*/ /* end of group ADC_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group ADC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- AIPS Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup AIPS_Peripheral_Access_Layer AIPS Peripheral Access Layer
* @{
*/
/** AIPS - Register Layout Typedef */
typedef struct {
__IO uint32_t MPRA; /**< Master Privilege Register A, offset: 0x0 */
uint8_t RESERVED_0[28];
__IO uint32_t PACRA; /**< Peripheral Access Control Register, offset: 0x20 */
__IO uint32_t PACRB; /**< Peripheral Access Control Register, offset: 0x24 */
__IO uint32_t PACRC; /**< Peripheral Access Control Register, offset: 0x28 */
__IO uint32_t PACRD; /**< Peripheral Access Control Register, offset: 0x2C */
uint8_t RESERVED_1[16];
__IO uint32_t PACRE; /**< Peripheral Access Control Register, offset: 0x40 */
__IO uint32_t PACRF; /**< Peripheral Access Control Register, offset: 0x44 */
__IO uint32_t PACRG; /**< Peripheral Access Control Register, offset: 0x48 */
__IO uint32_t PACRH; /**< Peripheral Access Control Register, offset: 0x4C */
__IO uint32_t PACRI; /**< Peripheral Access Control Register, offset: 0x50 */
__IO uint32_t PACRJ; /**< Peripheral Access Control Register, offset: 0x54 */
__IO uint32_t PACRK; /**< Peripheral Access Control Register, offset: 0x58 */
__IO uint32_t PACRL; /**< Peripheral Access Control Register, offset: 0x5C */
__IO uint32_t PACRM; /**< Peripheral Access Control Register, offset: 0x60 */
__IO uint32_t PACRN; /**< Peripheral Access Control Register, offset: 0x64 */
__IO uint32_t PACRO; /**< Peripheral Access Control Register, offset: 0x68 */
__IO uint32_t PACRP; /**< Peripheral Access Control Register, offset: 0x6C */
} AIPS_Type, *AIPS_MemMapPtr;
/* ----------------------------------------------------------------------------
-- AIPS - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup AIPS_Register_Accessor_Macros AIPS - Register accessor macros
* @{
*/
/* AIPS - Register accessors */
#define AIPS_MPRA_REG(base) ((base)->MPRA)
#define AIPS_PACRA_REG(base) ((base)->PACRA)
#define AIPS_PACRB_REG(base) ((base)->PACRB)
#define AIPS_PACRC_REG(base) ((base)->PACRC)
#define AIPS_PACRD_REG(base) ((base)->PACRD)
#define AIPS_PACRE_REG(base) ((base)->PACRE)
#define AIPS_PACRF_REG(base) ((base)->PACRF)
#define AIPS_PACRG_REG(base) ((base)->PACRG)
#define AIPS_PACRH_REG(base) ((base)->PACRH)
#define AIPS_PACRI_REG(base) ((base)->PACRI)
#define AIPS_PACRJ_REG(base) ((base)->PACRJ)
#define AIPS_PACRK_REG(base) ((base)->PACRK)
#define AIPS_PACRL_REG(base) ((base)->PACRL)
#define AIPS_PACRM_REG(base) ((base)->PACRM)
#define AIPS_PACRN_REG(base) ((base)->PACRN)
#define AIPS_PACRO_REG(base) ((base)->PACRO)
#define AIPS_PACRP_REG(base) ((base)->PACRP)
/*!
* @}
*/ /* end of group AIPS_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- AIPS Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup AIPS_Register_Masks AIPS Register Masks
* @{
*/
/* MPRA Bit Fields */
#define AIPS_MPRA_MPL5_MASK 0x100u
#define AIPS_MPRA_MPL5_SHIFT 8
#define AIPS_MPRA_MTW5_MASK 0x200u
#define AIPS_MPRA_MTW5_SHIFT 9
#define AIPS_MPRA_MTR5_MASK 0x400u
#define AIPS_MPRA_MTR5_SHIFT 10
#define AIPS_MPRA_MPL4_MASK 0x1000u
#define AIPS_MPRA_MPL4_SHIFT 12
#define AIPS_MPRA_MTW4_MASK 0x2000u
#define AIPS_MPRA_MTW4_SHIFT 13
#define AIPS_MPRA_MTR4_MASK 0x4000u
#define AIPS_MPRA_MTR4_SHIFT 14
#define AIPS_MPRA_MPL3_MASK 0x10000u
#define AIPS_MPRA_MPL3_SHIFT 16
#define AIPS_MPRA_MTW3_MASK 0x20000u
#define AIPS_MPRA_MTW3_SHIFT 17
#define AIPS_MPRA_MTR3_MASK 0x40000u
#define AIPS_MPRA_MTR3_SHIFT 18
#define AIPS_MPRA_MPL2_MASK 0x100000u
#define AIPS_MPRA_MPL2_SHIFT 20
#define AIPS_MPRA_MTW2_MASK 0x200000u
#define AIPS_MPRA_MTW2_SHIFT 21
#define AIPS_MPRA_MTR2_MASK 0x400000u
#define AIPS_MPRA_MTR2_SHIFT 22
#define AIPS_MPRA_MPL1_MASK 0x1000000u
#define AIPS_MPRA_MPL1_SHIFT 24
#define AIPS_MPRA_MTW1_MASK 0x2000000u
#define AIPS_MPRA_MTW1_SHIFT 25
#define AIPS_MPRA_MTR1_MASK 0x4000000u
#define AIPS_MPRA_MTR1_SHIFT 26
#define AIPS_MPRA_MPL0_MASK 0x10000000u
#define AIPS_MPRA_MPL0_SHIFT 28
#define AIPS_MPRA_MTW0_MASK 0x20000000u
#define AIPS_MPRA_MTW0_SHIFT 29
#define AIPS_MPRA_MTR0_MASK 0x40000000u
#define AIPS_MPRA_MTR0_SHIFT 30
/* PACRA Bit Fields */
#define AIPS_PACRA_TP7_MASK 0x1u
#define AIPS_PACRA_TP7_SHIFT 0
#define AIPS_PACRA_WP7_MASK 0x2u
#define AIPS_PACRA_WP7_SHIFT 1
#define AIPS_PACRA_SP7_MASK 0x4u
#define AIPS_PACRA_SP7_SHIFT 2
#define AIPS_PACRA_TP6_MASK 0x10u
#define AIPS_PACRA_TP6_SHIFT 4
#define AIPS_PACRA_WP6_MASK 0x20u
#define AIPS_PACRA_WP6_SHIFT 5
#define AIPS_PACRA_SP6_MASK 0x40u
#define AIPS_PACRA_SP6_SHIFT 6
#define AIPS_PACRA_TP5_MASK 0x100u
#define AIPS_PACRA_TP5_SHIFT 8
#define AIPS_PACRA_WP5_MASK 0x200u
#define AIPS_PACRA_WP5_SHIFT 9
#define AIPS_PACRA_SP5_MASK 0x400u
#define AIPS_PACRA_SP5_SHIFT 10
#define AIPS_PACRA_TP4_MASK 0x1000u
#define AIPS_PACRA_TP4_SHIFT 12
#define AIPS_PACRA_WP4_MASK 0x2000u
#define AIPS_PACRA_WP4_SHIFT 13
#define AIPS_PACRA_SP4_MASK 0x4000u
#define AIPS_PACRA_SP4_SHIFT 14
#define AIPS_PACRA_TP3_MASK 0x10000u
#define AIPS_PACRA_TP3_SHIFT 16
#define AIPS_PACRA_WP3_MASK 0x20000u
#define AIPS_PACRA_WP3_SHIFT 17
#define AIPS_PACRA_SP3_MASK 0x40000u
#define AIPS_PACRA_SP3_SHIFT 18
#define AIPS_PACRA_TP2_MASK 0x100000u
#define AIPS_PACRA_TP2_SHIFT 20
#define AIPS_PACRA_WP2_MASK 0x200000u
#define AIPS_PACRA_WP2_SHIFT 21
#define AIPS_PACRA_SP2_MASK 0x400000u
#define AIPS_PACRA_SP2_SHIFT 22
#define AIPS_PACRA_TP1_MASK 0x1000000u
#define AIPS_PACRA_TP1_SHIFT 24
#define AIPS_PACRA_WP1_MASK 0x2000000u
#define AIPS_PACRA_WP1_SHIFT 25
#define AIPS_PACRA_SP1_MASK 0x4000000u
#define AIPS_PACRA_SP1_SHIFT 26
#define AIPS_PACRA_TP0_MASK 0x10000000u
#define AIPS_PACRA_TP0_SHIFT 28
#define AIPS_PACRA_WP0_MASK 0x20000000u
#define AIPS_PACRA_WP0_SHIFT 29
#define AIPS_PACRA_SP0_MASK 0x40000000u
#define AIPS_PACRA_SP0_SHIFT 30
/* PACRB Bit Fields */
#define AIPS_PACRB_TP7_MASK 0x1u
#define AIPS_PACRB_TP7_SHIFT 0
#define AIPS_PACRB_WP7_MASK 0x2u
#define AIPS_PACRB_WP7_SHIFT 1
#define AIPS_PACRB_SP7_MASK 0x4u
#define AIPS_PACRB_SP7_SHIFT 2
#define AIPS_PACRB_TP6_MASK 0x10u
#define AIPS_PACRB_TP6_SHIFT 4
#define AIPS_PACRB_WP6_MASK 0x20u
#define AIPS_PACRB_WP6_SHIFT 5
#define AIPS_PACRB_SP6_MASK 0x40u
#define AIPS_PACRB_SP6_SHIFT 6
#define AIPS_PACRB_TP5_MASK 0x100u
#define AIPS_PACRB_TP5_SHIFT 8
#define AIPS_PACRB_WP5_MASK 0x200u
#define AIPS_PACRB_WP5_SHIFT 9
#define AIPS_PACRB_SP5_MASK 0x400u
#define AIPS_PACRB_SP5_SHIFT 10
#define AIPS_PACRB_TP4_MASK 0x1000u
#define AIPS_PACRB_TP4_SHIFT 12
#define AIPS_PACRB_WP4_MASK 0x2000u
#define AIPS_PACRB_WP4_SHIFT 13
#define AIPS_PACRB_SP4_MASK 0x4000u
#define AIPS_PACRB_SP4_SHIFT 14
#define AIPS_PACRB_TP3_MASK 0x10000u
#define AIPS_PACRB_TP3_SHIFT 16
#define AIPS_PACRB_WP3_MASK 0x20000u
#define AIPS_PACRB_WP3_SHIFT 17
#define AIPS_PACRB_SP3_MASK 0x40000u
#define AIPS_PACRB_SP3_SHIFT 18
#define AIPS_PACRB_TP2_MASK 0x100000u
#define AIPS_PACRB_TP2_SHIFT 20
#define AIPS_PACRB_WP2_MASK 0x200000u
#define AIPS_PACRB_WP2_SHIFT 21
#define AIPS_PACRB_SP2_MASK 0x400000u
#define AIPS_PACRB_SP2_SHIFT 22
#define AIPS_PACRB_TP1_MASK 0x1000000u
#define AIPS_PACRB_TP1_SHIFT 24
#define AIPS_PACRB_WP1_MASK 0x2000000u
#define AIPS_PACRB_WP1_SHIFT 25
#define AIPS_PACRB_SP1_MASK 0x4000000u
#define AIPS_PACRB_SP1_SHIFT 26
#define AIPS_PACRB_TP0_MASK 0x10000000u
#define AIPS_PACRB_TP0_SHIFT 28
#define AIPS_PACRB_WP0_MASK 0x20000000u
#define AIPS_PACRB_WP0_SHIFT 29
#define AIPS_PACRB_SP0_MASK 0x40000000u
#define AIPS_PACRB_SP0_SHIFT 30
/* PACRC Bit Fields */
#define AIPS_PACRC_TP7_MASK 0x1u
#define AIPS_PACRC_TP7_SHIFT 0
#define AIPS_PACRC_WP7_MASK 0x2u
#define AIPS_PACRC_WP7_SHIFT 1
#define AIPS_PACRC_SP7_MASK 0x4u
#define AIPS_PACRC_SP7_SHIFT 2
#define AIPS_PACRC_TP6_MASK 0x10u
#define AIPS_PACRC_TP6_SHIFT 4
#define AIPS_PACRC_WP6_MASK 0x20u
#define AIPS_PACRC_WP6_SHIFT 5
#define AIPS_PACRC_SP6_MASK 0x40u
#define AIPS_PACRC_SP6_SHIFT 6
#define AIPS_PACRC_TP5_MASK 0x100u
#define AIPS_PACRC_TP5_SHIFT 8
#define AIPS_PACRC_WP5_MASK 0x200u
#define AIPS_PACRC_WP5_SHIFT 9
#define AIPS_PACRC_SP5_MASK 0x400u
#define AIPS_PACRC_SP5_SHIFT 10
#define AIPS_PACRC_TP4_MASK 0x1000u
#define AIPS_PACRC_TP4_SHIFT 12
#define AIPS_PACRC_WP4_MASK 0x2000u
#define AIPS_PACRC_WP4_SHIFT 13
#define AIPS_PACRC_SP4_MASK 0x4000u
#define AIPS_PACRC_SP4_SHIFT 14
#define AIPS_PACRC_TP3_MASK 0x10000u
#define AIPS_PACRC_TP3_SHIFT 16
#define AIPS_PACRC_WP3_MASK 0x20000u
#define AIPS_PACRC_WP3_SHIFT 17
#define AIPS_PACRC_SP3_MASK 0x40000u
#define AIPS_PACRC_SP3_SHIFT 18
#define AIPS_PACRC_TP2_MASK 0x100000u
#define AIPS_PACRC_TP2_SHIFT 20
#define AIPS_PACRC_WP2_MASK 0x200000u
#define AIPS_PACRC_WP2_SHIFT 21
#define AIPS_PACRC_SP2_MASK 0x400000u
#define AIPS_PACRC_SP2_SHIFT 22
#define AIPS_PACRC_TP1_MASK 0x1000000u
#define AIPS_PACRC_TP1_SHIFT 24
#define AIPS_PACRC_WP1_MASK 0x2000000u
#define AIPS_PACRC_WP1_SHIFT 25
#define AIPS_PACRC_SP1_MASK 0x4000000u
#define AIPS_PACRC_SP1_SHIFT 26
#define AIPS_PACRC_TP0_MASK 0x10000000u
#define AIPS_PACRC_TP0_SHIFT 28
#define AIPS_PACRC_WP0_MASK 0x20000000u
#define AIPS_PACRC_WP0_SHIFT 29
#define AIPS_PACRC_SP0_MASK 0x40000000u
#define AIPS_PACRC_SP0_SHIFT 30
/* PACRD Bit Fields */
#define AIPS_PACRD_TP7_MASK 0x1u
#define AIPS_PACRD_TP7_SHIFT 0
#define AIPS_PACRD_WP7_MASK 0x2u
#define AIPS_PACRD_WP7_SHIFT 1
#define AIPS_PACRD_SP7_MASK 0x4u
#define AIPS_PACRD_SP7_SHIFT 2
#define AIPS_PACRD_TP6_MASK 0x10u
#define AIPS_PACRD_TP6_SHIFT 4
#define AIPS_PACRD_WP6_MASK 0x20u
#define AIPS_PACRD_WP6_SHIFT 5
#define AIPS_PACRD_SP6_MASK 0x40u
#define AIPS_PACRD_SP6_SHIFT 6
#define AIPS_PACRD_TP5_MASK 0x100u
#define AIPS_PACRD_TP5_SHIFT 8
#define AIPS_PACRD_WP5_MASK 0x200u
#define AIPS_PACRD_WP5_SHIFT 9
#define AIPS_PACRD_SP5_MASK 0x400u
#define AIPS_PACRD_SP5_SHIFT 10
#define AIPS_PACRD_TP4_MASK 0x1000u
#define AIPS_PACRD_TP4_SHIFT 12
#define AIPS_PACRD_WP4_MASK 0x2000u
#define AIPS_PACRD_WP4_SHIFT 13
#define AIPS_PACRD_SP4_MASK 0x4000u
#define AIPS_PACRD_SP4_SHIFT 14
#define AIPS_PACRD_TP3_MASK 0x10000u
#define AIPS_PACRD_TP3_SHIFT 16
#define AIPS_PACRD_WP3_MASK 0x20000u
#define AIPS_PACRD_WP3_SHIFT 17
#define AIPS_PACRD_SP3_MASK 0x40000u
#define AIPS_PACRD_SP3_SHIFT 18
#define AIPS_PACRD_TP2_MASK 0x100000u
#define AIPS_PACRD_TP2_SHIFT 20
#define AIPS_PACRD_WP2_MASK 0x200000u
#define AIPS_PACRD_WP2_SHIFT 21
#define AIPS_PACRD_SP2_MASK 0x400000u
#define AIPS_PACRD_SP2_SHIFT 22
#define AIPS_PACRD_TP1_MASK 0x1000000u
#define AIPS_PACRD_TP1_SHIFT 24
#define AIPS_PACRD_WP1_MASK 0x2000000u
#define AIPS_PACRD_WP1_SHIFT 25
#define AIPS_PACRD_SP1_MASK 0x4000000u
#define AIPS_PACRD_SP1_SHIFT 26
#define AIPS_PACRD_TP0_MASK 0x10000000u
#define AIPS_PACRD_TP0_SHIFT 28
#define AIPS_PACRD_WP0_MASK 0x20000000u
#define AIPS_PACRD_WP0_SHIFT 29
#define AIPS_PACRD_SP0_MASK 0x40000000u
#define AIPS_PACRD_SP0_SHIFT 30
/* PACRE Bit Fields */
#define AIPS_PACRE_TP7_MASK 0x1u
#define AIPS_PACRE_TP7_SHIFT 0
#define AIPS_PACRE_WP7_MASK 0x2u
#define AIPS_PACRE_WP7_SHIFT 1
#define AIPS_PACRE_SP7_MASK 0x4u
#define AIPS_PACRE_SP7_SHIFT 2
#define AIPS_PACRE_TP6_MASK 0x10u
#define AIPS_PACRE_TP6_SHIFT 4
#define AIPS_PACRE_WP6_MASK 0x20u
#define AIPS_PACRE_WP6_SHIFT 5
#define AIPS_PACRE_SP6_MASK 0x40u
#define AIPS_PACRE_SP6_SHIFT 6
#define AIPS_PACRE_TP5_MASK 0x100u
#define AIPS_PACRE_TP5_SHIFT 8
#define AIPS_PACRE_WP5_MASK 0x200u
#define AIPS_PACRE_WP5_SHIFT 9
#define AIPS_PACRE_SP5_MASK 0x400u
#define AIPS_PACRE_SP5_SHIFT 10
#define AIPS_PACRE_TP4_MASK 0x1000u
#define AIPS_PACRE_TP4_SHIFT 12
#define AIPS_PACRE_WP4_MASK 0x2000u
#define AIPS_PACRE_WP4_SHIFT 13
#define AIPS_PACRE_SP4_MASK 0x4000u
#define AIPS_PACRE_SP4_SHIFT 14
#define AIPS_PACRE_TP3_MASK 0x10000u
#define AIPS_PACRE_TP3_SHIFT 16
#define AIPS_PACRE_WP3_MASK 0x20000u
#define AIPS_PACRE_WP3_SHIFT 17
#define AIPS_PACRE_SP3_MASK 0x40000u
#define AIPS_PACRE_SP3_SHIFT 18
#define AIPS_PACRE_TP2_MASK 0x100000u
#define AIPS_PACRE_TP2_SHIFT 20
#define AIPS_PACRE_WP2_MASK 0x200000u
#define AIPS_PACRE_WP2_SHIFT 21
#define AIPS_PACRE_SP2_MASK 0x400000u
#define AIPS_PACRE_SP2_SHIFT 22
#define AIPS_PACRE_TP1_MASK 0x1000000u
#define AIPS_PACRE_TP1_SHIFT 24
#define AIPS_PACRE_WP1_MASK 0x2000000u
#define AIPS_PACRE_WP1_SHIFT 25
#define AIPS_PACRE_SP1_MASK 0x4000000u
#define AIPS_PACRE_SP1_SHIFT 26
#define AIPS_PACRE_TP0_MASK 0x10000000u
#define AIPS_PACRE_TP0_SHIFT 28
#define AIPS_PACRE_WP0_MASK 0x20000000u
#define AIPS_PACRE_WP0_SHIFT 29
#define AIPS_PACRE_SP0_MASK 0x40000000u
#define AIPS_PACRE_SP0_SHIFT 30
/* PACRF Bit Fields */
#define AIPS_PACRF_TP7_MASK 0x1u
#define AIPS_PACRF_TP7_SHIFT 0
#define AIPS_PACRF_WP7_MASK 0x2u
#define AIPS_PACRF_WP7_SHIFT 1
#define AIPS_PACRF_SP7_MASK 0x4u
#define AIPS_PACRF_SP7_SHIFT 2
#define AIPS_PACRF_TP6_MASK 0x10u
#define AIPS_PACRF_TP6_SHIFT 4
#define AIPS_PACRF_WP6_MASK 0x20u
#define AIPS_PACRF_WP6_SHIFT 5
#define AIPS_PACRF_SP6_MASK 0x40u
#define AIPS_PACRF_SP6_SHIFT 6
#define AIPS_PACRF_TP5_MASK 0x100u
#define AIPS_PACRF_TP5_SHIFT 8
#define AIPS_PACRF_WP5_MASK 0x200u
#define AIPS_PACRF_WP5_SHIFT 9
#define AIPS_PACRF_SP5_MASK 0x400u
#define AIPS_PACRF_SP5_SHIFT 10
#define AIPS_PACRF_TP4_MASK 0x1000u
#define AIPS_PACRF_TP4_SHIFT 12
#define AIPS_PACRF_WP4_MASK 0x2000u
#define AIPS_PACRF_WP4_SHIFT 13
#define AIPS_PACRF_SP4_MASK 0x4000u
#define AIPS_PACRF_SP4_SHIFT 14
#define AIPS_PACRF_TP3_MASK 0x10000u
#define AIPS_PACRF_TP3_SHIFT 16
#define AIPS_PACRF_WP3_MASK 0x20000u
#define AIPS_PACRF_WP3_SHIFT 17
#define AIPS_PACRF_SP3_MASK 0x40000u
#define AIPS_PACRF_SP3_SHIFT 18
#define AIPS_PACRF_TP2_MASK 0x100000u
#define AIPS_PACRF_TP2_SHIFT 20
#define AIPS_PACRF_WP2_MASK 0x200000u
#define AIPS_PACRF_WP2_SHIFT 21
#define AIPS_PACRF_SP2_MASK 0x400000u
#define AIPS_PACRF_SP2_SHIFT 22
#define AIPS_PACRF_TP1_MASK 0x1000000u
#define AIPS_PACRF_TP1_SHIFT 24
#define AIPS_PACRF_WP1_MASK 0x2000000u
#define AIPS_PACRF_WP1_SHIFT 25
#define AIPS_PACRF_SP1_MASK 0x4000000u
#define AIPS_PACRF_SP1_SHIFT 26
#define AIPS_PACRF_TP0_MASK 0x10000000u
#define AIPS_PACRF_TP0_SHIFT 28
#define AIPS_PACRF_WP0_MASK 0x20000000u
#define AIPS_PACRF_WP0_SHIFT 29
#define AIPS_PACRF_SP0_MASK 0x40000000u
#define AIPS_PACRF_SP0_SHIFT 30
/* PACRG Bit Fields */
#define AIPS_PACRG_TP7_MASK 0x1u
#define AIPS_PACRG_TP7_SHIFT 0
#define AIPS_PACRG_WP7_MASK 0x2u
#define AIPS_PACRG_WP7_SHIFT 1
#define AIPS_PACRG_SP7_MASK 0x4u
#define AIPS_PACRG_SP7_SHIFT 2
#define AIPS_PACRG_TP6_MASK 0x10u
#define AIPS_PACRG_TP6_SHIFT 4
#define AIPS_PACRG_WP6_MASK 0x20u
#define AIPS_PACRG_WP6_SHIFT 5
#define AIPS_PACRG_SP6_MASK 0x40u
#define AIPS_PACRG_SP6_SHIFT 6
#define AIPS_PACRG_TP5_MASK 0x100u
#define AIPS_PACRG_TP5_SHIFT 8
#define AIPS_PACRG_WP5_MASK 0x200u
#define AIPS_PACRG_WP5_SHIFT 9
#define AIPS_PACRG_SP5_MASK 0x400u
#define AIPS_PACRG_SP5_SHIFT 10
#define AIPS_PACRG_TP4_MASK 0x1000u
#define AIPS_PACRG_TP4_SHIFT 12
#define AIPS_PACRG_WP4_MASK 0x2000u
#define AIPS_PACRG_WP4_SHIFT 13
#define AIPS_PACRG_SP4_MASK 0x4000u
#define AIPS_PACRG_SP4_SHIFT 14
#define AIPS_PACRG_TP3_MASK 0x10000u
#define AIPS_PACRG_TP3_SHIFT 16
#define AIPS_PACRG_WP3_MASK 0x20000u
#define AIPS_PACRG_WP3_SHIFT 17
#define AIPS_PACRG_SP3_MASK 0x40000u
#define AIPS_PACRG_SP3_SHIFT 18
#define AIPS_PACRG_TP2_MASK 0x100000u
#define AIPS_PACRG_TP2_SHIFT 20
#define AIPS_PACRG_WP2_MASK 0x200000u
#define AIPS_PACRG_WP2_SHIFT 21
#define AIPS_PACRG_SP2_MASK 0x400000u
#define AIPS_PACRG_SP2_SHIFT 22
#define AIPS_PACRG_TP1_MASK 0x1000000u
#define AIPS_PACRG_TP1_SHIFT 24
#define AIPS_PACRG_WP1_MASK 0x2000000u
#define AIPS_PACRG_WP1_SHIFT 25
#define AIPS_PACRG_SP1_MASK 0x4000000u
#define AIPS_PACRG_SP1_SHIFT 26
#define AIPS_PACRG_TP0_MASK 0x10000000u
#define AIPS_PACRG_TP0_SHIFT 28
#define AIPS_PACRG_WP0_MASK 0x20000000u
#define AIPS_PACRG_WP0_SHIFT 29
#define AIPS_PACRG_SP0_MASK 0x40000000u
#define AIPS_PACRG_SP0_SHIFT 30
/* PACRH Bit Fields */
#define AIPS_PACRH_TP7_MASK 0x1u
#define AIPS_PACRH_TP7_SHIFT 0
#define AIPS_PACRH_WP7_MASK 0x2u
#define AIPS_PACRH_WP7_SHIFT 1
#define AIPS_PACRH_SP7_MASK 0x4u
#define AIPS_PACRH_SP7_SHIFT 2
#define AIPS_PACRH_TP6_MASK 0x10u
#define AIPS_PACRH_TP6_SHIFT 4
#define AIPS_PACRH_WP6_MASK 0x20u
#define AIPS_PACRH_WP6_SHIFT 5
#define AIPS_PACRH_SP6_MASK 0x40u
#define AIPS_PACRH_SP6_SHIFT 6
#define AIPS_PACRH_TP5_MASK 0x100u
#define AIPS_PACRH_TP5_SHIFT 8
#define AIPS_PACRH_WP5_MASK 0x200u
#define AIPS_PACRH_WP5_SHIFT 9
#define AIPS_PACRH_SP5_MASK 0x400u
#define AIPS_PACRH_SP5_SHIFT 10
#define AIPS_PACRH_TP4_MASK 0x1000u
#define AIPS_PACRH_TP4_SHIFT 12
#define AIPS_PACRH_WP4_MASK 0x2000u
#define AIPS_PACRH_WP4_SHIFT 13
#define AIPS_PACRH_SP4_MASK 0x4000u
#define AIPS_PACRH_SP4_SHIFT 14
#define AIPS_PACRH_TP3_MASK 0x10000u
#define AIPS_PACRH_TP3_SHIFT 16
#define AIPS_PACRH_WP3_MASK 0x20000u
#define AIPS_PACRH_WP3_SHIFT 17
#define AIPS_PACRH_SP3_MASK 0x40000u
#define AIPS_PACRH_SP3_SHIFT 18
#define AIPS_PACRH_TP2_MASK 0x100000u
#define AIPS_PACRH_TP2_SHIFT 20
#define AIPS_PACRH_WP2_MASK 0x200000u
#define AIPS_PACRH_WP2_SHIFT 21
#define AIPS_PACRH_SP2_MASK 0x400000u
#define AIPS_PACRH_SP2_SHIFT 22
#define AIPS_PACRH_TP1_MASK 0x1000000u
#define AIPS_PACRH_TP1_SHIFT 24
#define AIPS_PACRH_WP1_MASK 0x2000000u
#define AIPS_PACRH_WP1_SHIFT 25
#define AIPS_PACRH_SP1_MASK 0x4000000u
#define AIPS_PACRH_SP1_SHIFT 26
#define AIPS_PACRH_TP0_MASK 0x10000000u
#define AIPS_PACRH_TP0_SHIFT 28
#define AIPS_PACRH_WP0_MASK 0x20000000u
#define AIPS_PACRH_WP0_SHIFT 29
#define AIPS_PACRH_SP0_MASK 0x40000000u
#define AIPS_PACRH_SP0_SHIFT 30
/* PACRI Bit Fields */
#define AIPS_PACRI_TP7_MASK 0x1u
#define AIPS_PACRI_TP7_SHIFT 0
#define AIPS_PACRI_WP7_MASK 0x2u
#define AIPS_PACRI_WP7_SHIFT 1
#define AIPS_PACRI_SP7_MASK 0x4u
#define AIPS_PACRI_SP7_SHIFT 2
#define AIPS_PACRI_TP6_MASK 0x10u
#define AIPS_PACRI_TP6_SHIFT 4
#define AIPS_PACRI_WP6_MASK 0x20u
#define AIPS_PACRI_WP6_SHIFT 5
#define AIPS_PACRI_SP6_MASK 0x40u
#define AIPS_PACRI_SP6_SHIFT 6
#define AIPS_PACRI_TP5_MASK 0x100u
#define AIPS_PACRI_TP5_SHIFT 8
#define AIPS_PACRI_WP5_MASK 0x200u
#define AIPS_PACRI_WP5_SHIFT 9
#define AIPS_PACRI_SP5_MASK 0x400u
#define AIPS_PACRI_SP5_SHIFT 10
#define AIPS_PACRI_TP4_MASK 0x1000u
#define AIPS_PACRI_TP4_SHIFT 12
#define AIPS_PACRI_WP4_MASK 0x2000u
#define AIPS_PACRI_WP4_SHIFT 13
#define AIPS_PACRI_SP4_MASK 0x4000u
#define AIPS_PACRI_SP4_SHIFT 14
#define AIPS_PACRI_TP3_MASK 0x10000u
#define AIPS_PACRI_TP3_SHIFT 16
#define AIPS_PACRI_WP3_MASK 0x20000u
#define AIPS_PACRI_WP3_SHIFT 17
#define AIPS_PACRI_SP3_MASK 0x40000u
#define AIPS_PACRI_SP3_SHIFT 18
#define AIPS_PACRI_TP2_MASK 0x100000u
#define AIPS_PACRI_TP2_SHIFT 20
#define AIPS_PACRI_WP2_MASK 0x200000u
#define AIPS_PACRI_WP2_SHIFT 21
#define AIPS_PACRI_SP2_MASK 0x400000u
#define AIPS_PACRI_SP2_SHIFT 22
#define AIPS_PACRI_TP1_MASK 0x1000000u
#define AIPS_PACRI_TP1_SHIFT 24
#define AIPS_PACRI_WP1_MASK 0x2000000u
#define AIPS_PACRI_WP1_SHIFT 25
#define AIPS_PACRI_SP1_MASK 0x4000000u
#define AIPS_PACRI_SP1_SHIFT 26
#define AIPS_PACRI_TP0_MASK 0x10000000u
#define AIPS_PACRI_TP0_SHIFT 28
#define AIPS_PACRI_WP0_MASK 0x20000000u
#define AIPS_PACRI_WP0_SHIFT 29
#define AIPS_PACRI_SP0_MASK 0x40000000u
#define AIPS_PACRI_SP0_SHIFT 30
/* PACRJ Bit Fields */
#define AIPS_PACRJ_TP7_MASK 0x1u
#define AIPS_PACRJ_TP7_SHIFT 0
#define AIPS_PACRJ_WP7_MASK 0x2u
#define AIPS_PACRJ_WP7_SHIFT 1
#define AIPS_PACRJ_SP7_MASK 0x4u
#define AIPS_PACRJ_SP7_SHIFT 2
#define AIPS_PACRJ_TP6_MASK 0x10u
#define AIPS_PACRJ_TP6_SHIFT 4
#define AIPS_PACRJ_WP6_MASK 0x20u
#define AIPS_PACRJ_WP6_SHIFT 5
#define AIPS_PACRJ_SP6_MASK 0x40u
#define AIPS_PACRJ_SP6_SHIFT 6
#define AIPS_PACRJ_TP5_MASK 0x100u
#define AIPS_PACRJ_TP5_SHIFT 8
#define AIPS_PACRJ_WP5_MASK 0x200u
#define AIPS_PACRJ_WP5_SHIFT 9
#define AIPS_PACRJ_SP5_MASK 0x400u
#define AIPS_PACRJ_SP5_SHIFT 10
#define AIPS_PACRJ_TP4_MASK 0x1000u
#define AIPS_PACRJ_TP4_SHIFT 12
#define AIPS_PACRJ_WP4_MASK 0x2000u
#define AIPS_PACRJ_WP4_SHIFT 13
#define AIPS_PACRJ_SP4_MASK 0x4000u
#define AIPS_PACRJ_SP4_SHIFT 14
#define AIPS_PACRJ_TP3_MASK 0x10000u
#define AIPS_PACRJ_TP3_SHIFT 16
#define AIPS_PACRJ_WP3_MASK 0x20000u
#define AIPS_PACRJ_WP3_SHIFT 17
#define AIPS_PACRJ_SP3_MASK 0x40000u
#define AIPS_PACRJ_SP3_SHIFT 18
#define AIPS_PACRJ_TP2_MASK 0x100000u
#define AIPS_PACRJ_TP2_SHIFT 20
#define AIPS_PACRJ_WP2_MASK 0x200000u
#define AIPS_PACRJ_WP2_SHIFT 21
#define AIPS_PACRJ_SP2_MASK 0x400000u
#define AIPS_PACRJ_SP2_SHIFT 22
#define AIPS_PACRJ_TP1_MASK 0x1000000u
#define AIPS_PACRJ_TP1_SHIFT 24
#define AIPS_PACRJ_WP1_MASK 0x2000000u
#define AIPS_PACRJ_WP1_SHIFT 25
#define AIPS_PACRJ_SP1_MASK 0x4000000u
#define AIPS_PACRJ_SP1_SHIFT 26
#define AIPS_PACRJ_TP0_MASK 0x10000000u
#define AIPS_PACRJ_TP0_SHIFT 28
#define AIPS_PACRJ_WP0_MASK 0x20000000u
#define AIPS_PACRJ_WP0_SHIFT 29
#define AIPS_PACRJ_SP0_MASK 0x40000000u
#define AIPS_PACRJ_SP0_SHIFT 30
/* PACRK Bit Fields */
#define AIPS_PACRK_TP7_MASK 0x1u
#define AIPS_PACRK_TP7_SHIFT 0
#define AIPS_PACRK_WP7_MASK 0x2u
#define AIPS_PACRK_WP7_SHIFT 1
#define AIPS_PACRK_SP7_MASK 0x4u
#define AIPS_PACRK_SP7_SHIFT 2
#define AIPS_PACRK_TP6_MASK 0x10u
#define AIPS_PACRK_TP6_SHIFT 4
#define AIPS_PACRK_WP6_MASK 0x20u
#define AIPS_PACRK_WP6_SHIFT 5
#define AIPS_PACRK_SP6_MASK 0x40u
#define AIPS_PACRK_SP6_SHIFT 6
#define AIPS_PACRK_TP5_MASK 0x100u
#define AIPS_PACRK_TP5_SHIFT 8
#define AIPS_PACRK_WP5_MASK 0x200u
#define AIPS_PACRK_WP5_SHIFT 9
#define AIPS_PACRK_SP5_MASK 0x400u
#define AIPS_PACRK_SP5_SHIFT 10
#define AIPS_PACRK_TP4_MASK 0x1000u
#define AIPS_PACRK_TP4_SHIFT 12
#define AIPS_PACRK_WP4_MASK 0x2000u
#define AIPS_PACRK_WP4_SHIFT 13
#define AIPS_PACRK_SP4_MASK 0x4000u
#define AIPS_PACRK_SP4_SHIFT 14
#define AIPS_PACRK_TP3_MASK 0x10000u
#define AIPS_PACRK_TP3_SHIFT 16
#define AIPS_PACRK_WP3_MASK 0x20000u
#define AIPS_PACRK_WP3_SHIFT 17
#define AIPS_PACRK_SP3_MASK 0x40000u
#define AIPS_PACRK_SP3_SHIFT 18
#define AIPS_PACRK_TP2_MASK 0x100000u
#define AIPS_PACRK_TP2_SHIFT 20
#define AIPS_PACRK_WP2_MASK 0x200000u
#define AIPS_PACRK_WP2_SHIFT 21
#define AIPS_PACRK_SP2_MASK 0x400000u
#define AIPS_PACRK_SP2_SHIFT 22
#define AIPS_PACRK_TP1_MASK 0x1000000u
#define AIPS_PACRK_TP1_SHIFT 24
#define AIPS_PACRK_WP1_MASK 0x2000000u
#define AIPS_PACRK_WP1_SHIFT 25
#define AIPS_PACRK_SP1_MASK 0x4000000u
#define AIPS_PACRK_SP1_SHIFT 26
#define AIPS_PACRK_TP0_MASK 0x10000000u
#define AIPS_PACRK_TP0_SHIFT 28
#define AIPS_PACRK_WP0_MASK 0x20000000u
#define AIPS_PACRK_WP0_SHIFT 29
#define AIPS_PACRK_SP0_MASK 0x40000000u
#define AIPS_PACRK_SP0_SHIFT 30
/* PACRL Bit Fields */
#define AIPS_PACRL_TP7_MASK 0x1u
#define AIPS_PACRL_TP7_SHIFT 0
#define AIPS_PACRL_WP7_MASK 0x2u
#define AIPS_PACRL_WP7_SHIFT 1
#define AIPS_PACRL_SP7_MASK 0x4u
#define AIPS_PACRL_SP7_SHIFT 2
#define AIPS_PACRL_TP6_MASK 0x10u
#define AIPS_PACRL_TP6_SHIFT 4
#define AIPS_PACRL_WP6_MASK 0x20u
#define AIPS_PACRL_WP6_SHIFT 5
#define AIPS_PACRL_SP6_MASK 0x40u
#define AIPS_PACRL_SP6_SHIFT 6
#define AIPS_PACRL_TP5_MASK 0x100u
#define AIPS_PACRL_TP5_SHIFT 8
#define AIPS_PACRL_WP5_MASK 0x200u
#define AIPS_PACRL_WP5_SHIFT 9
#define AIPS_PACRL_SP5_MASK 0x400u
#define AIPS_PACRL_SP5_SHIFT 10
#define AIPS_PACRL_TP4_MASK 0x1000u
#define AIPS_PACRL_TP4_SHIFT 12
#define AIPS_PACRL_WP4_MASK 0x2000u
#define AIPS_PACRL_WP4_SHIFT 13
#define AIPS_PACRL_SP4_MASK 0x4000u
#define AIPS_PACRL_SP4_SHIFT 14
#define AIPS_PACRL_TP3_MASK 0x10000u
#define AIPS_PACRL_TP3_SHIFT 16
#define AIPS_PACRL_WP3_MASK 0x20000u
#define AIPS_PACRL_WP3_SHIFT 17
#define AIPS_PACRL_SP3_MASK 0x40000u
#define AIPS_PACRL_SP3_SHIFT 18
#define AIPS_PACRL_TP2_MASK 0x100000u
#define AIPS_PACRL_TP2_SHIFT 20
#define AIPS_PACRL_WP2_MASK 0x200000u
#define AIPS_PACRL_WP2_SHIFT 21
#define AIPS_PACRL_SP2_MASK 0x400000u
#define AIPS_PACRL_SP2_SHIFT 22
#define AIPS_PACRL_TP1_MASK 0x1000000u
#define AIPS_PACRL_TP1_SHIFT 24
#define AIPS_PACRL_WP1_MASK 0x2000000u
#define AIPS_PACRL_WP1_SHIFT 25
#define AIPS_PACRL_SP1_MASK 0x4000000u
#define AIPS_PACRL_SP1_SHIFT 26
#define AIPS_PACRL_TP0_MASK 0x10000000u
#define AIPS_PACRL_TP0_SHIFT 28
#define AIPS_PACRL_WP0_MASK 0x20000000u
#define AIPS_PACRL_WP0_SHIFT 29
#define AIPS_PACRL_SP0_MASK 0x40000000u
#define AIPS_PACRL_SP0_SHIFT 30
/* PACRM Bit Fields */
#define AIPS_PACRM_TP7_MASK 0x1u
#define AIPS_PACRM_TP7_SHIFT 0
#define AIPS_PACRM_WP7_MASK 0x2u
#define AIPS_PACRM_WP7_SHIFT 1
#define AIPS_PACRM_SP7_MASK 0x4u
#define AIPS_PACRM_SP7_SHIFT 2
#define AIPS_PACRM_TP6_MASK 0x10u
#define AIPS_PACRM_TP6_SHIFT 4
#define AIPS_PACRM_WP6_MASK 0x20u
#define AIPS_PACRM_WP6_SHIFT 5
#define AIPS_PACRM_SP6_MASK 0x40u
#define AIPS_PACRM_SP6_SHIFT 6
#define AIPS_PACRM_TP5_MASK 0x100u
#define AIPS_PACRM_TP5_SHIFT 8
#define AIPS_PACRM_WP5_MASK 0x200u
#define AIPS_PACRM_WP5_SHIFT 9
#define AIPS_PACRM_SP5_MASK 0x400u
#define AIPS_PACRM_SP5_SHIFT 10
#define AIPS_PACRM_TP4_MASK 0x1000u
#define AIPS_PACRM_TP4_SHIFT 12
#define AIPS_PACRM_WP4_MASK 0x2000u
#define AIPS_PACRM_WP4_SHIFT 13
#define AIPS_PACRM_SP4_MASK 0x4000u
#define AIPS_PACRM_SP4_SHIFT 14
#define AIPS_PACRM_TP3_MASK 0x10000u
#define AIPS_PACRM_TP3_SHIFT 16
#define AIPS_PACRM_WP3_MASK 0x20000u
#define AIPS_PACRM_WP3_SHIFT 17
#define AIPS_PACRM_SP3_MASK 0x40000u
#define AIPS_PACRM_SP3_SHIFT 18
#define AIPS_PACRM_TP2_MASK 0x100000u
#define AIPS_PACRM_TP2_SHIFT 20
#define AIPS_PACRM_WP2_MASK 0x200000u
#define AIPS_PACRM_WP2_SHIFT 21
#define AIPS_PACRM_SP2_MASK 0x400000u
#define AIPS_PACRM_SP2_SHIFT 22
#define AIPS_PACRM_TP1_MASK 0x1000000u
#define AIPS_PACRM_TP1_SHIFT 24
#define AIPS_PACRM_WP1_MASK 0x2000000u
#define AIPS_PACRM_WP1_SHIFT 25
#define AIPS_PACRM_SP1_MASK 0x4000000u
#define AIPS_PACRM_SP1_SHIFT 26
#define AIPS_PACRM_TP0_MASK 0x10000000u
#define AIPS_PACRM_TP0_SHIFT 28
#define AIPS_PACRM_WP0_MASK 0x20000000u
#define AIPS_PACRM_WP0_SHIFT 29
#define AIPS_PACRM_SP0_MASK 0x40000000u
#define AIPS_PACRM_SP0_SHIFT 30
/* PACRN Bit Fields */
#define AIPS_PACRN_TP7_MASK 0x1u
#define AIPS_PACRN_TP7_SHIFT 0
#define AIPS_PACRN_WP7_MASK 0x2u
#define AIPS_PACRN_WP7_SHIFT 1
#define AIPS_PACRN_SP7_MASK 0x4u
#define AIPS_PACRN_SP7_SHIFT 2
#define AIPS_PACRN_TP6_MASK 0x10u
#define AIPS_PACRN_TP6_SHIFT 4
#define AIPS_PACRN_WP6_MASK 0x20u
#define AIPS_PACRN_WP6_SHIFT 5
#define AIPS_PACRN_SP6_MASK 0x40u
#define AIPS_PACRN_SP6_SHIFT 6
#define AIPS_PACRN_TP5_MASK 0x100u
#define AIPS_PACRN_TP5_SHIFT 8
#define AIPS_PACRN_WP5_MASK 0x200u
#define AIPS_PACRN_WP5_SHIFT 9
#define AIPS_PACRN_SP5_MASK 0x400u
#define AIPS_PACRN_SP5_SHIFT 10
#define AIPS_PACRN_TP4_MASK 0x1000u
#define AIPS_PACRN_TP4_SHIFT 12
#define AIPS_PACRN_WP4_MASK 0x2000u
#define AIPS_PACRN_WP4_SHIFT 13
#define AIPS_PACRN_SP4_MASK 0x4000u
#define AIPS_PACRN_SP4_SHIFT 14
#define AIPS_PACRN_TP3_MASK 0x10000u
#define AIPS_PACRN_TP3_SHIFT 16
#define AIPS_PACRN_WP3_MASK 0x20000u
#define AIPS_PACRN_WP3_SHIFT 17
#define AIPS_PACRN_SP3_MASK 0x40000u
#define AIPS_PACRN_SP3_SHIFT 18
#define AIPS_PACRN_TP2_MASK 0x100000u
#define AIPS_PACRN_TP2_SHIFT 20
#define AIPS_PACRN_WP2_MASK 0x200000u
#define AIPS_PACRN_WP2_SHIFT 21
#define AIPS_PACRN_SP2_MASK 0x400000u
#define AIPS_PACRN_SP2_SHIFT 22
#define AIPS_PACRN_TP1_MASK 0x1000000u
#define AIPS_PACRN_TP1_SHIFT 24
#define AIPS_PACRN_WP1_MASK 0x2000000u
#define AIPS_PACRN_WP1_SHIFT 25
#define AIPS_PACRN_SP1_MASK 0x4000000u
#define AIPS_PACRN_SP1_SHIFT 26
#define AIPS_PACRN_TP0_MASK 0x10000000u
#define AIPS_PACRN_TP0_SHIFT 28
#define AIPS_PACRN_WP0_MASK 0x20000000u
#define AIPS_PACRN_WP0_SHIFT 29
#define AIPS_PACRN_SP0_MASK 0x40000000u
#define AIPS_PACRN_SP0_SHIFT 30
/* PACRO Bit Fields */
#define AIPS_PACRO_TP7_MASK 0x1u
#define AIPS_PACRO_TP7_SHIFT 0
#define AIPS_PACRO_WP7_MASK 0x2u
#define AIPS_PACRO_WP7_SHIFT 1
#define AIPS_PACRO_SP7_MASK 0x4u
#define AIPS_PACRO_SP7_SHIFT 2
#define AIPS_PACRO_TP6_MASK 0x10u
#define AIPS_PACRO_TP6_SHIFT 4
#define AIPS_PACRO_WP6_MASK 0x20u
#define AIPS_PACRO_WP6_SHIFT 5
#define AIPS_PACRO_SP6_MASK 0x40u
#define AIPS_PACRO_SP6_SHIFT 6
#define AIPS_PACRO_TP5_MASK 0x100u
#define AIPS_PACRO_TP5_SHIFT 8
#define AIPS_PACRO_WP5_MASK 0x200u
#define AIPS_PACRO_WP5_SHIFT 9
#define AIPS_PACRO_SP5_MASK 0x400u
#define AIPS_PACRO_SP5_SHIFT 10
#define AIPS_PACRO_TP4_MASK 0x1000u
#define AIPS_PACRO_TP4_SHIFT 12
#define AIPS_PACRO_WP4_MASK 0x2000u
#define AIPS_PACRO_WP4_SHIFT 13
#define AIPS_PACRO_SP4_MASK 0x4000u
#define AIPS_PACRO_SP4_SHIFT 14
#define AIPS_PACRO_TP3_MASK 0x10000u
#define AIPS_PACRO_TP3_SHIFT 16
#define AIPS_PACRO_WP3_MASK 0x20000u
#define AIPS_PACRO_WP3_SHIFT 17
#define AIPS_PACRO_SP3_MASK 0x40000u
#define AIPS_PACRO_SP3_SHIFT 18
#define AIPS_PACRO_TP2_MASK 0x100000u
#define AIPS_PACRO_TP2_SHIFT 20
#define AIPS_PACRO_WP2_MASK 0x200000u
#define AIPS_PACRO_WP2_SHIFT 21
#define AIPS_PACRO_SP2_MASK 0x400000u
#define AIPS_PACRO_SP2_SHIFT 22
#define AIPS_PACRO_TP1_MASK 0x1000000u
#define AIPS_PACRO_TP1_SHIFT 24
#define AIPS_PACRO_WP1_MASK 0x2000000u
#define AIPS_PACRO_WP1_SHIFT 25
#define AIPS_PACRO_SP1_MASK 0x4000000u
#define AIPS_PACRO_SP1_SHIFT 26
#define AIPS_PACRO_TP0_MASK 0x10000000u
#define AIPS_PACRO_TP0_SHIFT 28
#define AIPS_PACRO_WP0_MASK 0x20000000u
#define AIPS_PACRO_WP0_SHIFT 29
#define AIPS_PACRO_SP0_MASK 0x40000000u
#define AIPS_PACRO_SP0_SHIFT 30
/* PACRP Bit Fields */
#define AIPS_PACRP_TP7_MASK 0x1u
#define AIPS_PACRP_TP7_SHIFT 0
#define AIPS_PACRP_WP7_MASK 0x2u
#define AIPS_PACRP_WP7_SHIFT 1
#define AIPS_PACRP_SP7_MASK 0x4u
#define AIPS_PACRP_SP7_SHIFT 2
#define AIPS_PACRP_TP6_MASK 0x10u
#define AIPS_PACRP_TP6_SHIFT 4
#define AIPS_PACRP_WP6_MASK 0x20u
#define AIPS_PACRP_WP6_SHIFT 5
#define AIPS_PACRP_SP6_MASK 0x40u
#define AIPS_PACRP_SP6_SHIFT 6
#define AIPS_PACRP_TP5_MASK 0x100u
#define AIPS_PACRP_TP5_SHIFT 8
#define AIPS_PACRP_WP5_MASK 0x200u
#define AIPS_PACRP_WP5_SHIFT 9
#define AIPS_PACRP_SP5_MASK 0x400u
#define AIPS_PACRP_SP5_SHIFT 10
#define AIPS_PACRP_TP4_MASK 0x1000u
#define AIPS_PACRP_TP4_SHIFT 12
#define AIPS_PACRP_WP4_MASK 0x2000u
#define AIPS_PACRP_WP4_SHIFT 13
#define AIPS_PACRP_SP4_MASK 0x4000u
#define AIPS_PACRP_SP4_SHIFT 14
#define AIPS_PACRP_TP3_MASK 0x10000u
#define AIPS_PACRP_TP3_SHIFT 16
#define AIPS_PACRP_WP3_MASK 0x20000u
#define AIPS_PACRP_WP3_SHIFT 17
#define AIPS_PACRP_SP3_MASK 0x40000u
#define AIPS_PACRP_SP3_SHIFT 18
#define AIPS_PACRP_TP2_MASK 0x100000u
#define AIPS_PACRP_TP2_SHIFT 20
#define AIPS_PACRP_WP2_MASK 0x200000u
#define AIPS_PACRP_WP2_SHIFT 21
#define AIPS_PACRP_SP2_MASK 0x400000u
#define AIPS_PACRP_SP2_SHIFT 22
#define AIPS_PACRP_TP1_MASK 0x1000000u
#define AIPS_PACRP_TP1_SHIFT 24
#define AIPS_PACRP_WP1_MASK 0x2000000u
#define AIPS_PACRP_WP1_SHIFT 25
#define AIPS_PACRP_SP1_MASK 0x4000000u
#define AIPS_PACRP_SP1_SHIFT 26
#define AIPS_PACRP_TP0_MASK 0x10000000u
#define AIPS_PACRP_TP0_SHIFT 28
#define AIPS_PACRP_WP0_MASK 0x20000000u
#define AIPS_PACRP_WP0_SHIFT 29
#define AIPS_PACRP_SP0_MASK 0x40000000u
#define AIPS_PACRP_SP0_SHIFT 30
/*!
* @}
*/ /* end of group AIPS_Register_Masks */
/* AIPS - Peripheral instance base addresses */
/** Peripheral AIPS0 base address */
#define AIPS0_BASE (0x40000000u)
/** Peripheral AIPS0 base pointer */
#define AIPS0 ((AIPS_Type *)AIPS0_BASE)
#define AIPS0_BASE_PTR (AIPS0)
/** Peripheral AIPS1 base address */
#define AIPS1_BASE (0x40080000u)
/** Peripheral AIPS1 base pointer */
#define AIPS1 ((AIPS_Type *)AIPS1_BASE)
#define AIPS1_BASE_PTR (AIPS1)
/** Array initializer of AIPS peripheral base addresses */
#define AIPS_BASE_ADDRS { AIPS0_BASE, AIPS1_BASE }
/** Array initializer of AIPS peripheral base pointers */
#define AIPS_BASE_PTRS { AIPS0, AIPS1 }
/* ----------------------------------------------------------------------------
-- AIPS - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup AIPS_Register_Accessor_Macros AIPS - Register accessor macros
* @{
*/
/* AIPS - Register instance definitions */
/* AIPS0 */
#define AIPS0_MPRA AIPS_MPRA_REG(AIPS0)
#define AIPS0_PACRA AIPS_PACRA_REG(AIPS0)
#define AIPS0_PACRB AIPS_PACRB_REG(AIPS0)
#define AIPS0_PACRC AIPS_PACRC_REG(AIPS0)
#define AIPS0_PACRD AIPS_PACRD_REG(AIPS0)
#define AIPS0_PACRE AIPS_PACRE_REG(AIPS0)
#define AIPS0_PACRF AIPS_PACRF_REG(AIPS0)
#define AIPS0_PACRG AIPS_PACRG_REG(AIPS0)
#define AIPS0_PACRH AIPS_PACRH_REG(AIPS0)
#define AIPS0_PACRI AIPS_PACRI_REG(AIPS0)
#define AIPS0_PACRJ AIPS_PACRJ_REG(AIPS0)
#define AIPS0_PACRK AIPS_PACRK_REG(AIPS0)
#define AIPS0_PACRL AIPS_PACRL_REG(AIPS0)
#define AIPS0_PACRM AIPS_PACRM_REG(AIPS0)
#define AIPS0_PACRN AIPS_PACRN_REG(AIPS0)
#define AIPS0_PACRO AIPS_PACRO_REG(AIPS0)
#define AIPS0_PACRP AIPS_PACRP_REG(AIPS0)
/* AIPS1 */
#define AIPS1_MPRA AIPS_MPRA_REG(AIPS1)
#define AIPS1_PACRA AIPS_PACRA_REG(AIPS1)
#define AIPS1_PACRB AIPS_PACRB_REG(AIPS1)
#define AIPS1_PACRC AIPS_PACRC_REG(AIPS1)
#define AIPS1_PACRD AIPS_PACRD_REG(AIPS1)
#define AIPS1_PACRE AIPS_PACRE_REG(AIPS1)
#define AIPS1_PACRF AIPS_PACRF_REG(AIPS1)
#define AIPS1_PACRG AIPS_PACRG_REG(AIPS1)
#define AIPS1_PACRH AIPS_PACRH_REG(AIPS1)
#define AIPS1_PACRI AIPS_PACRI_REG(AIPS1)
#define AIPS1_PACRJ AIPS_PACRJ_REG(AIPS1)
#define AIPS1_PACRK AIPS_PACRK_REG(AIPS1)
#define AIPS1_PACRL AIPS_PACRL_REG(AIPS1)
#define AIPS1_PACRM AIPS_PACRM_REG(AIPS1)
#define AIPS1_PACRN AIPS_PACRN_REG(AIPS1)
#define AIPS1_PACRO AIPS_PACRO_REG(AIPS1)
#define AIPS1_PACRP AIPS_PACRP_REG(AIPS1)
/*!
* @}
*/ /* end of group AIPS_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group AIPS_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- AXBS Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup AXBS_Peripheral_Access_Layer AXBS Peripheral Access Layer
* @{
*/
/** AXBS - Register Layout Typedef */
typedef struct {
struct { /* offset: 0x0, array step: 0x100 */
__IO uint32_t PRS; /**< Priority Registers Slave, array offset: 0x0, array step: 0x100 */
uint8_t RESERVED_0[12];
__IO uint32_t CRS; /**< Control Register, array offset: 0x10, array step: 0x100 */
uint8_t RESERVED_1[236];
} SLAVE[5];
uint8_t RESERVED_0[768];
__IO uint32_t MGPCR0; /**< Master General Purpose Control Register, offset: 0x800 */
uint8_t RESERVED_1[252];
__IO uint32_t MGPCR1; /**< Master General Purpose Control Register, offset: 0x900 */
uint8_t RESERVED_2[252];
__IO uint32_t MGPCR2; /**< Master General Purpose Control Register, offset: 0xA00 */
uint8_t RESERVED_3[252];
__IO uint32_t MGPCR3; /**< Master General Purpose Control Register, offset: 0xB00 */
uint8_t RESERVED_4[252];
__IO uint32_t MGPCR4; /**< Master General Purpose Control Register, offset: 0xC00 */
uint8_t RESERVED_5[252];
__IO uint32_t MGPCR5; /**< Master General Purpose Control Register, offset: 0xD00 */
} AXBS_Type, *AXBS_MemMapPtr;
/* ----------------------------------------------------------------------------
-- AXBS - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup AXBS_Register_Accessor_Macros AXBS - Register accessor macros
* @{
*/
/* AXBS - Register accessors */
#define AXBS_PRS_REG(base,index) ((base)->SLAVE[index].PRS)
#define AXBS_CRS_REG(base,index) ((base)->SLAVE[index].CRS)
#define AXBS_MGPCR0_REG(base) ((base)->MGPCR0)
#define AXBS_MGPCR1_REG(base) ((base)->MGPCR1)
#define AXBS_MGPCR2_REG(base) ((base)->MGPCR2)
#define AXBS_MGPCR3_REG(base) ((base)->MGPCR3)
#define AXBS_MGPCR4_REG(base) ((base)->MGPCR4)
#define AXBS_MGPCR5_REG(base) ((base)->MGPCR5)
/*!
* @}
*/ /* end of group AXBS_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- AXBS Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup AXBS_Register_Masks AXBS Register Masks
* @{
*/
/* PRS Bit Fields */
#define AXBS_PRS_M0_MASK 0x7u
#define AXBS_PRS_M0_SHIFT 0
#define AXBS_PRS_M0(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M0_SHIFT))&AXBS_PRS_M0_MASK)
#define AXBS_PRS_M1_MASK 0x70u
#define AXBS_PRS_M1_SHIFT 4
#define AXBS_PRS_M1(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M1_SHIFT))&AXBS_PRS_M1_MASK)
#define AXBS_PRS_M2_MASK 0x700u
#define AXBS_PRS_M2_SHIFT 8
#define AXBS_PRS_M2(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M2_SHIFT))&AXBS_PRS_M2_MASK)
#define AXBS_PRS_M3_MASK 0x7000u
#define AXBS_PRS_M3_SHIFT 12
#define AXBS_PRS_M3(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M3_SHIFT))&AXBS_PRS_M3_MASK)
#define AXBS_PRS_M4_MASK 0x70000u
#define AXBS_PRS_M4_SHIFT 16
#define AXBS_PRS_M4(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M4_SHIFT))&AXBS_PRS_M4_MASK)
#define AXBS_PRS_M5_MASK 0x700000u
#define AXBS_PRS_M5_SHIFT 20
#define AXBS_PRS_M5(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M5_SHIFT))&AXBS_PRS_M5_MASK)
/* CRS Bit Fields */
#define AXBS_CRS_PARK_MASK 0x7u
#define AXBS_CRS_PARK_SHIFT 0
#define AXBS_CRS_PARK(x) (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_PARK_SHIFT))&AXBS_CRS_PARK_MASK)
#define AXBS_CRS_PCTL_MASK 0x30u
#define AXBS_CRS_PCTL_SHIFT 4
#define AXBS_CRS_PCTL(x) (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_PCTL_SHIFT))&AXBS_CRS_PCTL_MASK)
#define AXBS_CRS_ARB_MASK 0x300u
#define AXBS_CRS_ARB_SHIFT 8
#define AXBS_CRS_ARB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_ARB_SHIFT))&AXBS_CRS_ARB_MASK)
#define AXBS_CRS_HLP_MASK 0x40000000u
#define AXBS_CRS_HLP_SHIFT 30
#define AXBS_CRS_RO_MASK 0x80000000u
#define AXBS_CRS_RO_SHIFT 31
/* MGPCR0 Bit Fields */
#define AXBS_MGPCR0_AULB_MASK 0x7u
#define AXBS_MGPCR0_AULB_SHIFT 0
#define AXBS_MGPCR0_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR0_AULB_SHIFT))&AXBS_MGPCR0_AULB_MASK)
/* MGPCR1 Bit Fields */
#define AXBS_MGPCR1_AULB_MASK 0x7u
#define AXBS_MGPCR1_AULB_SHIFT 0
#define AXBS_MGPCR1_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR1_AULB_SHIFT))&AXBS_MGPCR1_AULB_MASK)
/* MGPCR2 Bit Fields */
#define AXBS_MGPCR2_AULB_MASK 0x7u
#define AXBS_MGPCR2_AULB_SHIFT 0
#define AXBS_MGPCR2_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR2_AULB_SHIFT))&AXBS_MGPCR2_AULB_MASK)
/* MGPCR3 Bit Fields */
#define AXBS_MGPCR3_AULB_MASK 0x7u
#define AXBS_MGPCR3_AULB_SHIFT 0
#define AXBS_MGPCR3_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR3_AULB_SHIFT))&AXBS_MGPCR3_AULB_MASK)
/* MGPCR4 Bit Fields */
#define AXBS_MGPCR4_AULB_MASK 0x7u
#define AXBS_MGPCR4_AULB_SHIFT 0
#define AXBS_MGPCR4_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR4_AULB_SHIFT))&AXBS_MGPCR4_AULB_MASK)
/* MGPCR5 Bit Fields */
#define AXBS_MGPCR5_AULB_MASK 0x7u
#define AXBS_MGPCR5_AULB_SHIFT 0
#define AXBS_MGPCR5_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR5_AULB_SHIFT))&AXBS_MGPCR5_AULB_MASK)
/*!
* @}
*/ /* end of group AXBS_Register_Masks */
/* AXBS - Peripheral instance base addresses */
/** Peripheral AXBS base address */
#define AXBS_BASE (0x40004000u)
/** Peripheral AXBS base pointer */
#define AXBS ((AXBS_Type *)AXBS_BASE)
#define AXBS_BASE_PTR (AXBS)
/** Array initializer of AXBS peripheral base addresses */
#define AXBS_BASE_ADDRS { AXBS_BASE }
/** Array initializer of AXBS peripheral base pointers */
#define AXBS_BASE_PTRS { AXBS }
/* ----------------------------------------------------------------------------
-- AXBS - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup AXBS_Register_Accessor_Macros AXBS - Register accessor macros
* @{
*/
/* AXBS - Register instance definitions */
/* AXBS */
#define AXBS_PRS0 AXBS_PRS_REG(AXBS,0)
#define AXBS_CRS0 AXBS_CRS_REG(AXBS,0)
#define AXBS_PRS1 AXBS_PRS_REG(AXBS,1)
#define AXBS_CRS1 AXBS_CRS_REG(AXBS,1)
#define AXBS_PRS2 AXBS_PRS_REG(AXBS,2)
#define AXBS_CRS2 AXBS_CRS_REG(AXBS,2)
#define AXBS_PRS3 AXBS_PRS_REG(AXBS,3)
#define AXBS_CRS3 AXBS_CRS_REG(AXBS,3)
#define AXBS_PRS4 AXBS_PRS_REG(AXBS,4)
#define AXBS_CRS4 AXBS_CRS_REG(AXBS,4)
#define AXBS_MGPCR0 AXBS_MGPCR0_REG(AXBS)
#define AXBS_MGPCR1 AXBS_MGPCR1_REG(AXBS)
#define AXBS_MGPCR2 AXBS_MGPCR2_REG(AXBS)
#define AXBS_MGPCR3 AXBS_MGPCR3_REG(AXBS)
#define AXBS_MGPCR4 AXBS_MGPCR4_REG(AXBS)
#define AXBS_MGPCR5 AXBS_MGPCR5_REG(AXBS)
/* AXBS - Register array accessors */
#define AXBS_PRS(index) AXBS_PRS_REG(AXBS,index)
#define AXBS_CRS(index) AXBS_CRS_REG(AXBS,index)
/*!
* @}
*/ /* end of group AXBS_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group AXBS_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- CAN Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
* @{
*/
/** CAN - Register Layout Typedef */
typedef struct {
__IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
__IO uint32_t CTRL1; /**< Control 1 register, offset: 0x4 */
__IO uint32_t TIMER; /**< Free Running Timer, offset: 0x8 */
uint8_t RESERVED_0[4];
__IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask Register, offset: 0x10 */
__IO uint32_t RX14MASK; /**< Rx 14 Mask register, offset: 0x14 */
__IO uint32_t RX15MASK; /**< Rx 15 Mask register, offset: 0x18 */
__IO uint32_t ECR; /**< Error Counter, offset: 0x1C */
__IO uint32_t ESR1; /**< Error and Status 1 register, offset: 0x20 */
uint8_t RESERVED_1[4];
__IO uint32_t IMASK1; /**< Interrupt Masks 1 register, offset: 0x28 */
uint8_t RESERVED_2[4];
__IO uint32_t IFLAG1; /**< Interrupt Flags 1 register, offset: 0x30 */
__IO uint32_t CTRL2; /**< Control 2 register, offset: 0x34 */
__I uint32_t ESR2; /**< Error and Status 2 register, offset: 0x38 */
uint8_t RESERVED_3[8];
__I uint32_t CRCR; /**< CRC Register, offset: 0x44 */
__IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask register, offset: 0x48 */
__I uint32_t RXFIR; /**< Rx FIFO Information Register, offset: 0x4C */
uint8_t RESERVED_4[48];
struct { /* offset: 0x80, array step: 0x10 */
__IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 15 CS Register, array offset: 0x80, array step: 0x10 */
__IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 15 ID Register, array offset: 0x84, array step: 0x10 */
__IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register, array offset: 0x88, array step: 0x10 */
__IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register, array offset: 0x8C, array step: 0x10 */
} MB[16];
uint8_t RESERVED_5[1792];
__IO uint32_t RXIMR[16]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */
} CAN_Type, *CAN_MemMapPtr;
/* ----------------------------------------------------------------------------
-- CAN - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup CAN_Register_Accessor_Macros CAN - Register accessor macros
* @{
*/
/* CAN - Register accessors */
#define CAN_MCR_REG(base) ((base)->MCR)
#define CAN_CTRL1_REG(base) ((base)->CTRL1)
#define CAN_TIMER_REG(base) ((base)->TIMER)
#define CAN_RXMGMASK_REG(base) ((base)->RXMGMASK)
#define CAN_RX14MASK_REG(base) ((base)->RX14MASK)
#define CAN_RX15MASK_REG(base) ((base)->RX15MASK)
#define CAN_ECR_REG(base) ((base)->ECR)
#define CAN_ESR1_REG(base) ((base)->ESR1)
#define CAN_IMASK1_REG(base) ((base)->IMASK1)
#define CAN_IFLAG1_REG(base) ((base)->IFLAG1)
#define CAN_CTRL2_REG(base) ((base)->CTRL2)
#define CAN_ESR2_REG(base) ((base)->ESR2)
#define CAN_CRCR_REG(base) ((base)->CRCR)
#define CAN_RXFGMASK_REG(base) ((base)->RXFGMASK)
#define CAN_RXFIR_REG(base) ((base)->RXFIR)
#define CAN_CS_REG(base,index) ((base)->MB[index].CS)
#define CAN_ID_REG(base,index) ((base)->MB[index].ID)
#define CAN_WORD0_REG(base,index) ((base)->MB[index].WORD0)
#define CAN_WORD1_REG(base,index) ((base)->MB[index].WORD1)
#define CAN_RXIMR_REG(base,index) ((base)->RXIMR[index])
/*!
* @}
*/ /* end of group CAN_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- CAN Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup CAN_Register_Masks CAN Register Masks
* @{
*/
/* MCR Bit Fields */
#define CAN_MCR_MAXMB_MASK 0x7Fu
#define CAN_MCR_MAXMB_SHIFT 0
#define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_MAXMB_SHIFT))&CAN_MCR_MAXMB_MASK)
#define CAN_MCR_IDAM_MASK 0x300u
#define CAN_MCR_IDAM_SHIFT 8
#define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_IDAM_SHIFT))&CAN_MCR_IDAM_MASK)
#define CAN_MCR_AEN_MASK 0x1000u
#define CAN_MCR_AEN_SHIFT 12
#define CAN_MCR_LPRIOEN_MASK 0x2000u
#define CAN_MCR_LPRIOEN_SHIFT 13
#define CAN_MCR_IRMQ_MASK 0x10000u
#define CAN_MCR_IRMQ_SHIFT 16
#define CAN_MCR_SRXDIS_MASK 0x20000u
#define CAN_MCR_SRXDIS_SHIFT 17
#define CAN_MCR_WAKSRC_MASK 0x80000u
#define CAN_MCR_WAKSRC_SHIFT 19
#define CAN_MCR_LPMACK_MASK 0x100000u
#define CAN_MCR_LPMACK_SHIFT 20
#define CAN_MCR_WRNEN_MASK 0x200000u
#define CAN_MCR_WRNEN_SHIFT 21
#define CAN_MCR_SLFWAK_MASK 0x400000u
#define CAN_MCR_SLFWAK_SHIFT 22
#define CAN_MCR_SUPV_MASK 0x800000u
#define CAN_MCR_SUPV_SHIFT 23
#define CAN_MCR_FRZACK_MASK 0x1000000u
#define CAN_MCR_FRZACK_SHIFT 24
#define CAN_MCR_SOFTRST_MASK 0x2000000u
#define CAN_MCR_SOFTRST_SHIFT 25
#define CAN_MCR_WAKMSK_MASK 0x4000000u
#define CAN_MCR_WAKMSK_SHIFT 26
#define CAN_MCR_NOTRDY_MASK 0x8000000u
#define CAN_MCR_NOTRDY_SHIFT 27
#define CAN_MCR_HALT_MASK 0x10000000u
#define CAN_MCR_HALT_SHIFT 28
#define CAN_MCR_RFEN_MASK 0x20000000u
#define CAN_MCR_RFEN_SHIFT 29
#define CAN_MCR_FRZ_MASK 0x40000000u
#define CAN_MCR_FRZ_SHIFT 30
#define CAN_MCR_MDIS_MASK 0x80000000u
#define CAN_MCR_MDIS_SHIFT 31
/* CTRL1 Bit Fields */
#define CAN_CTRL1_PROPSEG_MASK 0x7u
#define CAN_CTRL1_PROPSEG_SHIFT 0
#define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PROPSEG_SHIFT))&CAN_CTRL1_PROPSEG_MASK)
#define CAN_CTRL1_LOM_MASK 0x8u
#define CAN_CTRL1_LOM_SHIFT 3
#define CAN_CTRL1_LBUF_MASK 0x10u
#define CAN_CTRL1_LBUF_SHIFT 4
#define CAN_CTRL1_TSYN_MASK 0x20u
#define CAN_CTRL1_TSYN_SHIFT 5
#define CAN_CTRL1_BOFFREC_MASK 0x40u
#define CAN_CTRL1_BOFFREC_SHIFT 6
#define CAN_CTRL1_SMP_MASK 0x80u
#define CAN_CTRL1_SMP_SHIFT 7
#define CAN_CTRL1_RWRNMSK_MASK 0x400u
#define CAN_CTRL1_RWRNMSK_SHIFT 10
#define CAN_CTRL1_TWRNMSK_MASK 0x800u
#define CAN_CTRL1_TWRNMSK_SHIFT 11
#define CAN_CTRL1_LPB_MASK 0x1000u
#define CAN_CTRL1_LPB_SHIFT 12
#define CAN_CTRL1_CLKSRC_MASK 0x2000u
#define CAN_CTRL1_CLKSRC_SHIFT 13
#define CAN_CTRL1_ERRMSK_MASK 0x4000u
#define CAN_CTRL1_ERRMSK_SHIFT 14
#define CAN_CTRL1_BOFFMSK_MASK 0x8000u
#define CAN_CTRL1_BOFFMSK_SHIFT 15
#define CAN_CTRL1_PSEG2_MASK 0x70000u
#define CAN_CTRL1_PSEG2_SHIFT 16
#define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG2_SHIFT))&CAN_CTRL1_PSEG2_MASK)
#define CAN_CTRL1_PSEG1_MASK 0x380000u
#define CAN_CTRL1_PSEG1_SHIFT 19
#define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG1_SHIFT))&CAN_CTRL1_PSEG1_MASK)
#define CAN_CTRL1_RJW_MASK 0xC00000u
#define CAN_CTRL1_RJW_SHIFT 22
#define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_RJW_SHIFT))&CAN_CTRL1_RJW_MASK)
#define CAN_CTRL1_PRESDIV_MASK 0xFF000000u
#define CAN_CTRL1_PRESDIV_SHIFT 24
#define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PRESDIV_SHIFT))&CAN_CTRL1_PRESDIV_MASK)
/* TIMER Bit Fields */
#define CAN_TIMER_TIMER_MASK 0xFFFFu
#define CAN_TIMER_TIMER_SHIFT 0
#define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x))<<CAN_TIMER_TIMER_SHIFT))&CAN_TIMER_TIMER_MASK)
/* RXMGMASK Bit Fields */
#define CAN_RXMGMASK_MG_MASK 0xFFFFFFFFu
#define CAN_RXMGMASK_MG_SHIFT 0
#define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXMGMASK_MG_SHIFT))&CAN_RXMGMASK_MG_MASK)
/* RX14MASK Bit Fields */
#define CAN_RX14MASK_RX14M_MASK 0xFFFFFFFFu
#define CAN_RX14MASK_RX14M_SHIFT 0
#define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x))<<CAN_RX14MASK_RX14M_SHIFT))&CAN_RX14MASK_RX14M_MASK)
/* RX15MASK Bit Fields */
#define CAN_RX15MASK_RX15M_MASK 0xFFFFFFFFu
#define CAN_RX15MASK_RX15M_SHIFT 0
#define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x))<<CAN_RX15MASK_RX15M_SHIFT))&CAN_RX15MASK_RX15M_MASK)
/* ECR Bit Fields */
#define CAN_ECR_TXERRCNT_MASK 0xFFu
#define CAN_ECR_TXERRCNT_SHIFT 0
#define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ECR_TXERRCNT_SHIFT))&CAN_ECR_TXERRCNT_MASK)
#define CAN_ECR_RXERRCNT_MASK 0xFF00u
#define CAN_ECR_RXERRCNT_SHIFT 8
#define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ECR_RXERRCNT_SHIFT))&CAN_ECR_RXERRCNT_MASK)
/* ESR1 Bit Fields */
#define CAN_ESR1_WAKINT_MASK 0x1u
#define CAN_ESR1_WAKINT_SHIFT 0
#define CAN_ESR1_ERRINT_MASK 0x2u
#define CAN_ESR1_ERRINT_SHIFT 1
#define CAN_ESR1_BOFFINT_MASK 0x4u
#define CAN_ESR1_BOFFINT_SHIFT 2
#define CAN_ESR1_RX_MASK 0x8u
#define CAN_ESR1_RX_SHIFT 3
#define CAN_ESR1_FLTCONF_MASK 0x30u
#define CAN_ESR1_FLTCONF_SHIFT 4
#define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_FLTCONF_SHIFT))&CAN_ESR1_FLTCONF_MASK)
#define CAN_ESR1_TX_MASK 0x40u
#define CAN_ESR1_TX_SHIFT 6
#define CAN_ESR1_IDLE_MASK 0x80u
#define CAN_ESR1_IDLE_SHIFT 7
#define CAN_ESR1_RXWRN_MASK 0x100u
#define CAN_ESR1_RXWRN_SHIFT 8
#define CAN_ESR1_TXWRN_MASK 0x200u
#define CAN_ESR1_TXWRN_SHIFT 9
#define CAN_ESR1_STFERR_MASK 0x400u
#define CAN_ESR1_STFERR_SHIFT 10
#define CAN_ESR1_FRMERR_MASK 0x800u
#define CAN_ESR1_FRMERR_SHIFT 11
#define CAN_ESR1_CRCERR_MASK 0x1000u
#define CAN_ESR1_CRCERR_SHIFT 12
#define CAN_ESR1_ACKERR_MASK 0x2000u
#define CAN_ESR1_ACKERR_SHIFT 13
#define CAN_ESR1_BIT0ERR_MASK 0x4000u
#define CAN_ESR1_BIT0ERR_SHIFT 14
#define CAN_ESR1_BIT1ERR_MASK 0x8000u
#define CAN_ESR1_BIT1ERR_SHIFT 15
#define CAN_ESR1_RWRNINT_MASK 0x10000u
#define CAN_ESR1_RWRNINT_SHIFT 16
#define CAN_ESR1_TWRNINT_MASK 0x20000u
#define CAN_ESR1_TWRNINT_SHIFT 17
#define CAN_ESR1_SYNCH_MASK 0x40000u
#define CAN_ESR1_SYNCH_SHIFT 18
/* IMASK1 Bit Fields */
#define CAN_IMASK1_BUFLM_MASK 0xFFFFFFFFu
#define CAN_IMASK1_BUFLM_SHIFT 0
#define CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x))<<CAN_IMASK1_BUFLM_SHIFT))&CAN_IMASK1_BUFLM_MASK)
/* IFLAG1 Bit Fields */
#define CAN_IFLAG1_BUF4TO0I_MASK 0x1Fu
#define CAN_IFLAG1_BUF4TO0I_SHIFT 0
#define CAN_IFLAG1_BUF4TO0I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF4TO0I_SHIFT))&CAN_IFLAG1_BUF4TO0I_MASK)
#define CAN_IFLAG1_BUF5I_MASK 0x20u
#define CAN_IFLAG1_BUF5I_SHIFT 5
#define CAN_IFLAG1_BUF6I_MASK 0x40u
#define CAN_IFLAG1_BUF6I_SHIFT 6
#define CAN_IFLAG1_BUF7I_MASK 0x80u
#define CAN_IFLAG1_BUF7I_SHIFT 7
#define CAN_IFLAG1_BUF31TO8I_MASK 0xFFFFFF00u
#define CAN_IFLAG1_BUF31TO8I_SHIFT 8
#define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF31TO8I_SHIFT))&CAN_IFLAG1_BUF31TO8I_MASK)
/* CTRL2 Bit Fields */
#define CAN_CTRL2_EACEN_MASK 0x10000u
#define CAN_CTRL2_EACEN_SHIFT 16
#define CAN_CTRL2_RRS_MASK 0x20000u
#define CAN_CTRL2_RRS_SHIFT 17
#define CAN_CTRL2_MRP_MASK 0x40000u
#define CAN_CTRL2_MRP_SHIFT 18
#define CAN_CTRL2_TASD_MASK 0xF80000u
#define CAN_CTRL2_TASD_SHIFT 19
#define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_TASD_SHIFT))&CAN_CTRL2_TASD_MASK)
#define CAN_CTRL2_RFFN_MASK 0xF000000u
#define CAN_CTRL2_RFFN_SHIFT 24
#define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_RFFN_SHIFT))&CAN_CTRL2_RFFN_MASK)
#define CAN_CTRL2_WRMFRZ_MASK 0x10000000u
#define CAN_CTRL2_WRMFRZ_SHIFT 28
/* ESR2 Bit Fields */
#define CAN_ESR2_IMB_MASK 0x2000u
#define CAN_ESR2_IMB_SHIFT 13
#define CAN_ESR2_VPS_MASK 0x4000u
#define CAN_ESR2_VPS_SHIFT 14
#define CAN_ESR2_LPTM_MASK 0x7F0000u
#define CAN_ESR2_LPTM_SHIFT 16
#define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_LPTM_SHIFT))&CAN_ESR2_LPTM_MASK)
/* CRCR Bit Fields */
#define CAN_CRCR_TXCRC_MASK 0x7FFFu
#define CAN_CRCR_TXCRC_SHIFT 0
#define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_TXCRC_SHIFT))&CAN_CRCR_TXCRC_MASK)
#define CAN_CRCR_MBCRC_MASK 0x7F0000u
#define CAN_CRCR_MBCRC_SHIFT 16
#define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_MBCRC_SHIFT))&CAN_CRCR_MBCRC_MASK)
/* RXFGMASK Bit Fields */
#define CAN_RXFGMASK_FGM_MASK 0xFFFFFFFFu
#define CAN_RXFGMASK_FGM_SHIFT 0
#define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXFGMASK_FGM_SHIFT))&CAN_RXFGMASK_FGM_MASK)
/* RXFIR Bit Fields */
#define CAN_RXFIR_IDHIT_MASK 0x1FFu
#define CAN_RXFIR_IDHIT_SHIFT 0
#define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXFIR_IDHIT_SHIFT))&CAN_RXFIR_IDHIT_MASK)
/* CS Bit Fields */
#define CAN_CS_TIME_STAMP_MASK 0xFFFFu
#define CAN_CS_TIME_STAMP_SHIFT 0
#define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_TIME_STAMP_SHIFT))&CAN_CS_TIME_STAMP_MASK)
#define CAN_CS_DLC_MASK 0xF0000u
#define CAN_CS_DLC_SHIFT 16
#define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_DLC_SHIFT))&CAN_CS_DLC_MASK)
#define CAN_CS_RTR_MASK 0x100000u
#define CAN_CS_RTR_SHIFT 20
#define CAN_CS_IDE_MASK 0x200000u
#define CAN_CS_IDE_SHIFT 21
#define CAN_CS_SRR_MASK 0x400000u
#define CAN_CS_SRR_SHIFT 22
#define CAN_CS_CODE_MASK 0xF000000u
#define CAN_CS_CODE_SHIFT 24
#define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_CODE_SHIFT))&CAN_CS_CODE_MASK)
/* ID Bit Fields */
#define CAN_ID_EXT_MASK 0x3FFFFu
#define CAN_ID_EXT_SHIFT 0
#define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_EXT_SHIFT))&CAN_ID_EXT_MASK)
#define CAN_ID_STD_MASK 0x1FFC0000u
#define CAN_ID_STD_SHIFT 18
#define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_STD_SHIFT))&CAN_ID_STD_MASK)
#define CAN_ID_PRIO_MASK 0xE0000000u
#define CAN_ID_PRIO_SHIFT 29
#define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_PRIO_SHIFT))&CAN_ID_PRIO_MASK)
/* WORD0 Bit Fields */
#define CAN_WORD0_DATA_BYTE_3_MASK 0xFFu
#define CAN_WORD0_DATA_BYTE_3_SHIFT 0
#define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_3_SHIFT))&CAN_WORD0_DATA_BYTE_3_MASK)
#define CAN_WORD0_DATA_BYTE_2_MASK 0xFF00u
#define CAN_WORD0_DATA_BYTE_2_SHIFT 8
#define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_2_SHIFT))&CAN_WORD0_DATA_BYTE_2_MASK)
#define CAN_WORD0_DATA_BYTE_1_MASK 0xFF0000u
#define CAN_WORD0_DATA_BYTE_1_SHIFT 16
#define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_1_SHIFT))&CAN_WORD0_DATA_BYTE_1_MASK)
#define CAN_WORD0_DATA_BYTE_0_MASK 0xFF000000u
#define CAN_WORD0_DATA_BYTE_0_SHIFT 24
#define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_0_SHIFT))&CAN_WORD0_DATA_BYTE_0_MASK)
/* WORD1 Bit Fields */
#define CAN_WORD1_DATA_BYTE_7_MASK 0xFFu
#define CAN_WORD1_DATA_BYTE_7_SHIFT 0
#define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_7_SHIFT))&CAN_WORD1_DATA_BYTE_7_MASK)
#define CAN_WORD1_DATA_BYTE_6_MASK 0xFF00u
#define CAN_WORD1_DATA_BYTE_6_SHIFT 8
#define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_6_SHIFT))&CAN_WORD1_DATA_BYTE_6_MASK)
#define CAN_WORD1_DATA_BYTE_5_MASK 0xFF0000u
#define CAN_WORD1_DATA_BYTE_5_SHIFT 16
#define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_5_SHIFT))&CAN_WORD1_DATA_BYTE_5_MASK)
#define CAN_WORD1_DATA_BYTE_4_MASK 0xFF000000u
#define CAN_WORD1_DATA_BYTE_4_SHIFT 24
#define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_4_SHIFT))&CAN_WORD1_DATA_BYTE_4_MASK)
/* RXIMR Bit Fields */
#define CAN_RXIMR_MI_MASK 0xFFFFFFFFu
#define CAN_RXIMR_MI_SHIFT 0
#define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXIMR_MI_SHIFT))&CAN_RXIMR_MI_MASK)
/*!
* @}
*/ /* end of group CAN_Register_Masks */
/* CAN - Peripheral instance base addresses */
/** Peripheral CAN0 base address */
#define CAN0_BASE (0x40024000u)
/** Peripheral CAN0 base pointer */
#define CAN0 ((CAN_Type *)CAN0_BASE)
#define CAN0_BASE_PTR (CAN0)
/** Peripheral CAN1 base address */
#define CAN1_BASE (0x400A4000u)
/** Peripheral CAN1 base pointer */
#define CAN1 ((CAN_Type *)CAN1_BASE)
#define CAN1_BASE_PTR (CAN1)
/** Array initializer of CAN peripheral base addresses */
#define CAN_BASE_ADDRS { CAN0_BASE, CAN1_BASE }
/** Array initializer of CAN peripheral base pointers */
#define CAN_BASE_PTRS { CAN0, CAN1 }
/** Interrupt vectors for the CAN peripheral type */
#define CAN_Rx_Warning_IRQS { CAN0_Rx_Warning_IRQn, CAN1_Rx_Warning_IRQn }
#define CAN_Tx_Warning_IRQS { CAN0_Tx_Warning_IRQn, CAN1_Tx_Warning_IRQn }
#define CAN_Wake_Up_IRQS { CAN0_Wake_Up_IRQn, CAN1_Wake_Up_IRQn }
#define CAN_Error_IRQS { CAN0_Error_IRQn, CAN1_Error_IRQn }
#define CAN_Bus_Off_IRQS { CAN0_Bus_Off_IRQn, CAN1_Bus_Off_IRQn }
#define CAN_ORed_Message_buffer_IRQS { CAN0_ORed_Message_buffer_IRQn, CAN1_ORed_Message_buffer_IRQn }
/* ----------------------------------------------------------------------------
-- CAN - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup CAN_Register_Accessor_Macros CAN - Register accessor macros
* @{
*/
/* CAN - Register instance definitions */
/* CAN0 */
#define CAN0_MCR CAN_MCR_REG(CAN0)
#define CAN0_CTRL1 CAN_CTRL1_REG(CAN0)
#define CAN0_TIMER CAN_TIMER_REG(CAN0)
#define CAN0_RXMGMASK CAN_RXMGMASK_REG(CAN0)
#define CAN0_RX14MASK CAN_RX14MASK_REG(CAN0)
#define CAN0_RX15MASK CAN_RX15MASK_REG(CAN0)
#define CAN0_ECR CAN_ECR_REG(CAN0)
#define CAN0_ESR1 CAN_ESR1_REG(CAN0)
#define CAN0_IMASK1 CAN_IMASK1_REG(CAN0)
#define CAN0_IFLAG1 CAN_IFLAG1_REG(CAN0)
#define CAN0_CTRL2 CAN_CTRL2_REG(CAN0)
#define CAN0_ESR2 CAN_ESR2_REG(CAN0)
#define CAN0_CRCR CAN_CRCR_REG(CAN0)
#define CAN0_RXFGMASK CAN_RXFGMASK_REG(CAN0)
#define CAN0_RXFIR CAN_RXFIR_REG(CAN0)
#define CAN0_CS0 CAN_CS_REG(CAN0,0)
#define CAN0_ID0 CAN_ID_REG(CAN0,0)
#define CAN0_WORD00 CAN_WORD0_REG(CAN0,0)
#define CAN0_WORD10 CAN_WORD1_REG(CAN0,0)
#define CAN0_CS1 CAN_CS_REG(CAN0,1)
#define CAN0_ID1 CAN_ID_REG(CAN0,1)
#define CAN0_WORD01 CAN_WORD0_REG(CAN0,1)
#define CAN0_WORD11 CAN_WORD1_REG(CAN0,1)
#define CAN0_CS2 CAN_CS_REG(CAN0,2)
#define CAN0_ID2 CAN_ID_REG(CAN0,2)
#define CAN0_WORD02 CAN_WORD0_REG(CAN0,2)
#define CAN0_WORD12 CAN_WORD1_REG(CAN0,2)
#define CAN0_CS3 CAN_CS_REG(CAN0,3)
#define CAN0_ID3 CAN_ID_REG(CAN0,3)
#define CAN0_WORD03 CAN_WORD0_REG(CAN0,3)
#define CAN0_WORD13 CAN_WORD1_REG(CAN0,3)
#define CAN0_CS4 CAN_CS_REG(CAN0,4)
#define CAN0_ID4 CAN_ID_REG(CAN0,4)
#define CAN0_WORD04 CAN_WORD0_REG(CAN0,4)
#define CAN0_WORD14 CAN_WORD1_REG(CAN0,4)
#define CAN0_CS5 CAN_CS_REG(CAN0,5)
#define CAN0_ID5 CAN_ID_REG(CAN0,5)
#define CAN0_WORD05 CAN_WORD0_REG(CAN0,5)
#define CAN0_WORD15 CAN_WORD1_REG(CAN0,5)
#define CAN0_CS6 CAN_CS_REG(CAN0,6)
#define CAN0_ID6 CAN_ID_REG(CAN0,6)
#define CAN0_WORD06 CAN_WORD0_REG(CAN0,6)
#define CAN0_WORD16 CAN_WORD1_REG(CAN0,6)
#define CAN0_CS7 CAN_CS_REG(CAN0,7)
#define CAN0_ID7 CAN_ID_REG(CAN0,7)
#define CAN0_WORD07 CAN_WORD0_REG(CAN0,7)
#define CAN0_WORD17 CAN_WORD1_REG(CAN0,7)
#define CAN0_CS8 CAN_CS_REG(CAN0,8)
#define CAN0_ID8 CAN_ID_REG(CAN0,8)
#define CAN0_WORD08 CAN_WORD0_REG(CAN0,8)
#define CAN0_WORD18 CAN_WORD1_REG(CAN0,8)
#define CAN0_CS9 CAN_CS_REG(CAN0,9)
#define CAN0_ID9 CAN_ID_REG(CAN0,9)
#define CAN0_WORD09 CAN_WORD0_REG(CAN0,9)
#define CAN0_WORD19 CAN_WORD1_REG(CAN0,9)
#define CAN0_CS10 CAN_CS_REG(CAN0,10)
#define CAN0_ID10 CAN_ID_REG(CAN0,10)
#define CAN0_WORD010 CAN_WORD0_REG(CAN0,10)
#define CAN0_WORD110 CAN_WORD1_REG(CAN0,10)
#define CAN0_CS11 CAN_CS_REG(CAN0,11)
#define CAN0_ID11 CAN_ID_REG(CAN0,11)
#define CAN0_WORD011 CAN_WORD0_REG(CAN0,11)
#define CAN0_WORD111 CAN_WORD1_REG(CAN0,11)
#define CAN0_CS12 CAN_CS_REG(CAN0,12)
#define CAN0_ID12 CAN_ID_REG(CAN0,12)
#define CAN0_WORD012 CAN_WORD0_REG(CAN0,12)
#define CAN0_WORD112 CAN_WORD1_REG(CAN0,12)
#define CAN0_CS13 CAN_CS_REG(CAN0,13)
#define CAN0_ID13 CAN_ID_REG(CAN0,13)
#define CAN0_WORD013 CAN_WORD0_REG(CAN0,13)
#define CAN0_WORD113 CAN_WORD1_REG(CAN0,13)
#define CAN0_CS14 CAN_CS_REG(CAN0,14)
#define CAN0_ID14 CAN_ID_REG(CAN0,14)
#define CAN0_WORD014 CAN_WORD0_REG(CAN0,14)
#define CAN0_WORD114 CAN_WORD1_REG(CAN0,14)
#define CAN0_CS15 CAN_CS_REG(CAN0,15)
#define CAN0_ID15 CAN_ID_REG(CAN0,15)
#define CAN0_WORD015 CAN_WORD0_REG(CAN0,15)
#define CAN0_WORD115 CAN_WORD1_REG(CAN0,15)
#define CAN0_RXIMR0 CAN_RXIMR_REG(CAN0,0)
#define CAN0_RXIMR1 CAN_RXIMR_REG(CAN0,1)
#define CAN0_RXIMR2 CAN_RXIMR_REG(CAN0,2)
#define CAN0_RXIMR3 CAN_RXIMR_REG(CAN0,3)
#define CAN0_RXIMR4 CAN_RXIMR_REG(CAN0,4)
#define CAN0_RXIMR5 CAN_RXIMR_REG(CAN0,5)
#define CAN0_RXIMR6 CAN_RXIMR_REG(CAN0,6)
#define CAN0_RXIMR7 CAN_RXIMR_REG(CAN0,7)
#define CAN0_RXIMR8 CAN_RXIMR_REG(CAN0,8)
#define CAN0_RXIMR9 CAN_RXIMR_REG(CAN0,9)
#define CAN0_RXIMR10 CAN_RXIMR_REG(CAN0,10)
#define CAN0_RXIMR11 CAN_RXIMR_REG(CAN0,11)
#define CAN0_RXIMR12 CAN_RXIMR_REG(CAN0,12)
#define CAN0_RXIMR13 CAN_RXIMR_REG(CAN0,13)
#define CAN0_RXIMR14 CAN_RXIMR_REG(CAN0,14)
#define CAN0_RXIMR15 CAN_RXIMR_REG(CAN0,15)
/* CAN1 */
#define CAN1_MCR CAN_MCR_REG(CAN1)
#define CAN1_CTRL1 CAN_CTRL1_REG(CAN1)
#define CAN1_TIMER CAN_TIMER_REG(CAN1)
#define CAN1_RXMGMASK CAN_RXMGMASK_REG(CAN1)
#define CAN1_RX14MASK CAN_RX14MASK_REG(CAN1)
#define CAN1_RX15MASK CAN_RX15MASK_REG(CAN1)
#define CAN1_ECR CAN_ECR_REG(CAN1)
#define CAN1_ESR1 CAN_ESR1_REG(CAN1)
#define CAN1_IMASK1 CAN_IMASK1_REG(CAN1)
#define CAN1_IFLAG1 CAN_IFLAG1_REG(CAN1)
#define CAN1_CTRL2 CAN_CTRL2_REG(CAN1)
#define CAN1_ESR2 CAN_ESR2_REG(CAN1)
#define CAN1_CRCR CAN_CRCR_REG(CAN1)
#define CAN1_RXFGMASK CAN_RXFGMASK_REG(CAN1)
#define CAN1_RXFIR CAN_RXFIR_REG(CAN1)
#define CAN1_CS0 CAN_CS_REG(CAN1,0)
#define CAN1_ID0 CAN_ID_REG(CAN1,0)
#define CAN1_WORD00 CAN_WORD0_REG(CAN1,0)
#define CAN1_WORD10 CAN_WORD1_REG(CAN1,0)
#define CAN1_CS1 CAN_CS_REG(CAN1,1)
#define CAN1_ID1 CAN_ID_REG(CAN1,1)
#define CAN1_WORD01 CAN_WORD0_REG(CAN1,1)
#define CAN1_WORD11 CAN_WORD1_REG(CAN1,1)
#define CAN1_CS2 CAN_CS_REG(CAN1,2)
#define CAN1_ID2 CAN_ID_REG(CAN1,2)
#define CAN1_WORD02 CAN_WORD0_REG(CAN1,2)
#define CAN1_WORD12 CAN_WORD1_REG(CAN1,2)
#define CAN1_CS3 CAN_CS_REG(CAN1,3)
#define CAN1_ID3 CAN_ID_REG(CAN1,3)
#define CAN1_WORD03 CAN_WORD0_REG(CAN1,3)
#define CAN1_WORD13 CAN_WORD1_REG(CAN1,3)
#define CAN1_CS4 CAN_CS_REG(CAN1,4)
#define CAN1_ID4 CAN_ID_REG(CAN1,4)
#define CAN1_WORD04 CAN_WORD0_REG(CAN1,4)
#define CAN1_WORD14 CAN_WORD1_REG(CAN1,4)
#define CAN1_CS5 CAN_CS_REG(CAN1,5)
#define CAN1_ID5 CAN_ID_REG(CAN1,5)
#define CAN1_WORD05 CAN_WORD0_REG(CAN1,5)
#define CAN1_WORD15 CAN_WORD1_REG(CAN1,5)
#define CAN1_CS6 CAN_CS_REG(CAN1,6)
#define CAN1_ID6 CAN_ID_REG(CAN1,6)
#define CAN1_WORD06 CAN_WORD0_REG(CAN1,6)
#define CAN1_WORD16 CAN_WORD1_REG(CAN1,6)
#define CAN1_CS7 CAN_CS_REG(CAN1,7)
#define CAN1_ID7 CAN_ID_REG(CAN1,7)
#define CAN1_WORD07 CAN_WORD0_REG(CAN1,7)
#define CAN1_WORD17 CAN_WORD1_REG(CAN1,7)
#define CAN1_CS8 CAN_CS_REG(CAN1,8)
#define CAN1_ID8 CAN_ID_REG(CAN1,8)
#define CAN1_WORD08 CAN_WORD0_REG(CAN1,8)
#define CAN1_WORD18 CAN_WORD1_REG(CAN1,8)
#define CAN1_CS9 CAN_CS_REG(CAN1,9)
#define CAN1_ID9 CAN_ID_REG(CAN1,9)
#define CAN1_WORD09 CAN_WORD0_REG(CAN1,9)
#define CAN1_WORD19 CAN_WORD1_REG(CAN1,9)
#define CAN1_CS10 CAN_CS_REG(CAN1,10)
#define CAN1_ID10 CAN_ID_REG(CAN1,10)
#define CAN1_WORD010 CAN_WORD0_REG(CAN1,10)
#define CAN1_WORD110 CAN_WORD1_REG(CAN1,10)
#define CAN1_CS11 CAN_CS_REG(CAN1,11)
#define CAN1_ID11 CAN_ID_REG(CAN1,11)
#define CAN1_WORD011 CAN_WORD0_REG(CAN1,11)
#define CAN1_WORD111 CAN_WORD1_REG(CAN1,11)
#define CAN1_CS12 CAN_CS_REG(CAN1,12)
#define CAN1_ID12 CAN_ID_REG(CAN1,12)
#define CAN1_WORD012 CAN_WORD0_REG(CAN1,12)
#define CAN1_WORD112 CAN_WORD1_REG(CAN1,12)
#define CAN1_CS13 CAN_CS_REG(CAN1,13)
#define CAN1_ID13 CAN_ID_REG(CAN1,13)
#define CAN1_WORD013 CAN_WORD0_REG(CAN1,13)
#define CAN1_WORD113 CAN_WORD1_REG(CAN1,13)
#define CAN1_CS14 CAN_CS_REG(CAN1,14)
#define CAN1_ID14 CAN_ID_REG(CAN1,14)
#define CAN1_WORD014 CAN_WORD0_REG(CAN1,14)
#define CAN1_WORD114 CAN_WORD1_REG(CAN1,14)
#define CAN1_CS15 CAN_CS_REG(CAN1,15)
#define CAN1_ID15 CAN_ID_REG(CAN1,15)
#define CAN1_WORD015 CAN_WORD0_REG(CAN1,15)
#define CAN1_WORD115 CAN_WORD1_REG(CAN1,15)
#define CAN1_RXIMR0 CAN_RXIMR_REG(CAN1,0)
#define CAN1_RXIMR1 CAN_RXIMR_REG(CAN1,1)
#define CAN1_RXIMR2 CAN_RXIMR_REG(CAN1,2)
#define CAN1_RXIMR3 CAN_RXIMR_REG(CAN1,3)
#define CAN1_RXIMR4 CAN_RXIMR_REG(CAN1,4)
#define CAN1_RXIMR5 CAN_RXIMR_REG(CAN1,5)
#define CAN1_RXIMR6 CAN_RXIMR_REG(CAN1,6)
#define CAN1_RXIMR7 CAN_RXIMR_REG(CAN1,7)
#define CAN1_RXIMR8 CAN_RXIMR_REG(CAN1,8)
#define CAN1_RXIMR9 CAN_RXIMR_REG(CAN1,9)
#define CAN1_RXIMR10 CAN_RXIMR_REG(CAN1,10)
#define CAN1_RXIMR11 CAN_RXIMR_REG(CAN1,11)
#define CAN1_RXIMR12 CAN_RXIMR_REG(CAN1,12)
#define CAN1_RXIMR13 CAN_RXIMR_REG(CAN1,13)
#define CAN1_RXIMR14 CAN_RXIMR_REG(CAN1,14)
#define CAN1_RXIMR15 CAN_RXIMR_REG(CAN1,15)
/* CAN - Register array accessors */
#define CAN0_CS(index) CAN_CS_REG(CAN0,index)
#define CAN1_CS(index) CAN_CS_REG(CAN1,index)
#define CAN0_ID(index) CAN_ID_REG(CAN0,index)
#define CAN1_ID(index) CAN_ID_REG(CAN1,index)
#define CAN0_WORD0(index) CAN_WORD0_REG(CAN0,index)
#define CAN1_WORD0(index) CAN_WORD0_REG(CAN1,index)
#define CAN0_WORD1(index) CAN_WORD1_REG(CAN0,index)
#define CAN1_WORD1(index) CAN_WORD1_REG(CAN1,index)
#define CAN0_RXIMR(index) CAN_RXIMR_REG(CAN0,index)
#define CAN1_RXIMR(index) CAN_RXIMR_REG(CAN1,index)
/*!
* @}
*/ /* end of group CAN_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group CAN_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- CAU Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup CAU_Peripheral_Access_Layer CAU Peripheral Access Layer
* @{
*/
/** CAU - Register Layout Typedef */
typedef struct {
__O uint32_t DIRECT[16]; /**< Direct access register 0..Direct access register 15, array offset: 0x0, array step: 0x4 */
uint8_t RESERVED_0[2048];
__O uint32_t LDR_CASR; /**< Status register - Load Register command, offset: 0x840 */
__O uint32_t LDR_CAA; /**< Accumulator register - Load Register command, offset: 0x844 */
__O uint32_t LDR_CA[9]; /**< General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command, array offset: 0x848, array step: 0x4 */
uint8_t RESERVED_1[20];
__I uint32_t STR_CASR; /**< Status register - Store Register command, offset: 0x880 */
__I uint32_t STR_CAA; /**< Accumulator register - Store Register command, offset: 0x884 */
__I uint32_t STR_CA[9]; /**< General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command, array offset: 0x888, array step: 0x4 */
uint8_t RESERVED_2[20];
__O uint32_t ADR_CASR; /**< Status register - Add Register command, offset: 0x8C0 */
__O uint32_t ADR_CAA; /**< Accumulator register - Add to register command, offset: 0x8C4 */
__O uint32_t ADR_CA[9]; /**< General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command, array offset: 0x8C8, array step: 0x4 */
uint8_t RESERVED_3[20];
__O uint32_t RADR_CASR; /**< Status register - Reverse and Add to Register command, offset: 0x900 */
__O uint32_t RADR_CAA; /**< Accumulator register - Reverse and Add to Register command, offset: 0x904 */
__O uint32_t RADR_CA[9]; /**< General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command, array offset: 0x908, array step: 0x4 */
uint8_t RESERVED_4[84];
__O uint32_t XOR_CASR; /**< Status register - Exclusive Or command, offset: 0x980 */
__O uint32_t XOR_CAA; /**< Accumulator register - Exclusive Or command, offset: 0x984 */
__O uint32_t XOR_CA[9]; /**< General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command, array offset: 0x988, array step: 0x4 */
uint8_t RESERVED_5[20];
__O uint32_t ROTL_CASR; /**< Status register - Rotate Left command, offset: 0x9C0 */
__O uint32_t ROTL_CAA; /**< Accumulator register - Rotate Left command, offset: 0x9C4 */
__O uint32_t ROTL_CA[9]; /**< General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command, array offset: 0x9C8, array step: 0x4 */
uint8_t RESERVED_6[276];
__O uint32_t AESC_CASR; /**< Status register - AES Column Operation command, offset: 0xB00 */
__O uint32_t AESC_CAA; /**< Accumulator register - AES Column Operation command, offset: 0xB04 */
__O uint32_t AESC_CA[9]; /**< General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command, array offset: 0xB08, array step: 0x4 */
uint8_t RESERVED_7[20];
__O uint32_t AESIC_CASR; /**< Status register - AES Inverse Column Operation command, offset: 0xB40 */
__O uint32_t AESIC_CAA; /**< Accumulator register - AES Inverse Column Operation command, offset: 0xB44 */
__O uint32_t AESIC_CA[9]; /**< General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command, array offset: 0xB48, array step: 0x4 */
} CAU_Type, *CAU_MemMapPtr;
/* ----------------------------------------------------------------------------
-- CAU - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup CAU_Register_Accessor_Macros CAU - Register accessor macros
* @{
*/
/* CAU - Register accessors */
#define CAU_DIRECT_REG(base,index) ((base)->DIRECT[index])
#define CAU_LDR_CASR_REG(base) ((base)->LDR_CASR)
#define CAU_LDR_CAA_REG(base) ((base)->LDR_CAA)
#define CAU_LDR_CA_REG(base,index) ((base)->LDR_CA[index])
#define CAU_STR_CASR_REG(base) ((base)->STR_CASR)
#define CAU_STR_CAA_REG(base) ((base)->STR_CAA)
#define CAU_STR_CA_REG(base,index) ((base)->STR_CA[index])
#define CAU_ADR_CASR_REG(base) ((base)->ADR_CASR)
#define CAU_ADR_CAA_REG(base) ((base)->ADR_CAA)
#define CAU_ADR_CA_REG(base,index) ((base)->ADR_CA[index])
#define CAU_RADR_CASR_REG(base) ((base)->RADR_CASR)
#define CAU_RADR_CAA_REG(base) ((base)->RADR_CAA)
#define CAU_RADR_CA_REG(base,index) ((base)->RADR_CA[index])
#define CAU_XOR_CASR_REG(base) ((base)->XOR_CASR)
#define CAU_XOR_CAA_REG(base) ((base)->XOR_CAA)
#define CAU_XOR_CA_REG(base,index) ((base)->XOR_CA[index])
#define CAU_ROTL_CASR_REG(base) ((base)->ROTL_CASR)
#define CAU_ROTL_CAA_REG(base) ((base)->ROTL_CAA)
#define CAU_ROTL_CA_REG(base,index) ((base)->ROTL_CA[index])
#define CAU_AESC_CASR_REG(base) ((base)->AESC_CASR)
#define CAU_AESC_CAA_REG(base) ((base)->AESC_CAA)