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/*
** ###################################################################
** Processors: MK60DN512ZVLL10
** MK60DX256ZVLL10
** MK60DN256ZVLL10
** MK60DN512ZVLQ10
** MK60DN256ZVLQ10
** MK60DX256ZVLQ10
** MK60DN512ZVMC10
** MK60DN256ZVMC10
** MK60DX256ZVMC10
** MK60DN512ZVMD10
** MK60DX256ZVMD10
** MK60DN256ZVMD10
**
** Compilers: ARM Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
**
** Reference manual: K60P144M100SF2RM, Rev. 5, 8 May 2011
** Version: rev. 1.2, 2011-09-08
**
** Abstract:
** CMSIS Peripheral Access Layer for MK60DZ10
**
** Copyright: 1997 - 2011 Freescale Semiconductor, Inc. All Rights Reserved.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** Revisions:
** - rev. 1.0 (2011-06-10)
** Initial version.
** Changes with respect to the previous MK60NxxxMD100 header file:
** RTC - CCR register removed. Replaced by IER register.
** CRC - added CTRLHU register for 8-bit access to the CTRL register.
** FB - bit FB_CSCR_EXALE renamed to FB_CSCR_EXTS.
** SIM - bit group FSIZE in SIM_FCFG1 split into groups PFSIZE and NVMSIZE.
** I2S - bit SSIEN in I2S_CR register renamed to I2SEN.
** SDHC - bit VOLTSEL in SDHC_VENDOR register removed.
** - rev. 1.1 (2011-06-29)
** Order of declarations changed.
** - rev. 1.2 (2011-09-08)
** Cortex_Core_Configuration extended with additional parameters.
** Gap between end of interrupt vector table and flash configuration field filled by default ISR.
** - rev. 1.2-jg (2015-05-18)
** Added BITBAND_REG32, BITBAND_REG16, BITBAND_REG8, BITBAND_REGADDR macros from MK60D10.h.
** Removed BITBAND_REG macro.
**
** ###################################################################
*/
/**
* @file MK60DZ10.h
* @version 1.2-jg
* @date 2015-05-18
* @brief CMSIS Peripheral Access Layer for MK60DZ10
*
* CMSIS Peripheral Access Layer for MK60DZ10
*/
#ifdef __cplusplus
extern "C"
{
#endif
#if !defined(MK60DZ10_H_)
#define MK60DZ10_H_ /**< Symbol preventing repeated inclusion */
/** Memory map version 1.2 */
#define MCU_MEM_MAP_VERSION 0x0102u
/**
* @brief Macro to calculate address of an aliased word in the peripheral
* bitband area for a peripheral register and bit (bit band region 0x40000000 to
* 0x400FFFFF).
* @param Reg Register to access.
* @param Bit Bit number to access.
* @return Address of the aliased word in the peripheral bitband area.
*/
#define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))
/**
* @brief Macro to access a single bit of a peripheral register (bit band region
* 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
* be used for peripherals with 32bit access allowed.
* @param Reg Register to access.
* @param Bit Bit number to access.
* @return Value of the targeted bit in the bit band region.
*/
#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
/**
* @brief Macro to access a single bit of a peripheral register (bit band region
* 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
* be used for peripherals with 16bit access allowed.
* @param Reg Register to access.
* @param Bit Bit number to access.
* @return Value of the targeted bit in the bit band region.
*/
#define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
/**
* @brief Macro to access a single bit of a peripheral register (bit band region
* 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
* be used for peripherals with 8bit access allowed.
* @param Reg Register to access.
* @param Bit Bit number to access.
* @return Value of the targeted bit in the bit band region.
*/
#define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
/* ----------------------------------------------------------------------------
-- Interrupt vector numbers
---------------------------------------------------------------------------- */
/**
* @addtogroup Interrupt_vector_numbers Interrupt vector numbers
* @{
*/
/** Interrupt Number Definitions */
typedef enum IRQn {
/* Core interrupts */
NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
/* Device specific interrupts */
DMA0_IRQn = 0, /**< DMA Channel 0 Transfer Complete */
DMA1_IRQn = 1, /**< DMA Channel 1 Transfer Complete */
DMA2_IRQn = 2, /**< DMA Channel 2 Transfer Complete */
DMA3_IRQn = 3, /**< DMA Channel 3 Transfer Complete */
DMA4_IRQn = 4, /**< DMA Channel 4 Transfer Complete */
DMA5_IRQn = 5, /**< DMA Channel 5 Transfer Complete */
DMA6_IRQn = 6, /**< DMA Channel 6 Transfer Complete */
DMA7_IRQn = 7, /**< DMA Channel 7 Transfer Complete */
DMA8_IRQn = 8, /**< DMA Channel 8 Transfer Complete */
DMA9_IRQn = 9, /**< DMA Channel 9 Transfer Complete */
DMA10_IRQn = 10, /**< DMA Channel 10 Transfer Complete */
DMA11_IRQn = 11, /**< DMA Channel 11 Transfer Complete */
DMA12_IRQn = 12, /**< DMA Channel 12 Transfer Complete */
DMA13_IRQn = 13, /**< DMA Channel 13 Transfer Complete */
DMA14_IRQn = 14, /**< DMA Channel 14 Transfer Complete */
DMA15_IRQn = 15, /**< DMA Channel 15 Transfer Complete */
DMA_Error_IRQn = 16, /**< DMA Error Interrupt */
MCM_IRQn = 17, /**< Normal Interrupt */
FTFL_IRQn = 18, /**< FTFL Interrupt */
Read_Collision_IRQn = 19, /**< Read Collision Interrupt */
LVD_LVW_IRQn = 20, /**< Low Voltage Detect, Low Voltage Warning */
LLW_IRQn = 21, /**< Low Leakage Wakeup */
Watchdog_IRQn = 22, /**< WDOG Interrupt */
RNG_IRQn = 23, /**< RNGB Interrupt */
I2C0_IRQn = 24, /**< I2C0 interrupt */
I2C1_IRQn = 25, /**< I2C1 interrupt */
SPI0_IRQn = 26, /**< SPI0 Interrupt */
SPI1_IRQn = 27, /**< SPI1 Interrupt */
SPI2_IRQn = 28, /**< SPI2 Interrupt */
CAN0_ORed_Message_buffer_IRQn = 29, /**< CAN0 OR'd Message Buffers Interrupt */
CAN0_Bus_Off_IRQn = 30, /**< CAN0 Bus Off Interrupt */
CAN0_Error_IRQn = 31, /**< CAN0 Error Interrupt */
CAN0_Tx_Warning_IRQn = 32, /**< CAN0 Tx Warning Interrupt */
CAN0_Rx_Warning_IRQn = 33, /**< CAN0 Rx Warning Interrupt */
CAN0_Wake_Up_IRQn = 34, /**< CAN0 Wake Up Interrupt */
Reserved51_IRQn = 35, /**< Reserved interrupt 51 */
Reserved52_IRQn = 36, /**< Reserved interrupt 52 */
CAN1_ORed_Message_buffer_IRQn = 37, /**< CAN1 OR'd Message Buffers Interrupt */
CAN1_Bus_Off_IRQn = 38, /**< CAN1 Bus Off Interrupt */
CAN1_Error_IRQn = 39, /**< CAN1 Error Interrupt */
CAN1_Tx_Warning_IRQn = 40, /**< CAN1 Tx Warning Interrupt */
CAN1_Rx_Warning_IRQn = 41, /**< CAN1 Rx Warning Interrupt */
CAN1_Wake_Up_IRQn = 42, /**< CAN1 Wake Up Interrupt */
Reserved59_IRQn = 43, /**< Reserved interrupt 59 */
Reserved60_IRQn = 44, /**< Reserved interrupt 60 */
UART0_RX_TX_IRQn = 45, /**< UART0 Receive/Transmit interrupt */
UART0_ERR_IRQn = 46, /**< UART0 Error interrupt */
UART1_RX_TX_IRQn = 47, /**< UART1 Receive/Transmit interrupt */
UART1_ERR_IRQn = 48, /**< UART1 Error interrupt */
UART2_RX_TX_IRQn = 49, /**< UART2 Receive/Transmit interrupt */
UART2_ERR_IRQn = 50, /**< UART2 Error interrupt */
UART3_RX_TX_IRQn = 51, /**< UART3 Receive/Transmit interrupt */
UART3_ERR_IRQn = 52, /**< UART3 Error interrupt */
UART4_RX_TX_IRQn = 53, /**< UART4 Receive/Transmit interrupt */
UART4_ERR_IRQn = 54, /**< UART4 Error interrupt */
UART5_RX_TX_IRQn = 55, /**< UART5 Receive/Transmit interrupt */
UART5_ERR_IRQn = 56, /**< UART5 Error interrupt */
ADC0_IRQn = 57, /**< ADC0 interrupt */
ADC1_IRQn = 58, /**< ADC1 interrupt */
CMP0_IRQn = 59, /**< CMP0 interrupt */
CMP1_IRQn = 60, /**< CMP1 interrupt */
CMP2_IRQn = 61, /**< CMP2 interrupt */
FTM0_IRQn = 62, /**< FTM0 fault, overflow and channels interrupt */
FTM1_IRQn = 63, /**< FTM1 fault, overflow and channels interrupt */
FTM2_IRQn = 64, /**< FTM2 fault, overflow and channels interrupt */
CMT_IRQn = 65, /**< CMT interrupt */
RTC_IRQn = 66, /**< RTC interrupt */
Reserved83_IRQn = 67, /**< Reserved interrupt 83 */
PIT0_IRQn = 68, /**< PIT timer channel 0 interrupt */
PIT1_IRQn = 69, /**< PIT timer channel 1 interrupt */
PIT2_IRQn = 70, /**< PIT timer channel 2 interrupt */
PIT3_IRQn = 71, /**< PIT timer channel 3 interrupt */
PDB0_IRQn = 72, /**< PDB0 Interrupt */
USB0_IRQn = 73, /**< USB0 interrupt */
USBDCD_IRQn = 74, /**< USBDCD Interrupt */
ENET_1588_Timer_IRQn = 75, /**< Ethernet MAC IEEE 1588 Timer Interrupt */
ENET_Transmit_IRQn = 76, /**< Ethernet MAC Transmit Interrupt */
ENET_Receive_IRQn = 77, /**< Ethernet MAC Receive Interrupt */
ENET_Error_IRQn = 78, /**< Ethernet MAC Error and miscelaneous Interrupt */
I2S0_IRQn = 79, /**< I2S0 Interrupt */
SDHC_IRQn = 80, /**< SDHC Interrupt */
DAC0_IRQn = 81, /**< DAC0 interrupt */
DAC1_IRQn = 82, /**< DAC1 interrupt */
TSI0_IRQn = 83, /**< TSI0 Interrupt */
MCG_IRQn = 84, /**< MCG Interrupt */
LPTimer_IRQn = 85, /**< LPTimer interrupt */
Reserved102_IRQn = 86, /**< Reserved interrupt 102 */
PORTA_IRQn = 87, /**< Port A interrupt */
PORTB_IRQn = 88, /**< Port B interrupt */
PORTC_IRQn = 89, /**< Port C interrupt */
PORTD_IRQn = 90, /**< Port D interrupt */
PORTE_IRQn = 91, /**< Port E interrupt */
Reserved108_IRQn = 92, /**< Reserved interrupt 108 */
Reserved109_IRQn = 93, /**< Reserved interrupt 109 */
Reserved110_IRQn = 94, /**< Reserved interrupt 110 */
Reserved111_IRQn = 95, /**< Reserved interrupt 111 */
Reserved112_IRQn = 96, /**< Reserved interrupt 112 */
Reserved113_IRQn = 97, /**< Reserved interrupt 113 */
Reserved114_IRQn = 98, /**< Reserved interrupt 114 */
Reserved115_IRQn = 99, /**< Reserved interrupt 115 */
Reserved116_IRQn = 100, /**< Reserved interrupt 116 */
Reserved117_IRQn = 101, /**< Reserved interrupt 117 */
Reserved118_IRQn = 102, /**< Reserved interrupt 118 */
Reserved119_IRQn = 103 /**< Reserved interrupt 119 */
} IRQn_Type;
/**
* @}
*/ /* end of group Interrupt_vector_numbers */
/* ----------------------------------------------------------------------------
-- Configuration of the Cortex-M4 Processor and Core Peripherals
---------------------------------------------------------------------------- */
/**
* @addtogroup Cortex_Core_Configuration Configuration of the Cortex-M4 Processor and Core Peripherals
* @{
*/
#define __CM4_REV 0x0001 /**< Core revision r0p1 */
#define __MPU_PRESENT 0 /**< MPU present or not */
#define __NVIC_PRIO_BITS 4 /**< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 0 /**< FPU present or not */
#include "core_cm4.h" /* Core Peripheral Access Layer */
/**
* @}
*/ /* end of group Cortex_Core_Configuration */
/* ----------------------------------------------------------------------------
-- Device Peripheral Access Layer
---------------------------------------------------------------------------- */
/**
* @addtogroup Peripheral_access_layer Device Peripheral Access Layer
* @{
*/
/*
** Start of section using anonymous unions
*/
#if defined(__ARMCC_VERSION)
#pragma push
#pragma anon_unions
#elif defined(__CWCC__)
#pragma push
#pragma cpp_extensions on
#elif defined(__GNUC__)
/* anonymous unions are enabled by default */
#elif defined(__IAR_SYSTEMS_ICC__)
#pragma language=extended
#else
#error Not supported compiler type
#endif
/* ----------------------------------------------------------------------------
-- ADC Peripheral Access Layer
---------------------------------------------------------------------------- */
/**
* @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
* @{
*/
/** ADC - Register Layout Typedef */
typedef struct {
__IO uint32_t SC1[2]; /**< ADC status and control registers 1, array offset: 0x0, array step: 0x4 */
__IO uint32_t CFG1; /**< ADC configuration register 1, offset: 0x8 */
__IO uint32_t CFG2; /**< Configuration register 2, offset: 0xC */
__I uint32_t R[2]; /**< ADC data result register, array offset: 0x10, array step: 0x4 */
__IO uint32_t CV1; /**< Compare value registers, offset: 0x18 */
__IO uint32_t CV2; /**< Compare value registers, offset: 0x1C */
__IO uint32_t SC2; /**< Status and control register 2, offset: 0x20 */
__IO uint32_t SC3; /**< Status and control register 3, offset: 0x24 */
__IO uint32_t OFS; /**< ADC offset correction register, offset: 0x28 */
__IO uint32_t PG; /**< ADC plus-side gain register, offset: 0x2C */
__IO uint32_t MG; /**< ADC minus-side gain register, offset: 0x30 */
__IO uint32_t CLPD; /**< ADC plus-side general calibration value register, offset: 0x34 */
__IO uint32_t CLPS; /**< ADC plus-side general calibration value register, offset: 0x38 */
__IO uint32_t CLP4; /**< ADC plus-side general calibration value register, offset: 0x3C */
__IO uint32_t CLP3; /**< ADC plus-side general calibration value register, offset: 0x40 */
__IO uint32_t CLP2; /**< ADC plus-side general calibration value register, offset: 0x44 */
__IO uint32_t CLP1; /**< ADC plus-side general calibration value register, offset: 0x48 */
__IO uint32_t CLP0; /**< ADC plus-side general calibration value register, offset: 0x4C */
__IO uint32_t PGA; /**< ADC PGA register, offset: 0x50 */
__IO uint32_t CLMD; /**< ADC minus-side general calibration value register, offset: 0x54 */
__IO uint32_t CLMS; /**< ADC minus-side general calibration value register, offset: 0x58 */
__IO uint32_t CLM4; /**< ADC minus-side general calibration value register, offset: 0x5C */
__IO uint32_t CLM3; /**< ADC minus-side general calibration value register, offset: 0x60 */
__IO uint32_t CLM2; /**< ADC minus-side general calibration value register, offset: 0x64 */
__IO uint32_t CLM1; /**< ADC minus-side general calibration value register, offset: 0x68 */
__IO uint32_t CLM0; /**< ADC minus-side general calibration value register, offset: 0x6C */
} ADC_Type;
/* ----------------------------------------------------------------------------
-- ADC Register Masks
---------------------------------------------------------------------------- */
/**
* @addtogroup ADC_Register_Masks ADC Register Masks
* @{
*/
/* SC1 Bit Fields */
#define ADC_SC1_ADCH_MASK 0x1Fu
#define ADC_SC1_ADCH_SHIFT 0
#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
#define ADC_SC1_DIFF_MASK 0x20u
#define ADC_SC1_DIFF_SHIFT 5
#define ADC_SC1_AIEN_MASK 0x40u
#define ADC_SC1_AIEN_SHIFT 6
#define ADC_SC1_COCO_MASK 0x80u
#define ADC_SC1_COCO_SHIFT 7
/* CFG1 Bit Fields */
#define ADC_CFG1_ADICLK_MASK 0x3u
#define ADC_CFG1_ADICLK_SHIFT 0
#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
#define ADC_CFG1_MODE_MASK 0xCu
#define ADC_CFG1_MODE_SHIFT 2
#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
#define ADC_CFG1_ADLSMP_MASK 0x10u
#define ADC_CFG1_ADLSMP_SHIFT 4
#define ADC_CFG1_ADIV_MASK 0x60u
#define ADC_CFG1_ADIV_SHIFT 5
#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
#define ADC_CFG1_ADLPC_MASK 0x80u
#define ADC_CFG1_ADLPC_SHIFT 7
/* CFG2 Bit Fields */
#define ADC_CFG2_ADLSTS_MASK 0x3u
#define ADC_CFG2_ADLSTS_SHIFT 0
#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
#define ADC_CFG2_ADHSC_MASK 0x4u
#define ADC_CFG2_ADHSC_SHIFT 2
#define ADC_CFG2_ADACKEN_MASK 0x8u
#define ADC_CFG2_ADACKEN_SHIFT 3
#define ADC_CFG2_MUXSEL_MASK 0x10u
#define ADC_CFG2_MUXSEL_SHIFT 4
/* R Bit Fields */
#define ADC_R_D_MASK 0xFFFFu
#define ADC_R_D_SHIFT 0
#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
/* CV1 Bit Fields */
#define ADC_CV1_CV_MASK 0xFFFFu
#define ADC_CV1_CV_SHIFT 0
#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
/* CV2 Bit Fields */
#define ADC_CV2_CV_MASK 0xFFFFu
#define ADC_CV2_CV_SHIFT 0
#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
/* SC2 Bit Fields */
#define ADC_SC2_REFSEL_MASK 0x3u
#define ADC_SC2_REFSEL_SHIFT 0
#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
#define ADC_SC2_DMAEN_MASK 0x4u
#define ADC_SC2_DMAEN_SHIFT 2
#define ADC_SC2_ACREN_MASK 0x8u
#define ADC_SC2_ACREN_SHIFT 3
#define ADC_SC2_ACFGT_MASK 0x10u
#define ADC_SC2_ACFGT_SHIFT 4
#define ADC_SC2_ACFE_MASK 0x20u
#define ADC_SC2_ACFE_SHIFT 5
#define ADC_SC2_ADTRG_MASK 0x40u
#define ADC_SC2_ADTRG_SHIFT 6
#define ADC_SC2_ADACT_MASK 0x80u
#define ADC_SC2_ADACT_SHIFT 7
/* SC3 Bit Fields */
#define ADC_SC3_AVGS_MASK 0x3u
#define ADC_SC3_AVGS_SHIFT 0
#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
#define ADC_SC3_AVGE_MASK 0x4u
#define ADC_SC3_AVGE_SHIFT 2
#define ADC_SC3_ADCO_MASK 0x8u
#define ADC_SC3_ADCO_SHIFT 3
#define ADC_SC3_CALF_MASK 0x40u
#define ADC_SC3_CALF_SHIFT 6
#define ADC_SC3_CAL_MASK 0x80u
#define ADC_SC3_CAL_SHIFT 7
/* OFS Bit Fields */
#define ADC_OFS_OFS_MASK 0xFFFFu
#define ADC_OFS_OFS_SHIFT 0
#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
/* PG Bit Fields */
#define ADC_PG_PG_MASK 0xFFFFu
#define ADC_PG_PG_SHIFT 0
#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
/* MG Bit Fields */
#define ADC_MG_MG_MASK 0xFFFFu
#define ADC_MG_MG_SHIFT 0
#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
/* CLPD Bit Fields */
#define ADC_CLPD_CLPD_MASK 0x3Fu
#define ADC_CLPD_CLPD_SHIFT 0
#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
/* CLPS Bit Fields */
#define ADC_CLPS_CLPS_MASK 0x3Fu
#define ADC_CLPS_CLPS_SHIFT 0
#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
/* CLP4 Bit Fields */
#define ADC_CLP4_CLP4_MASK 0x3FFu
#define ADC_CLP4_CLP4_SHIFT 0
#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
/* CLP3 Bit Fields */
#define ADC_CLP3_CLP3_MASK 0x1FFu
#define ADC_CLP3_CLP3_SHIFT 0
#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
/* CLP2 Bit Fields */
#define ADC_CLP2_CLP2_MASK 0xFFu
#define ADC_CLP2_CLP2_SHIFT 0
#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
/* CLP1 Bit Fields */
#define ADC_CLP1_CLP1_MASK 0x7Fu
#define ADC_CLP1_CLP1_SHIFT 0
#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
/* CLP0 Bit Fields */
#define ADC_CLP0_CLP0_MASK 0x3Fu
#define ADC_CLP0_CLP0_SHIFT 0
#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
/* PGA Bit Fields */
#define ADC_PGA_PGAG_MASK 0xF0000u
#define ADC_PGA_PGAG_SHIFT 16
#define ADC_PGA_PGAG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PGA_PGAG_SHIFT))&ADC_PGA_PGAG_MASK)
#define ADC_PGA_PGAEN_MASK 0x800000u
#define ADC_PGA_PGAEN_SHIFT 23
/* CLMD Bit Fields */
#define ADC_CLMD_CLMD_MASK 0x3Fu
#define ADC_CLMD_CLMD_SHIFT 0
#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
/* CLMS Bit Fields */
#define ADC_CLMS_CLMS_MASK 0x3Fu
#define ADC_CLMS_CLMS_SHIFT 0
#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
/* CLM4 Bit Fields */
#define ADC_CLM4_CLM4_MASK 0x3FFu
#define ADC_CLM4_CLM4_SHIFT 0
#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
/* CLM3 Bit Fields */
#define ADC_CLM3_CLM3_MASK 0x1FFu
#define ADC_CLM3_CLM3_SHIFT 0
#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
/* CLM2 Bit Fields */
#define ADC_CLM2_CLM2_MASK 0xFFu
#define ADC_CLM2_CLM2_SHIFT 0
#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
/* CLM1 Bit Fields */
#define ADC_CLM1_CLM1_MASK 0x7Fu
#define ADC_CLM1_CLM1_SHIFT 0
#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
/* CLM0 Bit Fields */
#define ADC_CLM0_CLM0_MASK 0x3Fu
#define ADC_CLM0_CLM0_SHIFT 0
#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
/**
* @}
*/ /* end of group ADC_Register_Masks */
/* ADC - Peripheral instance base addresses */
/** Peripheral ADC0 base address */
#define ADC0_BASE (0x4003B000u)
/** Peripheral ADC0 base pointer */
#define ADC0 ((ADC_Type *)ADC0_BASE)
/** Peripheral ADC1 base address */
#define ADC1_BASE (0x400BB000u)
/** Peripheral ADC1 base pointer */
#define ADC1 ((ADC_Type *)ADC1_BASE)
/**
* @}
*/ /* end of group ADC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- AIPS Peripheral Access Layer
---------------------------------------------------------------------------- */
/**
* @addtogroup AIPS_Peripheral_Access_Layer AIPS Peripheral Access Layer
* @{
*/
/** AIPS - Register Layout Typedef */
typedef struct {
__IO uint32_t MPRA; /**< Master Privilege Register A, offset: 0x0 */
uint8_t RESERVED_0[28];
__IO uint32_t PACRA; /**< Peripheral Access Control Register, offset: 0x20 */
__IO uint32_t PACRB; /**< Peripheral Access Control Register, offset: 0x24 */
__IO uint32_t PACRC; /**< Peripheral Access Control Register, offset: 0x28 */
__IO uint32_t PACRD; /**< Peripheral Access Control Register, offset: 0x2C */
uint8_t RESERVED_1[16];
__IO uint32_t PACRE; /**< Peripheral Access Control Register, offset: 0x40 */
__IO uint32_t PACRF; /**< Peripheral Access Control Register, offset: 0x44 */
__IO uint32_t PACRG; /**< Peripheral Access Control Register, offset: 0x48 */
__IO uint32_t PACRH; /**< Peripheral Access Control Register, offset: 0x4C */
__IO uint32_t PACRI; /**< Peripheral Access Control Register, offset: 0x50 */
__IO uint32_t PACRJ; /**< Peripheral Access Control Register, offset: 0x54 */
__IO uint32_t PACRK; /**< Peripheral Access Control Register, offset: 0x58 */
__IO uint32_t PACRL; /**< Peripheral Access Control Register, offset: 0x5C */
__IO uint32_t PACRM; /**< Peripheral Access Control Register, offset: 0x60 */
__IO uint32_t PACRN; /**< Peripheral Access Control Register, offset: 0x64 */
__IO uint32_t PACRO; /**< Peripheral Access Control Register, offset: 0x68 */
__IO uint32_t PACRP; /**< Peripheral Access Control Register, offset: 0x6C */
} AIPS_Type;
/* ----------------------------------------------------------------------------
-- AIPS Register Masks
---------------------------------------------------------------------------- */
/**
* @addtogroup AIPS_Register_Masks AIPS Register Masks
* @{
*/
/* MPRA Bit Fields */
#define AIPS_MPRA_MPL5_MASK 0x100u
#define AIPS_MPRA_MPL5_SHIFT 8
#define AIPS_MPRA_MTW5_MASK 0x200u
#define AIPS_MPRA_MTW5_SHIFT 9
#define AIPS_MPRA_MTR5_MASK 0x400u
#define AIPS_MPRA_MTR5_SHIFT 10
#define AIPS_MPRA_MPL4_MASK 0x1000u
#define AIPS_MPRA_MPL4_SHIFT 12
#define AIPS_MPRA_MTW4_MASK 0x2000u
#define AIPS_MPRA_MTW4_SHIFT 13
#define AIPS_MPRA_MTR4_MASK 0x4000u
#define AIPS_MPRA_MTR4_SHIFT 14
#define AIPS_MPRA_MPL3_MASK 0x10000u
#define AIPS_MPRA_MPL3_SHIFT 16
#define AIPS_MPRA_MTW3_MASK 0x20000u
#define AIPS_MPRA_MTW3_SHIFT 17
#define AIPS_MPRA_MTR3_MASK 0x40000u
#define AIPS_MPRA_MTR3_SHIFT 18
#define AIPS_MPRA_MPL2_MASK 0x100000u
#define AIPS_MPRA_MPL2_SHIFT 20
#define AIPS_MPRA_MTW2_MASK 0x200000u
#define AIPS_MPRA_MTW2_SHIFT 21
#define AIPS_MPRA_MTR2_MASK 0x400000u
#define AIPS_MPRA_MTR2_SHIFT 22
#define AIPS_MPRA_MPL1_MASK 0x1000000u
#define AIPS_MPRA_MPL1_SHIFT 24
#define AIPS_MPRA_MTW1_MASK 0x2000000u
#define AIPS_MPRA_MTW1_SHIFT 25
#define AIPS_MPRA_MTR1_MASK 0x4000000u
#define AIPS_MPRA_MTR1_SHIFT 26
#define AIPS_MPRA_MPL0_MASK 0x10000000u
#define AIPS_MPRA_MPL0_SHIFT 28
#define AIPS_MPRA_MTW0_MASK 0x20000000u
#define AIPS_MPRA_MTW0_SHIFT 29
#define AIPS_MPRA_MTR0_MASK 0x40000000u
#define AIPS_MPRA_MTR0_SHIFT 30
/* PACRA Bit Fields */
#define AIPS_PACRA_TP7_MASK 0x1u
#define AIPS_PACRA_TP7_SHIFT 0
#define AIPS_PACRA_WP7_MASK 0x2u
#define AIPS_PACRA_WP7_SHIFT 1
#define AIPS_PACRA_SP7_MASK 0x4u
#define AIPS_PACRA_SP7_SHIFT 2
#define AIPS_PACRA_TP6_MASK 0x10u
#define AIPS_PACRA_TP6_SHIFT 4
#define AIPS_PACRA_WP6_MASK 0x20u
#define AIPS_PACRA_WP6_SHIFT 5
#define AIPS_PACRA_SP6_MASK 0x40u
#define AIPS_PACRA_SP6_SHIFT 6
#define AIPS_PACRA_TP5_MASK 0x100u
#define AIPS_PACRA_TP5_SHIFT 8
#define AIPS_PACRA_WP5_MASK 0x200u
#define AIPS_PACRA_WP5_SHIFT 9
#define AIPS_PACRA_SP5_MASK 0x400u
#define AIPS_PACRA_SP5_SHIFT 10
#define AIPS_PACRA_TP4_MASK 0x1000u
#define AIPS_PACRA_TP4_SHIFT 12
#define AIPS_PACRA_WP4_MASK 0x2000u
#define AIPS_PACRA_WP4_SHIFT 13
#define AIPS_PACRA_SP4_MASK 0x4000u
#define AIPS_PACRA_SP4_SHIFT 14
#define AIPS_PACRA_TP3_MASK 0x10000u
#define AIPS_PACRA_TP3_SHIFT 16
#define AIPS_PACRA_WP3_MASK 0x20000u
#define AIPS_PACRA_WP3_SHIFT 17
#define AIPS_PACRA_SP3_MASK 0x40000u
#define AIPS_PACRA_SP3_SHIFT 18
#define AIPS_PACRA_TP2_MASK 0x100000u
#define AIPS_PACRA_TP2_SHIFT 20
#define AIPS_PACRA_WP2_MASK 0x200000u
#define AIPS_PACRA_WP2_SHIFT 21
#define AIPS_PACRA_SP2_MASK 0x400000u
#define AIPS_PACRA_SP2_SHIFT 22
#define AIPS_PACRA_TP1_MASK 0x1000000u
#define AIPS_PACRA_TP1_SHIFT 24
#define AIPS_PACRA_WP1_MASK 0x2000000u
#define AIPS_PACRA_WP1_SHIFT 25
#define AIPS_PACRA_SP1_MASK 0x4000000u
#define AIPS_PACRA_SP1_SHIFT 26
#define AIPS_PACRA_TP0_MASK 0x10000000u
#define AIPS_PACRA_TP0_SHIFT 28
#define AIPS_PACRA_WP0_MASK 0x20000000u
#define AIPS_PACRA_WP0_SHIFT 29
#define AIPS_PACRA_SP0_MASK 0x40000000u
#define AIPS_PACRA_SP0_SHIFT 30
/* PACRB Bit Fields */
#define AIPS_PACRB_TP7_MASK 0x1u
#define AIPS_PACRB_TP7_SHIFT 0
#define AIPS_PACRB_WP7_MASK 0x2u
#define AIPS_PACRB_WP7_SHIFT 1
#define AIPS_PACRB_SP7_MASK 0x4u
#define AIPS_PACRB_SP7_SHIFT 2
#define AIPS_PACRB_TP6_MASK 0x10u
#define AIPS_PACRB_TP6_SHIFT 4
#define AIPS_PACRB_WP6_MASK 0x20u
#define AIPS_PACRB_WP6_SHIFT 5
#define AIPS_PACRB_SP6_MASK 0x40u
#define AIPS_PACRB_SP6_SHIFT 6
#define AIPS_PACRB_TP5_MASK 0x100u
#define AIPS_PACRB_TP5_SHIFT 8
#define AIPS_PACRB_WP5_MASK 0x200u
#define AIPS_PACRB_WP5_SHIFT 9
#define AIPS_PACRB_SP5_MASK 0x400u
#define AIPS_PACRB_SP5_SHIFT 10
#define AIPS_PACRB_TP4_MASK 0x1000u
#define AIPS_PACRB_TP4_SHIFT 12
#define AIPS_PACRB_WP4_MASK 0x2000u
#define AIPS_PACRB_WP4_SHIFT 13
#define AIPS_PACRB_SP4_MASK 0x4000u
#define AIPS_PACRB_SP4_SHIFT 14
#define AIPS_PACRB_TP3_MASK 0x10000u
#define AIPS_PACRB_TP3_SHIFT 16
#define AIPS_PACRB_WP3_MASK 0x20000u
#define AIPS_PACRB_WP3_SHIFT 17
#define AIPS_PACRB_SP3_MASK 0x40000u
#define AIPS_PACRB_SP3_SHIFT 18
#define AIPS_PACRB_TP2_MASK 0x100000u
#define AIPS_PACRB_TP2_SHIFT 20
#define AIPS_PACRB_WP2_MASK 0x200000u
#define AIPS_PACRB_WP2_SHIFT 21
#define AIPS_PACRB_SP2_MASK 0x400000u
#define AIPS_PACRB_SP2_SHIFT 22
#define AIPS_PACRB_TP1_MASK 0x1000000u
#define AIPS_PACRB_TP1_SHIFT 24
#define AIPS_PACRB_WP1_MASK 0x2000000u
#define AIPS_PACRB_WP1_SHIFT 25
#define AIPS_PACRB_SP1_MASK 0x4000000u
#define AIPS_PACRB_SP1_SHIFT 26
#define AIPS_PACRB_TP0_MASK 0x10000000u
#define AIPS_PACRB_TP0_SHIFT 28
#define AIPS_PACRB_WP0_MASK 0x20000000u
#define AIPS_PACRB_WP0_SHIFT 29
#define AIPS_PACRB_SP0_MASK 0x40000000u
#define AIPS_PACRB_SP0_SHIFT 30
/* PACRC Bit Fields */
#define AIPS_PACRC_TP7_MASK 0x1u
#define AIPS_PACRC_TP7_SHIFT 0
#define AIPS_PACRC_WP7_MASK 0x2u
#define AIPS_PACRC_WP7_SHIFT 1
#define AIPS_PACRC_SP7_MASK 0x4u
#define AIPS_PACRC_SP7_SHIFT 2
#define AIPS_PACRC_TP6_MASK 0x10u
#define AIPS_PACRC_TP6_SHIFT 4
#define AIPS_PACRC_WP6_MASK 0x20u
#define AIPS_PACRC_WP6_SHIFT 5
#define AIPS_PACRC_SP6_MASK 0x40u
#define AIPS_PACRC_SP6_SHIFT 6
#define AIPS_PACRC_TP5_MASK 0x100u
#define AIPS_PACRC_TP5_SHIFT 8
#define AIPS_PACRC_WP5_MASK 0x200u
#define AIPS_PACRC_WP5_SHIFT 9
#define AIPS_PACRC_SP5_MASK 0x400u
#define AIPS_PACRC_SP5_SHIFT 10
#define AIPS_PACRC_TP4_MASK 0x1000u
#define AIPS_PACRC_TP4_SHIFT 12
#define AIPS_PACRC_WP4_MASK 0x2000u
#define AIPS_PACRC_WP4_SHIFT 13
#define AIPS_PACRC_SP4_MASK 0x4000u
#define AIPS_PACRC_SP4_SHIFT 14
#define AIPS_PACRC_TP3_MASK 0x10000u
#define AIPS_PACRC_TP3_SHIFT 16
#define AIPS_PACRC_WP3_MASK 0x20000u
#define AIPS_PACRC_WP3_SHIFT 17
#define AIPS_PACRC_SP3_MASK 0x40000u
#define AIPS_PACRC_SP3_SHIFT 18
#define AIPS_PACRC_TP2_MASK 0x100000u
#define AIPS_PACRC_TP2_SHIFT 20
#define AIPS_PACRC_WP2_MASK 0x200000u
#define AIPS_PACRC_WP2_SHIFT 21
#define AIPS_PACRC_SP2_MASK 0x400000u
#define AIPS_PACRC_SP2_SHIFT 22
#define AIPS_PACRC_TP1_MASK 0x1000000u
#define AIPS_PACRC_TP1_SHIFT 24
#define AIPS_PACRC_WP1_MASK 0x2000000u
#define AIPS_PACRC_WP1_SHIFT 25
#define AIPS_PACRC_SP1_MASK 0x4000000u
#define AIPS_PACRC_SP1_SHIFT 26
#define AIPS_PACRC_TP0_MASK 0x10000000u
#define AIPS_PACRC_TP0_SHIFT 28
#define AIPS_PACRC_WP0_MASK 0x20000000u
#define AIPS_PACRC_WP0_SHIFT 29
#define AIPS_PACRC_SP0_MASK 0x40000000u
#define AIPS_PACRC_SP0_SHIFT 30
/* PACRD Bit Fields */
#define AIPS_PACRD_TP7_MASK 0x1u
#define AIPS_PACRD_TP7_SHIFT 0
#define AIPS_PACRD_WP7_MASK 0x2u
#define AIPS_PACRD_WP7_SHIFT 1
#define AIPS_PACRD_SP7_MASK 0x4u
#define AIPS_PACRD_SP7_SHIFT 2
#define AIPS_PACRD_TP6_MASK 0x10u
#define AIPS_PACRD_TP6_SHIFT 4
#define AIPS_PACRD_WP6_MASK 0x20u
#define AIPS_PACRD_WP6_SHIFT 5
#define AIPS_PACRD_SP6_MASK 0x40u
#define AIPS_PACRD_SP6_SHIFT 6
#define AIPS_PACRD_TP5_MASK 0x100u
#define AIPS_PACRD_TP5_SHIFT 8
#define AIPS_PACRD_WP5_MASK 0x200u
#define AIPS_PACRD_WP5_SHIFT 9
#define AIPS_PACRD_SP5_MASK 0x400u
#define AIPS_PACRD_SP5_SHIFT 10
#define AIPS_PACRD_TP4_MASK 0x1000u
#define AIPS_PACRD_TP4_SHIFT 12
#define AIPS_PACRD_WP4_MASK 0x2000u
#define AIPS_PACRD_WP4_SHIFT 13
#define AIPS_PACRD_SP4_MASK 0x4000u
#define AIPS_PACRD_SP4_SHIFT 14
#define AIPS_PACRD_TP3_MASK 0x10000u
#define AIPS_PACRD_TP3_SHIFT 16
#define AIPS_PACRD_WP3_MASK 0x20000u
#define AIPS_PACRD_WP3_SHIFT 17
#define AIPS_PACRD_SP3_MASK 0x40000u
#define AIPS_PACRD_SP3_SHIFT 18
#define AIPS_PACRD_TP2_MASK 0x100000u
#define AIPS_PACRD_TP2_SHIFT 20
#define AIPS_PACRD_WP2_MASK 0x200000u
#define AIPS_PACRD_WP2_SHIFT 21
#define AIPS_PACRD_SP2_MASK 0x400000u
#define AIPS_PACRD_SP2_SHIFT 22
#define AIPS_PACRD_TP1_MASK 0x1000000u
#define AIPS_PACRD_TP1_SHIFT 24
#define AIPS_PACRD_WP1_MASK 0x2000000u
#define AIPS_PACRD_WP1_SHIFT 25
#define AIPS_PACRD_SP1_MASK 0x4000000u
#define AIPS_PACRD_SP1_SHIFT 26
#define AIPS_PACRD_TP0_MASK 0x10000000u
#define AIPS_PACRD_TP0_SHIFT 28
#define AIPS_PACRD_WP0_MASK 0x20000000u
#define AIPS_PACRD_WP0_SHIFT 29
#define AIPS_PACRD_SP0_MASK 0x40000000u
#define AIPS_PACRD_SP0_SHIFT 30
/* PACRE Bit Fields */
#define AIPS_PACRE_TP7_MASK 0x1u
#define AIPS_PACRE_TP7_SHIFT 0
#define AIPS_PACRE_WP7_MASK 0x2u
#define AIPS_PACRE_WP7_SHIFT 1
#define AIPS_PACRE_SP7_MASK 0x4u
#define AIPS_PACRE_SP7_SHIFT 2
#define AIPS_PACRE_TP6_MASK 0x10u
#define AIPS_PACRE_TP6_SHIFT 4
#define AIPS_PACRE_WP6_MASK 0x20u
#define AIPS_PACRE_WP6_SHIFT 5
#define AIPS_PACRE_SP6_MASK 0x40u
#define AIPS_PACRE_SP6_SHIFT 6
#define AIPS_PACRE_TP5_MASK 0x100u
#define AIPS_PACRE_TP5_SHIFT 8
#define AIPS_PACRE_WP5_MASK 0x200u
#define AIPS_PACRE_WP5_SHIFT 9
#define AIPS_PACRE_SP5_MASK 0x400u
#define AIPS_PACRE_SP5_SHIFT 10
#define AIPS_PACRE_TP4_MASK 0x1000u
#define AIPS_PACRE_TP4_SHIFT 12
#define AIPS_PACRE_WP4_MASK 0x2000u
#define AIPS_PACRE_WP4_SHIFT 13
#define AIPS_PACRE_SP4_MASK 0x4000u
#define AIPS_PACRE_SP4_SHIFT 14
#define AIPS_PACRE_TP3_MASK 0x10000u
#define AIPS_PACRE_TP3_SHIFT 16
#define AIPS_PACRE_WP3_MASK 0x20000u
#define AIPS_PACRE_WP3_SHIFT 17
#define AIPS_PACRE_SP3_MASK 0x40000u
#define AIPS_PACRE_SP3_SHIFT 18
#define AIPS_PACRE_TP2_MASK 0x100000u
#define AIPS_PACRE_TP2_SHIFT 20
#define AIPS_PACRE_WP2_MASK 0x200000u
#define AIPS_PACRE_WP2_SHIFT 21
#define AIPS_PACRE_SP2_MASK 0x400000u
#define AIPS_PACRE_SP2_SHIFT 22
#define AIPS_PACRE_TP1_MASK 0x1000000u
#define AIPS_PACRE_TP1_SHIFT 24
#define AIPS_PACRE_WP1_MASK 0x2000000u
#define AIPS_PACRE_WP1_SHIFT 25
#define AIPS_PACRE_SP1_MASK 0x4000000u
#define AIPS_PACRE_SP1_SHIFT 26
#define AIPS_PACRE_TP0_MASK 0x10000000u
#define AIPS_PACRE_TP0_SHIFT 28
#define AIPS_PACRE_WP0_MASK 0x20000000u
#define AIPS_PACRE_WP0_SHIFT 29
#define AIPS_PACRE_SP0_MASK 0x40000000u
#define AIPS_PACRE_SP0_SHIFT 30
/* PACRF Bit Fields */
#define AIPS_PACRF_TP7_MASK 0x1u
#define AIPS_PACRF_TP7_SHIFT 0
#define AIPS_PACRF_WP7_MASK 0x2u
#define AIPS_PACRF_WP7_SHIFT 1
#define AIPS_PACRF_SP7_MASK 0x4u
#define AIPS_PACRF_SP7_SHIFT 2
#define AIPS_PACRF_TP6_MASK 0x10u
#define AIPS_PACRF_TP6_SHIFT 4
#define AIPS_PACRF_WP6_MASK 0x20u
#define AIPS_PACRF_WP6_SHIFT 5
#define AIPS_PACRF_SP6_MASK 0x40u
#define AIPS_PACRF_SP6_SHIFT 6
#define AIPS_PACRF_TP5_MASK 0x100u
#define AIPS_PACRF_TP5_SHIFT 8
#define AIPS_PACRF_WP5_MASK 0x200u
#define AIPS_PACRF_WP5_SHIFT 9
#define AIPS_PACRF_SP5_MASK 0x400u
#define AIPS_PACRF_SP5_SHIFT 10
#define AIPS_PACRF_TP4_MASK 0x1000u
#define AIPS_PACRF_TP4_SHIFT 12
#define AIPS_PACRF_WP4_MASK 0x2000u
#define AIPS_PACRF_WP4_SHIFT 13
#define AIPS_PACRF_SP4_MASK 0x4000u
#define AIPS_PACRF_SP4_SHIFT 14
#define AIPS_PACRF_TP3_MASK 0x10000u
#define AIPS_PACRF_TP3_SHIFT 16
#define AIPS_PACRF_WP3_MASK 0x20000u
#define AIPS_PACRF_WP3_SHIFT 17
#define AIPS_PACRF_SP3_MASK 0x40000u
#define AIPS_PACRF_SP3_SHIFT 18
#define AIPS_PACRF_TP2_MASK 0x100000u
#define AIPS_PACRF_TP2_SHIFT 20
#define AIPS_PACRF_WP2_MASK 0x200000u
#define AIPS_PACRF_WP2_SHIFT 21
#define AIPS_PACRF_SP2_MASK 0x400000u
#define AIPS_PACRF_SP2_SHIFT 22
#define AIPS_PACRF_TP1_MASK 0x1000000u
#define AIPS_PACRF_TP1_SHIFT 24
#define AIPS_PACRF_WP1_MASK 0x2000000u
#define AIPS_PACRF_WP1_SHIFT 25
#define AIPS_PACRF_SP1_MASK 0x4000000u
#define AIPS_PACRF_SP1_SHIFT 26
#define AIPS_PACRF_TP0_MASK 0x10000000u
#define AIPS_PACRF_TP0_SHIFT 28
#define AIPS_PACRF_WP0_MASK 0x20000000u
#define AIPS_PACRF_WP0_SHIFT 29
#define AIPS_PACRF_SP0_MASK 0x40000000u
#define AIPS_PACRF_SP0_SHIFT 30
/* PACRG Bit Fields */
#define AIPS_PACRG_TP7_MASK 0x1u
#define AIPS_PACRG_TP7_SHIFT 0
#define AIPS_PACRG_WP7_MASK 0x2u
#define AIPS_PACRG_WP7_SHIFT 1
#define AIPS_PACRG_SP7_MASK 0x4u
#define AIPS_PACRG_SP7_SHIFT 2
#define AIPS_PACRG_TP6_MASK 0x10u
#define AIPS_PACRG_TP6_SHIFT 4
#define AIPS_PACRG_WP6_MASK 0x20u
#define AIPS_PACRG_WP6_SHIFT 5
#define AIPS_PACRG_SP6_MASK 0x40u
#define AIPS_PACRG_SP6_SHIFT 6
#define AIPS_PACRG_TP5_MASK 0x100u
#define AIPS_PACRG_TP5_SHIFT 8
#define AIPS_PACRG_WP5_MASK 0x200u
#define AIPS_PACRG_WP5_SHIFT 9
#define AIPS_PACRG_SP5_MASK 0x400u
#define AIPS_PACRG_SP5_SHIFT 10
#define AIPS_PACRG_TP4_MASK 0x1000u
#define AIPS_PACRG_TP4_SHIFT 12
#define AIPS_PACRG_WP4_MASK 0x2000u
#define AIPS_PACRG_WP4_SHIFT 13
#define AIPS_PACRG_SP4_MASK 0x4000u
#define AIPS_PACRG_SP4_SHIFT 14
#define AIPS_PACRG_TP3_MASK 0x10000u
#define AIPS_PACRG_TP3_SHIFT 16
#define AIPS_PACRG_WP3_MASK 0x20000u
#define AIPS_PACRG_WP3_SHIFT 17
#define AIPS_PACRG_SP3_MASK 0x40000u
#define AIPS_PACRG_SP3_SHIFT 18
#define AIPS_PACRG_TP2_MASK 0x100000u
#define AIPS_PACRG_TP2_SHIFT 20
#define AIPS_PACRG_WP2_MASK 0x200000u
#define AIPS_PACRG_WP2_SHIFT 21
#define AIPS_PACRG_SP2_MASK 0x400000u
#define AIPS_PACRG_SP2_SHIFT 22
#define AIPS_PACRG_TP1_MASK 0x1000000u
#define AIPS_PACRG_TP1_SHIFT 24
#define AIPS_PACRG_WP1_MASK 0x2000000u
#define AIPS_PACRG_WP1_SHIFT 25
#define AIPS_PACRG_SP1_MASK 0x4000000u
#define AIPS_PACRG_SP1_SHIFT 26
#define AIPS_PACRG_TP0_MASK 0x10000000u
#define AIPS_PACRG_TP0_SHIFT 28
#define AIPS_PACRG_WP0_MASK 0x20000000u
#define AIPS_PACRG_WP0_SHIFT 29
#define AIPS_PACRG_SP0_MASK 0x40000000u
#define AIPS_PACRG_SP0_SHIFT 30
/* PACRH Bit Fields */
#define AIPS_PACRH_TP7_MASK 0x1u
#define AIPS_PACRH_TP7_SHIFT 0
#define AIPS_PACRH_WP7_MASK 0x2u
#define AIPS_PACRH_WP7_SHIFT 1
#define AIPS_PACRH_SP7_MASK 0x4u
#define AIPS_PACRH_SP7_SHIFT 2
#define AIPS_PACRH_TP6_MASK 0x10u
#define AIPS_PACRH_TP6_SHIFT 4
#define AIPS_PACRH_WP6_MASK 0x20u
#define AIPS_PACRH_WP6_SHIFT 5
#define AIPS_PACRH_SP6_MASK 0x40u
#define AIPS_PACRH_SP6_SHIFT 6
#define AIPS_PACRH_TP5_MASK 0x100u
#define AIPS_PACRH_TP5_SHIFT 8
#define AIPS_PACRH_WP5_MASK 0x200u
#define AIPS_PACRH_WP5_SHIFT 9
#define AIPS_PACRH_SP5_MASK 0x400u
#define AIPS_PACRH_SP5_SHIFT 10
#define AIPS_PACRH_TP4_MASK 0x1000u
#define AIPS_PACRH_TP4_SHIFT 12
#define AIPS_PACRH_WP4_MASK 0x2000u
#define AIPS_PACRH_WP4_SHIFT 13
#define AIPS_PACRH_SP4_MASK 0x4000u
#define AIPS_PACRH_SP4_SHIFT 14
#define AIPS_PACRH_TP3_MASK 0x10000u
#define AIPS_PACRH_TP3_SHIFT 16
#define AIPS_PACRH_WP3_MASK 0x20000u
#define AIPS_PACRH_WP3_SHIFT 17
#define AIPS_PACRH_SP3_MASK 0x40000u
#define AIPS_PACRH_SP3_SHIFT 18
#define AIPS_PACRH_TP2_MASK 0x100000u
#define AIPS_PACRH_TP2_SHIFT 20
#define AIPS_PACRH_WP2_MASK 0x200000u
#define AIPS_PACRH_WP2_SHIFT 21
#define AIPS_PACRH_SP2_MASK 0x400000u
#define AIPS_PACRH_SP2_SHIFT 22
#define AIPS_PACRH_TP1_MASK 0x1000000u
#define AIPS_PACRH_TP1_SHIFT 24
#define AIPS_PACRH_WP1_MASK 0x2000000u
#define AIPS_PACRH_WP1_SHIFT 25
#define AIPS_PACRH_SP1_MASK 0x4000000u
#define AIPS_PACRH_SP1_SHIFT 26
#define AIPS_PACRH_TP0_MASK 0x10000000u
#define AIPS_PACRH_TP0_SHIFT 28
#define AIPS_PACRH_WP0_MASK 0x20000000u
#define AIPS_PACRH_WP0_SHIFT 29
#define AIPS_PACRH_SP0_MASK 0x40000000u
#define AIPS_PACRH_SP0_SHIFT 30
/* PACRI Bit Fields */
#define AIPS_PACRI_TP7_MASK 0x1u
#define AIPS_PACRI_TP7_SHIFT 0
#define AIPS_PACRI_WP7_MASK 0x2u
#define AIPS_PACRI_WP7_SHIFT 1
#define AIPS_PACRI_SP7_MASK 0x4u
#define AIPS_PACRI_SP7_SHIFT 2
#define AIPS_PACRI_TP6_MASK 0x10u
#define AIPS_PACRI_TP6_SHIFT 4
#define AIPS_PACRI_WP6_MASK 0x20u
#define AIPS_PACRI_WP6_SHIFT 5
#define AIPS_PACRI_SP6_MASK 0x40u
#define AIPS_PACRI_SP6_SHIFT 6
#define AIPS_PACRI_TP5_MASK 0x100u
#define AIPS_PACRI_TP5_SHIFT 8
#define AIPS_PACRI_WP5_MASK 0x200u
#define AIPS_PACRI_WP5_SHIFT 9
#define AIPS_PACRI_SP5_MASK 0x400u
#define AIPS_PACRI_SP5_SHIFT 10
#define AIPS_PACRI_TP4_MASK 0x1000u
#define AIPS_PACRI_TP4_SHIFT 12
#define AIPS_PACRI_WP4_MASK 0x2000u
#define AIPS_PACRI_WP4_SHIFT 13
#define AIPS_PACRI_SP4_MASK 0x4000u
#define AIPS_PACRI_SP4_SHIFT 14
#define AIPS_PACRI_TP3_MASK 0x10000u
#define AIPS_PACRI_TP3_SHIFT 16
#define AIPS_PACRI_WP3_MASK 0x20000u
#define AIPS_PACRI_WP3_SHIFT 17
#define AIPS_PACRI_SP3_MASK 0x40000u
#define AIPS_PACRI_SP3_SHIFT 18
#define AIPS_PACRI_TP2_MASK 0x100000u
#define AIPS_PACRI_TP2_SHIFT 20
#define AIPS_PACRI_WP2_MASK 0x200000u
#define AIPS_PACRI_WP2_SHIFT 21
#define AIPS_PACRI_SP2_MASK 0x400000u
#define AIPS_PACRI_SP2_SHIFT 22
#define AIPS_PACRI_TP1_MASK 0x1000000u
#define AIPS_PACRI_TP1_SHIFT 24
#define AIPS_PACRI_WP1_MASK 0x2000000u
#define AIPS_PACRI_WP1_SHIFT 25
#define AIPS_PACRI_SP1_MASK 0x4000000u
#define AIPS_PACRI_SP1_SHIFT 26
#define AIPS_PACRI_TP0_MASK 0x10000000u
#define AIPS_PACRI_TP0_SHIFT 28
#define AIPS_PACRI_WP0_MASK 0x20000000u
#define AIPS_PACRI_WP0_SHIFT 29
#define AIPS_PACRI_SP0_MASK 0x40000000u
#define AIPS_PACRI_SP0_SHIFT 30
/* PACRJ Bit Fields */
#define AIPS_PACRJ_TP7_MASK 0x1u
#define AIPS_PACRJ_TP7_SHIFT 0
#define AIPS_PACRJ_WP7_MASK 0x2u
#define AIPS_PACRJ_WP7_SHIFT 1
#define AIPS_PACRJ_SP7_MASK 0x4u
#define AIPS_PACRJ_SP7_SHIFT 2
#define AIPS_PACRJ_TP6_MASK 0x10u
#define AIPS_PACRJ_TP6_SHIFT 4
#define AIPS_PACRJ_WP6_MASK 0x20u
#define AIPS_PACRJ_WP6_SHIFT 5
#define AIPS_PACRJ_SP6_MASK 0x40u
#define AIPS_PACRJ_SP6_SHIFT 6
#define AIPS_PACRJ_TP5_MASK 0x100u
#define AIPS_PACRJ_TP5_SHIFT 8
#define AIPS_PACRJ_WP5_MASK 0x200u
#define AIPS_PACRJ_WP5_SHIFT 9
#define AIPS_PACRJ_SP5_MASK 0x400u
#define AIPS_PACRJ_SP5_SHIFT 10
#define AIPS_PACRJ_TP4_MASK 0x1000u
#define AIPS_PACRJ_TP4_SHIFT 12
#define AIPS_PACRJ_WP4_MASK 0x2000u
#define AIPS_PACRJ_WP4_SHIFT 13
#define AIPS_PACRJ_SP4_MASK 0x4000u
#define AIPS_PACRJ_SP4_SHIFT 14
#define AIPS_PACRJ_TP3_MASK 0x10000u
#define AIPS_PACRJ_TP3_SHIFT 16
#define AIPS_PACRJ_WP3_MASK 0x20000u
#define AIPS_PACRJ_WP3_SHIFT 17
#define AIPS_PACRJ_SP3_MASK 0x40000u
#define AIPS_PACRJ_SP3_SHIFT 18
#define AIPS_PACRJ_TP2_MASK 0x100000u
#define AIPS_PACRJ_TP2_SHIFT 20
#define AIPS_PACRJ_WP2_MASK 0x200000u
#define AIPS_PACRJ_WP2_SHIFT 21
#define AIPS_PACRJ_SP2_MASK 0x400000u
#define AIPS_PACRJ_SP2_SHIFT 22
#define AIPS_PACRJ_TP1_MASK 0x1000000u
#define AIPS_PACRJ_TP1_SHIFT 24
#define AIPS_PACRJ_WP1_MASK 0x2000000u
#define AIPS_PACRJ_WP1_SHIFT 25
#define AIPS_PACRJ_SP1_MASK 0x4000000u
#define AIPS_PACRJ_SP1_SHIFT 26
#define AIPS_PACRJ_TP0_MASK 0x10000000u
#define AIPS_PACRJ_TP0_SHIFT 28
#define AIPS_PACRJ_WP0_MASK 0x20000000u
#define AIPS_PACRJ_WP0_SHIFT 29
#define AIPS_PACRJ_SP0_MASK 0x40000000u
#define AIPS_PACRJ_SP0_SHIFT 30
/* PACRK Bit Fields */
#define AIPS_PACRK_TP7_MASK 0x1u
#define AIPS_PACRK_TP7_SHIFT 0
#define AIPS_PACRK_WP7_MASK 0x2u
#define AIPS_PACRK_WP7_SHIFT 1
#define AIPS_PACRK_SP7_MASK 0x4u
#define AIPS_PACRK_SP7_SHIFT 2
#define AIPS_PACRK_TP6_MASK 0x10u
#define AIPS_PACRK_TP6_SHIFT 4
#define AIPS_PACRK_WP6_MASK 0x20u
#define AIPS_PACRK_WP6_SHIFT 5
#define AIPS_PACRK_SP6_MASK 0x40u
#define AIPS_PACRK_SP6_SHIFT 6
#define AIPS_PACRK_TP5_MASK 0x100u
#define AIPS_PACRK_TP5_SHIFT 8
#define AIPS_PACRK_WP5_MASK 0x200u
#define AIPS_PACRK_WP5_SHIFT 9
#define AIPS_PACRK_SP5_MASK 0x400u
#define AIPS_PACRK_SP5_SHIFT 10
#define AIPS_PACRK_TP4_MASK 0x1000u
#define AIPS_PACRK_TP4_SHIFT 12
#define AIPS_PACRK_WP4_MASK 0x2000u
#define AIPS_PACRK_WP4_SHIFT 13
#define AIPS_PACRK_SP4_MASK 0x4000u
#define AIPS_PACRK_SP4_SHIFT 14
#define AIPS_PACRK_TP3_MASK 0x10000u
#define AIPS_PACRK_TP3_SHIFT 16
#define AIPS_PACRK_WP3_MASK 0x20000u
#define AIPS_PACRK_WP3_SHIFT 17
#define AIPS_PACRK_SP3_MASK 0x40000u
#define AIPS_PACRK_SP3_SHIFT 18
#define AIPS_PACRK_TP2_MASK 0x100000u
#define AIPS_PACRK_TP2_SHIFT 20
#define AIPS_PACRK_WP2_MASK 0x200000u
#define AIPS_PACRK_WP2_SHIFT 21
#define AIPS_PACRK_SP2_MASK 0x400000u
#define AIPS_PACRK_SP2_SHIFT 22
#define AIPS_PACRK_TP1_MASK 0x1000000u
#define AIPS_PACRK_TP1_SHIFT 24
#define AIPS_PACRK_WP1_MASK 0x2000000u
#define AIPS_PACRK_WP1_SHIFT 25
#define AIPS_PACRK_SP1_MASK 0x4000000u
#define AIPS_PACRK_SP1_SHIFT 26
#define AIPS_PACRK_TP0_MASK 0x10000000u
#define AIPS_PACRK_TP0_SHIFT 28
#define AIPS_PACRK_WP0_MASK 0x20000000u
#define AIPS_PACRK_WP0_SHIFT 29
#define AIPS_PACRK_SP0_MASK 0x40000000u
#define AIPS_PACRK_SP0_SHIFT 30
/* PACRL Bit Fields */
#define AIPS_PACRL_TP7_MASK 0x1u
#define AIPS_PACRL_TP7_SHIFT 0
#define AIPS_PACRL_WP7_MASK 0x2u
#define AIPS_PACRL_WP7_SHIFT 1
#define AIPS_PACRL_SP7_MASK 0x4u
#define AIPS_PACRL_SP7_SHIFT 2
#define AIPS_PACRL_TP6_MASK 0x10u
#define AIPS_PACRL_TP6_SHIFT 4
#define AIPS_PACRL_WP6_MASK 0x20u
#define AIPS_PACRL_WP6_SHIFT 5
#define AIPS_PACRL_SP6_MASK 0x40u
#define AIPS_PACRL_SP6_SHIFT 6
#define AIPS_PACRL_TP5_MASK 0x100u
#define AIPS_PACRL_TP5_SHIFT 8
#define AIPS_PACRL_WP5_MASK 0x200u
#define AIPS_PACRL_WP5_SHIFT 9
#define AIPS_PACRL_SP5_MASK 0x400u
#define AIPS_PACRL_SP5_SHIFT 10
#define AIPS_PACRL_TP4_MASK 0x1000u
#define AIPS_PACRL_TP4_SHIFT 12
#define AIPS_PACRL_WP4_MASK 0x2000u
#define AIPS_PACRL_WP4_SHIFT 13
#define AIPS_PACRL_SP4_MASK 0x4000u
#define AIPS_PACRL_SP4_SHIFT 14
#define AIPS_PACRL_TP3_MASK 0x10000u
#define AIPS_PACRL_TP3_SHIFT 16
#define AIPS_PACRL_WP3_MASK 0x20000u
#define AIPS_PACRL_WP3_SHIFT 17
#define AIPS_PACRL_SP3_MASK 0x40000u
#define AIPS_PACRL_SP3_SHIFT 18
#define AIPS_PACRL_TP2_MASK 0x100000u
#define AIPS_PACRL_TP2_SHIFT 20
#define AIPS_PACRL_WP2_MASK 0x200000u
#define AIPS_PACRL_WP2_SHIFT 21
#define AIPS_PACRL_SP2_MASK 0x400000u
#define AIPS_PACRL_SP2_SHIFT 22
#define AIPS_PACRL_TP1_MASK 0x1000000u
#define AIPS_PACRL_TP1_SHIFT 24
#define AIPS_PACRL_WP1_MASK 0x2000000u
#define AIPS_PACRL_WP1_SHIFT 25
#define AIPS_PACRL_SP1_MASK 0x4000000u
#define AIPS_PACRL_SP1_SHIFT 26
#define AIPS_PACRL_TP0_MASK 0x10000000u
#define AIPS_PACRL_TP0_SHIFT 28
#define AIPS_PACRL_WP0_MASK 0x20000000u
#define AIPS_PACRL_WP0_SHIFT 29
#define AIPS_PACRL_SP0_MASK 0x40000000u
#define AIPS_PACRL_SP0_SHIFT 30
/* PACRM Bit Fields */
#define AIPS_PACRM_TP7_MASK 0x1u
#define AIPS_PACRM_TP7_SHIFT 0
#define AIPS_PACRM_WP7_MASK 0x2u
#define AIPS_PACRM_WP7_SHIFT 1
#define AIPS_PACRM_SP7_MASK 0x4u
#define AIPS_PACRM_SP7_SHIFT 2
#define AIPS_PACRM_TP6_MASK 0x10u
#define AIPS_PACRM_TP6_SHIFT 4
#define AIPS_PACRM_WP6_MASK 0x20u
#define AIPS_PACRM_WP6_SHIFT 5
#define AIPS_PACRM_SP6_MASK 0x40u
#define AIPS_PACRM_SP6_SHIFT 6
#define AIPS_PACRM_TP5_MASK 0x100u
#define AIPS_PACRM_TP5_SHIFT 8
#define AIPS_PACRM_WP5_MASK 0x200u
#define AIPS_PACRM_WP5_SHIFT 9
#define AIPS_PACRM_SP5_MASK 0x400u
#define AIPS_PACRM_SP5_SHIFT 10
#define AIPS_PACRM_TP4_MASK 0x1000u
#define AIPS_PACRM_TP4_SHIFT 12
#define AIPS_PACRM_WP4_MASK 0x2000u
#define AIPS_PACRM_WP4_SHIFT 13
#define AIPS_PACRM_SP4_MASK 0x4000u
#define AIPS_PACRM_SP4_SHIFT 14
#define AIPS_PACRM_TP3_MASK 0x10000u
#define AIPS_PACRM_TP3_SHIFT 16
#define AIPS_PACRM_WP3_MASK 0x20000u
#define AIPS_PACRM_WP3_SHIFT 17
#define AIPS_PACRM_SP3_MASK 0x40000u
#define AIPS_PACRM_SP3_SHIFT 18
#define AIPS_PACRM_TP2_MASK 0x100000u
#define AIPS_PACRM_TP2_SHIFT 20
#define AIPS_PACRM_WP2_MASK 0x200000u
#define AIPS_PACRM_WP2_SHIFT 21
#define AIPS_PACRM_SP2_MASK 0x400000u
#define AIPS_PACRM_SP2_SHIFT 22
#define AIPS_PACRM_TP1_MASK 0x1000000u
#define AIPS_PACRM_TP1_SHIFT 24
#define AIPS_PACRM_WP1_MASK 0x2000000u
#define AIPS_PACRM_WP1_SHIFT 25
#define AIPS_PACRM_SP1_MASK 0x4000000u
#define AIPS_PACRM_SP1_SHIFT 26
#define AIPS_PACRM_TP0_MASK 0x10000000u
#define AIPS_PACRM_TP0_SHIFT 28
#define AIPS_PACRM_WP0_MASK 0x20000000u
#define AIPS_PACRM_WP0_SHIFT 29
#define AIPS_PACRM_SP0_MASK 0x40000000u
#define AIPS_PACRM_SP0_SHIFT 30
/* PACRN Bit Fields */
#define AIPS_PACRN_TP7_MASK 0x1u
#define AIPS_PACRN_TP7_SHIFT 0
#define AIPS_PACRN_WP7_MASK 0x2u
#define AIPS_PACRN_WP7_SHIFT 1
#define AIPS_PACRN_SP7_MASK 0x4u
#define AIPS_PACRN_SP7_SHIFT 2
#define AIPS_PACRN_TP6_MASK 0x10u
#define AIPS_PACRN_TP6_SHIFT 4
#define AIPS_PACRN_WP6_MASK 0x20u
#define AIPS_PACRN_WP6_SHIFT 5
#define AIPS_PACRN_SP6_MASK 0x40u
#define AIPS_PACRN_SP6_SHIFT 6
#define AIPS_PACRN_TP5_MASK 0x100u
#define AIPS_PACRN_TP5_SHIFT 8
#define AIPS_PACRN_WP5_MASK 0x200u
#define AIPS_PACRN_WP5_SHIFT 9
#define AIPS_PACRN_SP5_MASK 0x400u
#define AIPS_PACRN_SP5_SHIFT 10
#define AIPS_PACRN_TP4_MASK 0x1000u
#define AIPS_PACRN_TP4_SHIFT 12
#define AIPS_PACRN_WP4_MASK 0x2000u
#define AIPS_PACRN_WP4_SHIFT 13
#define AIPS_PACRN_SP4_MASK 0x4000u
#define AIPS_PACRN_SP4_SHIFT 14
#define AIPS_PACRN_TP3_MASK 0x10000u
#define AIPS_PACRN_TP3_SHIFT 16
#define AIPS_PACRN_WP3_MASK 0x20000u
#define AIPS_PACRN_WP3_SHIFT 17
#define AIPS_PACRN_SP3_MASK 0x40000u
#define AIPS_PACRN_SP3_SHIFT 18
#define AIPS_PACRN_TP2_MASK 0x100000u
#define AIPS_PACRN_TP2_SHIFT 20
#define AIPS_PACRN_WP2_MASK 0x200000u
#define AIPS_PACRN_WP2_SHIFT 21
#define AIPS_PACRN_SP2_MASK 0x400000u
#define AIPS_PACRN_SP2_SHIFT 22
#define AIPS_PACRN_TP1_MASK 0x1000000u
#define AIPS_PACRN_TP1_SHIFT 24
#define AIPS_PACRN_WP1_MASK 0x2000000u
#define AIPS_PACRN_WP1_SHIFT 25
#define AIPS_PACRN_SP1_MASK 0x4000000u
#define AIPS_PACRN_SP1_SHIFT 26
#define AIPS_PACRN_TP0_MASK 0x10000000u
#define AIPS_PACRN_TP0_SHIFT 28
#define AIPS_PACRN_WP0_MASK 0x20000000u
#define AIPS_PACRN_WP0_SHIFT 29
#define AIPS_PACRN_SP0_MASK 0x40000000u
#define AIPS_PACRN_SP0_SHIFT 30
/* PACRO Bit Fields */
#define AIPS_PACRO_TP7_MASK 0x1u
#define AIPS_PACRO_TP7_SHIFT 0
#define AIPS_PACRO_WP7_MASK 0x2u
#define AIPS_PACRO_WP7_SHIFT 1
#define AIPS_PACRO_SP7_MASK 0x4u
#define AIPS_PACRO_SP7_SHIFT 2
#define AIPS_PACRO_TP6_MASK 0x10u
#define AIPS_PACRO_TP6_SHIFT 4
#define AIPS_PACRO_WP6_MASK 0x20u
#define AIPS_PACRO_WP6_SHIFT 5
#define AIPS_PACRO_SP6_MASK 0x40u
#define AIPS_PACRO_SP6_SHIFT 6
#define AIPS_PACRO_TP5_MASK 0x100u
#define AIPS_PACRO_TP5_SHIFT 8
#define AIPS_PACRO_WP5_MASK 0x200u
#define AIPS_PACRO_WP5_SHIFT 9
#define AIPS_PACRO_SP5_MASK 0x400u
#define AIPS_PACRO_SP5_SHIFT 10
#define AIPS_PACRO_TP4_MASK 0x1000u
#define AIPS_PACRO_TP4_SHIFT 12
#define AIPS_PACRO_WP4_MASK 0x2000u
#define AIPS_PACRO_WP4_SHIFT 13
#define AIPS_PACRO_SP4_MASK 0x4000u
#define AIPS_PACRO_SP4_SHIFT 14
#define AIPS_PACRO_TP3_MASK 0x10000u
#define AIPS_PACRO_TP3_SHIFT 16
#define AIPS_PACRO_WP3_MASK 0x20000u
#define AIPS_PACRO_WP3_SHIFT 17
#define AIPS_PACRO_SP3_MASK 0x40000u
#define AIPS_PACRO_SP3_SHIFT 18
#define AIPS_PACRO_TP2_MASK 0x100000u
#define AIPS_PACRO_TP2_SHIFT 20
#define AIPS_PACRO_WP2_MASK 0x200000u
#define AIPS_PACRO_WP2_SHIFT 21
#define AIPS_PACRO_SP2_MASK 0x400000u
#define AIPS_PACRO_SP2_SHIFT 22
#define AIPS_PACRO_TP1_MASK 0x1000000u
#define AIPS_PACRO_TP1_SHIFT 24
#define AIPS_PACRO_WP1_MASK 0x2000000u
#define AIPS_PACRO_WP1_SHIFT 25
#define AIPS_PACRO_SP1_MASK 0x4000000u
#define AIPS_PACRO_SP1_SHIFT 26
#define AIPS_PACRO_TP0_MASK 0x10000000u
#define AIPS_PACRO_TP0_SHIFT 28
#define AIPS_PACRO_WP0_MASK 0x20000000u
#define AIPS_PACRO_WP0_SHIFT 29
#define AIPS_PACRO_SP0_MASK 0x40000000u
#define AIPS_PACRO_SP0_SHIFT 30
/* PACRP Bit Fields */
#define AIPS_PACRP_TP7_MASK 0x1u
#define AIPS_PACRP_TP7_SHIFT 0
#define AIPS_PACRP_WP7_MASK 0x2u
#define AIPS_PACRP_WP7_SHIFT 1
#define AIPS_PACRP_SP7_MASK 0x4u
#define AIPS_PACRP_SP7_SHIFT 2
#define AIPS_PACRP_TP6_MASK 0x10u
#define AIPS_PACRP_TP6_SHIFT 4
#define AIPS_PACRP_WP6_MASK 0x20u
#define AIPS_PACRP_WP6_SHIFT 5
#define AIPS_PACRP_SP6_MASK 0x40u
#define AIPS_PACRP_SP6_SHIFT 6
#define AIPS_PACRP_TP5_MASK 0x100u
#define AIPS_PACRP_TP5_SHIFT 8
#define AIPS_PACRP_WP5_MASK 0x200u
#define AIPS_PACRP_WP5_SHIFT 9
#define AIPS_PACRP_SP5_MASK 0x400u
#define AIPS_PACRP_SP5_SHIFT 10
#define AIPS_PACRP_TP4_MASK 0x1000u
#define AIPS_PACRP_TP4_SHIFT 12
#define AIPS_PACRP_WP4_MASK 0x2000u
#define AIPS_PACRP_WP4_SHIFT 13
#define AIPS_PACRP_SP4_MASK 0x4000u
#define AIPS_PACRP_SP4_SHIFT 14
#define AIPS_PACRP_TP3_MASK 0x10000u
#define AIPS_PACRP_TP3_SHIFT 16
#define AIPS_PACRP_WP3_MASK 0x20000u
#define AIPS_PACRP_WP3_SHIFT 17
#define AIPS_PACRP_SP3_MASK 0x40000u
#define AIPS_PACRP_SP3_SHIFT 18
#define AIPS_PACRP_TP2_MASK 0x100000u
#define AIPS_PACRP_TP2_SHIFT 20
#define AIPS_PACRP_WP2_MASK 0x200000u
#define AIPS_PACRP_WP2_SHIFT 21
#define AIPS_PACRP_SP2_MASK 0x400000u
#define AIPS_PACRP_SP2_SHIFT 22
#define AIPS_PACRP_TP1_MASK 0x1000000u
#define AIPS_PACRP_TP1_SHIFT 24
#define AIPS_PACRP_WP1_MASK 0x2000000u
#define AIPS_PACRP_WP1_SHIFT 25
#define AIPS_PACRP_SP1_MASK 0x4000000u
#define AIPS_PACRP_SP1_SHIFT 26
#define AIPS_PACRP_TP0_MASK 0x10000000u
#define AIPS_PACRP_TP0_SHIFT 28
#define AIPS_PACRP_WP0_MASK 0x20000000u
#define AIPS_PACRP_WP0_SHIFT 29
#define AIPS_PACRP_SP0_MASK 0x40000000u
#define AIPS_PACRP_SP0_SHIFT 30
/**
* @}
*/ /* end of group AIPS_Register_Masks */
/* AIPS - Peripheral instance base addresses */
/** Peripheral AIPS0 base address */
#define AIPS0_BASE (0x40000000u)
/** Peripheral AIPS0 base pointer */
#define AIPS0 ((AIPS_Type *)AIPS0_BASE)
/** Peripheral AIPS1 base address */
#define AIPS1_BASE (0x40080000u)
/** Peripheral AIPS1 base pointer */
#define AIPS1 ((AIPS_Type *)AIPS1_BASE)
/**
* @}
*/ /* end of group AIPS_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- AXBS Peripheral Access Layer
---------------------------------------------------------------------------- */
/**
* @addtogroup AXBS_Peripheral_Access_Layer AXBS Peripheral Access Layer
* @{
*/
/** AXBS - Register Layout Typedef */
typedef struct {
struct { /* offset: 0x0, array step: 0x100 */
__IO uint32_t PRS; /**< Priority Registers Slave, array offset: 0x0, array step: 0x100 */
uint8_t RESERVED_0[12];
__IO uint32_t CRS; /**< Control Register, array offset: 0x10, array step: 0x100 */
uint8_t RESERVED_1[236];
} SLAVE[5];
uint8_t RESERVED_0[768];
__IO uint32_t MGPCR0; /**< Master General Purpose Control Register, offset: 0x800 */
uint8_t RESERVED_1[252];
__IO uint32_t MGPCR1; /**< Master General Purpose Control Register, offset: 0x900 */
uint8_t RESERVED_2[252];
__IO uint32_t MGPCR2; /**< Master General Purpose Control Register, offset: 0xA00 */
uint8_t RESERVED_3[252];
__IO uint32_t MGPCR3; /**< Master General Purpose Control Register, offset: 0xB00 */
uint8_t RESERVED_4[252];
__IO uint32_t MGPCR4; /**< Master General Purpose Control Register, offset: 0xC00 */
uint8_t RESERVED_5[252];
__IO uint32_t MGPCR5; /**< Master General Purpose Control Register, offset: 0xD00 */
} AXBS_Type;
/* ----------------------------------------------------------------------------
-- AXBS Register Masks
---------------------------------------------------------------------------- */
/**
* @addtogroup AXBS_Register_Masks AXBS Register Masks
* @{
*/
/* PRS Bit Fields */
#define AXBS_PRS_M0_MASK 0x7u
#define AXBS_PRS_M0_SHIFT 0
#define AXBS_PRS_M0(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M0_SHIFT))&AXBS_PRS_M0_MASK)
#define AXBS_PRS_M1_MASK 0x70u
#define AXBS_PRS_M1_SHIFT 4
#define AXBS_PRS_M1(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M1_SHIFT))&AXBS_PRS_M1_MASK)
#define AXBS_PRS_M2_MASK 0x700u
#define AXBS_PRS_M2_SHIFT 8
#define AXBS_PRS_M2(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M2_SHIFT))&AXBS_PRS_M2_MASK)
#define AXBS_PRS_M3_MASK 0x7000u
#define AXBS_PRS_M3_SHIFT 12
#define AXBS_PRS_M3(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M3_SHIFT))&AXBS_PRS_M3_MASK)
#define AXBS_PRS_M4_MASK 0x70000u
#define AXBS_PRS_M4_SHIFT 16
#define AXBS_PRS_M4(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M4_SHIFT))&AXBS_PRS_M4_MASK)
#define AXBS_PRS_M5_MASK 0x700000u
#define AXBS_PRS_M5_SHIFT 20
#define AXBS_PRS_M5(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M5_SHIFT))&AXBS_PRS_M5_MASK)
/* CRS Bit Fields */
#define AXBS_CRS_PARK_MASK 0x7u
#define AXBS_CRS_PARK_SHIFT 0
#define AXBS_CRS_PARK(x) (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_PARK_SHIFT))&AXBS_CRS_PARK_MASK)
#define AXBS_CRS_PCTL_MASK 0x30u
#define AXBS_CRS_PCTL_SHIFT 4
#define AXBS_CRS_PCTL(x) (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_PCTL_SHIFT))&AXBS_CRS_PCTL_MASK)
#define AXBS_CRS_ARB_MASK 0x300u
#define AXBS_CRS_ARB_SHIFT 8
#define AXBS_CRS_ARB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_ARB_SHIFT))&AXBS_CRS_ARB_MASK)
#define AXBS_CRS_HLP_MASK 0x40000000u
#define AXBS_CRS_HLP_SHIFT 30
#define AXBS_CRS_RO_MASK 0x80000000u
#define AXBS_CRS_RO_SHIFT 31
/* MGPCR0 Bit Fields */
#define AXBS_MGPCR0_AULB_MASK 0x7u
#define AXBS_MGPCR0_AULB_SHIFT 0
#define AXBS_MGPCR0_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR0_AULB_SHIFT))&AXBS_MGPCR0_AULB_MASK)
/* MGPCR1 Bit Fields */
#define AXBS_MGPCR1_AULB_MASK 0x7u
#define AXBS_MGPCR1_AULB_SHIFT 0
#define AXBS_MGPCR1_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR1_AULB_SHIFT))&AXBS_MGPCR1_AULB_MASK)
/* MGPCR2 Bit Fields */
#define AXBS_MGPCR2_AULB_MASK 0x7u
#define AXBS_MGPCR2_AULB_SHIFT 0
#define AXBS_MGPCR2_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR2_AULB_SHIFT))&AXBS_MGPCR2_AULB_MASK)
/* MGPCR3 Bit Fields */
#define AXBS_MGPCR3_AULB_MASK 0x7u
#define AXBS_MGPCR3_AULB_SHIFT 0
#define AXBS_MGPCR3_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR3_AULB_SHIFT))&AXBS_MGPCR3_AULB_MASK)
/* MGPCR4 Bit Fields */
#define AXBS_MGPCR4_AULB_MASK 0x7u
#define AXBS_MGPCR4_AULB_SHIFT 0
#define AXBS_MGPCR4_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR4_AULB_SHIFT))&AXBS_MGPCR4_AULB_MASK)
/* MGPCR5 Bit Fields */
#define AXBS_MGPCR5_AULB_MASK 0x7u
#define AXBS_MGPCR5_AULB_SHIFT 0
#define AXBS_MGPCR5_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR5_AULB_SHIFT))&AXBS_MGPCR5_AULB_MASK)
/**
* @}
*/ /* end of group AXBS_Register_Masks */
/* AXBS - Peripheral instance base addresses */
/** Peripheral AXBS base address */
#define AXBS_BASE (0x40004000u)
/** Peripheral AXBS base pointer */
#define AXBS ((AXBS_Type *)AXBS_BASE)
/**
* @}
*/ /* end of group AXBS_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- CAN Peripheral Access Layer
---------------------------------------------------------------------------- */
/**
* @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
* @{
*/
/** CAN - Register Layout Typedef */
typedef struct {
__IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
__IO uint32_t CTRL1; /**< Control 1 Register, offset: 0x4 */
__IO uint32_t TIMER; /**< Free Running Timer, offset: 0x8 */
uint8_t RESERVED_0[4];
__IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask Register, offset: 0x10 */
__IO uint32_t RX14MASK; /**< Rx 14 Mask Register, offset: 0x14 */
__IO uint32_t RX15MASK; /**< Rx 15 Mask Register, offset: 0x18 */
__IO uint32_t ECR; /**< Error Counter, offset: 0x1C */
__IO uint32_t ESR1; /**< Error and Status 1 Register, offset: 0x20 */
__IO uint32_t IMASK2; /**< Interrupt Masks 2 Register, offset: 0x24 */
__IO uint32_t IMASK1; /**< Interrupt Masks 1 Register, offset: 0x28 */
__IO uint32_t IFLAG2; /**< Interrupt Flags 2 Register, offset: 0x2C */
__IO uint32_t IFLAG1; /**< Interrupt Flags 1 Register, offset: 0x30 */
__IO uint32_t CTRL2; /**< Control 2 Register, offset: 0x34 */
__I uint32_t ESR2; /**< Error and Status 2 Register, offset: 0x38 */
uint8_t RESERVED_1[8];
__I uint32_t CRCR; /**< CRC Register, offset: 0x44 */
__IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask Register, offset: 0x48 */
__I uint32_t RXFIR; /**< Rx FIFO Information Register, offset: 0x4C */
uint8_t RESERVED_2[48];
struct { /* offset: 0x80, array step: 0x10 */
__IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 15 CS Register, array offset: 0x80, array step: 0x10 */
__IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 15 ID Register, array offset: 0x84, array step: 0x10 */
__IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register, array offset: 0x88, array step: 0x10 */
__IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register, array offset: 0x8C, array step: 0x10 */
} MB[16];
uint8_t RESERVED_3[1792];
__IO uint32_t RXIMR[16]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */
} CAN_Type;
/* ----------------------------------------------------------------------------
-- CAN Register Masks
---------------------------------------------------------------------------- */
/**
* @addtogroup CAN_Register_Masks CAN Register Masks
* @{
*/
/* MCR Bit Fields */
#define CAN_MCR_MAXMB_MASK 0x7Fu
#define CAN_MCR_MAXMB_SHIFT 0
#define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_MAXMB_SHIFT))&CAN_MCR_MAXMB_MASK)
#define CAN_MCR_IDAM_MASK 0x300u
#define CAN_MCR_IDAM_SHIFT 8
#define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_IDAM_SHIFT))&CAN_MCR_IDAM_MASK)
#define CAN_MCR_AEN_MASK 0x1000u
#define CAN_MCR_AEN_SHIFT 12
#define CAN_MCR_LPRIOEN_MASK 0x2000u
#define CAN_MCR_LPRIOEN_SHIFT 13
#define CAN_MCR_IRMQ_MASK 0x10000u
#define CAN_MCR_IRMQ_SHIFT 16
#define CAN_MCR_SRXDIS_MASK 0x20000u
#define CAN_MCR_SRXDIS_SHIFT 17
#define CAN_MCR_DOZE_MASK 0x40000u
#define CAN_MCR_DOZE_SHIFT 18
#define CAN_MCR_LPMACK_MASK 0x100000u
#define CAN_MCR_LPMACK_SHIFT 20
#define CAN_MCR_WRNEN_MASK 0x200000u
#define CAN_MCR_WRNEN_SHIFT 21
#define CAN_MCR_SLFWAK_MASK 0x400000u
#define CAN_MCR_SLFWAK_SHIFT 22
#define CAN_MCR_SUPV_MASK 0x800000u
#define CAN_MCR_SUPV_SHIFT 23
#define CAN_MCR_FRZACK_MASK 0x1000000u
#define CAN_MCR_FRZACK_SHIFT 24
#define CAN_MCR_SOFTRST_MASK 0x2000000u
#define CAN_MCR_SOFTRST_SHIFT 25
#define CAN_MCR_WAKMSK_MASK 0x4000000u
#define CAN_MCR_WAKMSK_SHIFT 26
#define CAN_MCR_NOTRDY_MASK 0x8000000u
#define CAN_MCR_NOTRDY_SHIFT 27
#define CAN_MCR_HALT_MASK 0x10000000u
#define CAN_MCR_HALT_SHIFT 28
#define CAN_MCR_RFEN_MASK 0x20000000u
#define CAN_MCR_RFEN_SHIFT 29
#define CAN_MCR_FRZ_MASK 0x40000000u
#define CAN_MCR_FRZ_SHIFT 30
#define CAN_MCR_MDIS_MASK 0x80000000u
#define CAN_MCR_MDIS_SHIFT 31
/* CTRL1 Bit Fields */
#define CAN_CTRL1_PROPSEG_MASK 0x7u
#define CAN_CTRL1_PROPSEG_SHIFT 0
#define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PROPSEG_SHIFT))&CAN_CTRL1_PROPSEG_MASK)
#define CAN_CTRL1_LOM_MASK 0x8u
#define CAN_CTRL1_LOM_SHIFT 3
#define CAN_CTRL1_LBUF_MASK 0x10u
#define CAN_CTRL1_LBUF_SHIFT 4
#define CAN_CTRL1_TSYN_MASK 0x20u
#define CAN_CTRL1_TSYN_SHIFT 5
#define CAN_CTRL1_BOFFREC_MASK 0x40u
#define CAN_CTRL1_BOFFREC_SHIFT 6
#define CAN_CTRL1_SMP_MASK 0x80u
#define CAN_CTRL1_SMP_SHIFT 7
#define CAN_CTRL1_RWRNMSK_MASK 0x400u
#define CAN_CTRL1_RWRNMSK_SHIFT 10
#define CAN_CTRL1_TWRNMSK_MASK 0x800u
#define CAN_CTRL1_TWRNMSK_SHIFT 11
#define CAN_CTRL1_LPB_MASK 0x1000u
#define CAN_CTRL1_LPB_SHIFT 12
#define CAN_CTRL1_CLKSRC_MASK 0x2000u
#define CAN_CTRL1_CLKSRC_SHIFT 13
#define CAN_CTRL1_ERRMSK_MASK 0x4000u
#define CAN_CTRL1_ERRMSK_SHIFT 14
#define CAN_CTRL1_BOFFMSK_MASK 0x8000u
#define CAN_CTRL1_BOFFMSK_SHIFT 15
#define CAN_CTRL1_PSEG2_MASK 0x70000u
#define CAN_CTRL1_PSEG2_SHIFT 16
#define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG2_SHIFT))&CAN_CTRL1_PSEG2_MASK)
#define CAN_CTRL1_PSEG1_MASK 0x380000u
#define CAN_CTRL1_PSEG1_SHIFT 19
#define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG1_SHIFT))&CAN_CTRL1_PSEG1_MASK)
#define CAN_CTRL1_RJW_MASK 0xC00000u
#define CAN_CTRL1_RJW_SHIFT 22
#define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_RJW_SHIFT))&CAN_CTRL1_RJW_MASK)
#define CAN_CTRL1_PRESDIV_MASK 0xFF000000u
#define CAN_CTRL1_PRESDIV_SHIFT 24
#define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PRESDIV_SHIFT))&CAN_CTRL1_PRESDIV_MASK)
/* TIMER Bit Fields */
#define CAN_TIMER_TIMER_MASK 0xFFFFu
#define CAN_TIMER_TIMER_SHIFT 0
#define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x))<<CAN_TIMER_TIMER_SHIFT))&CAN_TIMER_TIMER_MASK)
/* RXMGMASK Bit Fields */
#define CAN_RXMGMASK_MG_MASK 0xFFFFFFFFu
#define CAN_RXMGMASK_MG_SHIFT 0
#define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXMGMASK_MG_SHIFT))&CAN_RXMGMASK_MG_MASK)
/* RX14MASK Bit Fields */
#define CAN_RX14MASK_RX14M_MASK 0xFFFFFFFFu
#define CAN_RX14MASK_RX14M_SHIFT 0
#define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x))<<CAN_RX14MASK_RX14M_SHIFT))&CAN_RX14MASK_RX14M_MASK)
/* RX15MASK Bit Fields */
#define CAN_RX15MASK_RX15M_MASK 0xFFFFFFFFu
#define CAN_RX15MASK_RX15M_SHIFT 0
#define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x))<<CAN_RX15MASK_RX15M_SHIFT))&CAN_RX15MASK_RX15M_MASK)
/* ECR Bit Fields */
#define CAN_ECR_TXERRCNT_MASK 0xFFu
#define CAN_ECR_TXERRCNT_SHIFT 0
#define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ECR_TXERRCNT_SHIFT))&CAN_ECR_TXERRCNT_MASK)
#define CAN_ECR_RXERRCNT_MASK 0xFF00u
#define CAN_ECR_RXERRCNT_SHIFT 8
#define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ECR_RXERRCNT_SHIFT))&CAN_ECR_RXERRCNT_MASK)
/* ESR1 Bit Fields */
#define CAN_ESR1_WAKINT_MASK 0x1u
#define CAN_ESR1_WAKINT_SHIFT 0
#define CAN_ESR1_ERRINT_MASK 0x2u
#define CAN_ESR1_ERRINT_SHIFT 1
#define CAN_ESR1_BOFFINT_MASK 0x4u
#define CAN_ESR1_BOFFINT_SHIFT 2
#define CAN_ESR1_RX_MASK 0x8u
#define CAN_ESR1_RX_SHIFT 3
#define CAN_ESR1_FLTCONF_MASK 0x30u
#define CAN_ESR1_FLTCONF_SHIFT 4
#define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_FLTCONF_SHIFT))&CAN_ESR1_FLTCONF_MASK)
#define CAN_ESR1_TX_MASK 0x40u
#define CAN_ESR1_TX_SHIFT 6
#define CAN_ESR1_IDLE_MASK 0x80u
#define CAN_ESR1_IDLE_SHIFT 7
#define CAN_ESR1_RXWRN_MASK 0x100u
#define CAN_ESR1_RXWRN_SHIFT 8
#define CAN_ESR1_TXWRN_MASK 0x200u
#define CAN_ESR1_TXWRN_SHIFT 9
#define CAN_ESR1_STFERR_MASK 0x400u
#define CAN_ESR1_STFERR_SHIFT 10
#define CAN_ESR1_FRMERR_MASK 0x800u
#define CAN_ESR1_FRMERR_SHIFT 11
#define CAN_ESR1_CRCERR_MASK 0x1000u
#define CAN_ESR1_CRCERR_SHIFT 12
#define CAN_ESR1_ACKERR_MASK 0x2000u
#define CAN_ESR1_ACKERR_SHIFT 13
#define CAN_ESR1_BIT0ERR_MASK 0x4000u
#define CAN_ESR1_BIT0ERR_SHIFT 14
#define CAN_ESR1_BIT1ERR_MASK 0x8000u
#define CAN_ESR1_BIT1ERR_SHIFT 15
#define CAN_ESR1_RWRNINT_MASK 0x10000u
#define CAN_ESR1_RWRNINT_SHIFT 16
#define CAN_ESR1_TWRNINT_MASK 0x20000u
#define CAN_ESR1_TWRNINT_SHIFT 17
#define CAN_ESR1_SYNCH_MASK 0x40000u
#define CAN_ESR1_SYNCH_SHIFT 18
/* IMASK2 Bit Fields */
#define CAN_IMASK2_BUFHM_MASK 0xFFFFFFFFu
#define CAN_IMASK2_BUFHM_SHIFT 0
#define CAN_IMASK2_BUFHM(x) (((uint32_t)(((uint32_t)(x))<<CAN_IMASK2_BUFHM_SHIFT))&CAN_IMASK2_BUFHM_MASK)
/* IMASK1 Bit Fields */
#define CAN_IMASK1_BUFLM_MASK 0xFFFFFFFFu
#define CAN_IMASK1_BUFLM_SHIFT 0
#define CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x))<<CAN_IMASK1_BUFLM_SHIFT))&CAN_IMASK1_BUFLM_MASK)
/* IFLAG2 Bit Fields */
#define CAN_IFLAG2_BUFHI_MASK 0xFFFFFFFFu
#define CAN_IFLAG2_BUFHI_SHIFT 0
#define CAN_IFLAG2_BUFHI(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG2_BUFHI_SHIFT))&CAN_IFLAG2_BUFHI_MASK)
/* IFLAG1 Bit Fields */
#define CAN_IFLAG1_BUF4TO0I_MASK 0x1Fu
#define CAN_IFLAG1_BUF4TO0I_SHIFT 0
#define CAN_IFLAG1_BUF4TO0I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF4TO0I_SHIFT))&CAN_IFLAG1_BUF4TO0I_MASK)
#define CAN_IFLAG1_BUF5I_MASK 0x20u
#define CAN_IFLAG1_BUF5I_SHIFT 5
#define CAN_IFLAG1_BUF6I_MASK 0x40u
#define CAN_IFLAG1_BUF6I_SHIFT 6
#define CAN_IFLAG1_BUF7I_MASK 0x80u
#define CAN_IFLAG1_BUF7I_SHIFT 7
#define CAN_IFLAG1_BUF31TO8I_MASK 0xFFFFFF00u
#define CAN_IFLAG1_BUF31TO8I_SHIFT 8
#define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF31TO8I_SHIFT))&CAN_IFLAG1_BUF31TO8I_MASK)
/* CTRL2 Bit Fields */
#define CAN_CTRL2_EACEN_MASK 0x10000u
#define CAN_CTRL2_EACEN_SHIFT 16
#define CAN_CTRL2_RRS_MASK 0x20000u
#define CAN_CTRL2_RRS_SHIFT 17
#define CAN_CTRL2_MRP_MASK 0x40000u
#define CAN_CTRL2_MRP_SHIFT 18
#define CAN_CTRL2_TASD_MASK 0xF80000u
#define CAN_CTRL2_TASD_SHIFT 19
#define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_TASD_SHIFT))&CAN_CTRL2_TASD_MASK)
#define CAN_CTRL2_RFFN_MASK 0xF000000u
#define CAN_CTRL2_RFFN_SHIFT 24
#define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_RFFN_SHIFT))&CAN_CTRL2_RFFN_MASK)
#define CAN_CTRL2_WRMFRZ_MASK 0x10000000u
#define CAN_CTRL2_WRMFRZ_SHIFT 28
/* ESR2 Bit Fields */
#define CAN_ESR2_IMB_MASK 0x2000u
#define CAN_ESR2_IMB_SHIFT 13
#define CAN_ESR2_VPS_MASK 0x4000u
#define CAN_ESR2_VPS_SHIFT 14
#define CAN_ESR2_LPTM_MASK 0x7F0000u
#define CAN_ESR2_LPTM_SHIFT 16
#define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_LPTM_SHIFT))&CAN_ESR2_LPTM_MASK)
/* CRCR Bit Fields */
#define CAN_CRCR_TXCRC_MASK 0x7FFFu
#define CAN_CRCR_TXCRC_SHIFT 0
#define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_TXCRC_SHIFT))&CAN_CRCR_TXCRC_MASK)
#define CAN_CRCR_MBCRC_MASK 0x7F0000u
#define CAN_CRCR_MBCRC_SHIFT 16
#define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_MBCRC_SHIFT))&CAN_CRCR_MBCRC_MASK)
/* RXFGMASK Bit Fields */
#define CAN_RXFGMASK_FGM_MASK 0xFFFFFFFFu
#define CAN_RXFGMASK_FGM_SHIFT 0
#define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXFGMASK_FGM_SHIFT))&CAN_RXFGMASK_FGM_MASK)
/* RXFIR Bit Fields */
#define CAN_RXFIR_IDHIT_MASK 0x1FFu
#define CAN_RXFIR_IDHIT_SHIFT 0
#define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXFIR_IDHIT_SHIFT))&CAN_RXFIR_IDHIT_MASK)
/* CS Bit Fields */
#define CAN_CS_TIME_STAMP_MASK 0xFFFFu
#define CAN_CS_TIME_STAMP_SHIFT 0
#define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_TIME_STAMP_SHIFT))&CAN_CS_TIME_STAMP_MASK)
#define CAN_CS_DLC_MASK 0xF0000u
#define CAN_CS_DLC_SHIFT 16
#define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_DLC_SHIFT))&CAN_CS_DLC_MASK)
#define CAN_CS_RTR_MASK 0x100000u
#define CAN_CS_RTR_SHIFT 20
#define CAN_CS_IDE_MASK 0x200000u
#define CAN_CS_IDE_SHIFT 21
#define CAN_CS_SRR_MASK 0x400000u
#define CAN_CS_SRR_SHIFT 22
#define CAN_CS_CODE_MASK 0xF000000u
#define CAN_CS_CODE_SHIFT 24
#define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_CODE_SHIFT))&CAN_CS_CODE_MASK)
/* ID Bit Fields */
#define CAN_ID_EXT_MASK 0x3FFFFu
#define CAN_ID_EXT_SHIFT 0
#define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_EXT_SHIFT))&CAN_ID_EXT_MASK)
#define CAN_ID_STD_MASK 0x1FFC0000u
#define CAN_ID_STD_SHIFT 18
#define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_STD_SHIFT))&CAN_ID_STD_MASK)
#define CAN_ID_PRIO_MASK 0xE0000000u
#define CAN_ID_PRIO_SHIFT 29
#define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_PRIO_SHIFT))&CAN_ID_PRIO_MASK)
/* WORD0 Bit Fields */
#define CAN_WORD0_DATA_BYTE_3_MASK 0xFFu
#define CAN_WORD0_DATA_BYTE_3_SHIFT 0
#define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_3_SHIFT))&CAN_WORD0_DATA_BYTE_3_MASK)
#define CAN_WORD0_DATA_BYTE_2_MASK 0xFF00u
#define CAN_WORD0_DATA_BYTE_2_SHIFT 8
#define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_2_SHIFT))&CAN_WORD0_DATA_BYTE_2_MASK)
#define CAN_WORD0_DATA_BYTE_1_MASK 0xFF0000u
#define CAN_WORD0_DATA_BYTE_1_SHIFT 16
#define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_1_SHIFT))&CAN_WORD0_DATA_BYTE_1_MASK)
#define CAN_WORD0_DATA_BYTE_0_MASK 0xFF000000u
#define CAN_WORD0_DATA_BYTE_0_SHIFT 24
#define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_0_SHIFT))&CAN_WORD0_DATA_BYTE_0_MASK)
/* WORD1 Bit Fields */
#define CAN_WORD1_DATA_BYTE_7_MASK 0xFFu
#define CAN_WORD1_DATA_BYTE_7_SHIFT 0
#define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_7_SHIFT))&CAN_WORD1_DATA_BYTE_7_MASK)
#define CAN_WORD1_DATA_BYTE_6_MASK 0xFF00u
#define CAN_WORD1_DATA_BYTE_6_SHIFT 8
#define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_6_SHIFT))&CAN_WORD1_DATA_BYTE_6_MASK)
#define CAN_WORD1_DATA_BYTE_5_MASK 0xFF0000u
#define CAN_WORD1_DATA_BYTE_5_SHIFT 16
#define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_5_SHIFT))&CAN_WORD1_DATA_BYTE_5_MASK)
#define CAN_WORD1_DATA_BYTE_4_MASK 0xFF000000u
#define CAN_WORD1_DATA_BYTE_4_SHIFT 24
#define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_4_SHIFT))&CAN_WORD1_DATA_BYTE_4_MASK)
/* RXIMR Bit Fields */
#define CAN_RXIMR_MI_MASK 0xFFFFFFFFu
#define CAN_RXIMR_MI_SHIFT 0
#define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXIMR_MI_SHIFT))&CAN_RXIMR_MI_MASK)
/**
* @}
*/ /* end of group CAN_Register_Masks */
/* CAN - Peripheral instance base addresses */
/** Peripheral CAN0 base address */
#define CAN0_BASE (0x40024000u)
/** Peripheral CAN0 base pointer */
#define CAN0 ((CAN_Type *)CAN0_BASE)
/** Peripheral CAN1 base address */
#define CAN1_BASE (0x400A4000u)
/** Peripheral CAN1 base pointer */
#define CAN1 ((CAN_Type *)CAN1_BASE)
/**
* @}
*/ /* end of group CAN_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- CAU Peripheral Access Layer
---------------------------------------------------------------------------- */
/**
* @addtogroup CAU_Peripheral_Access_Layer CAU Peripheral Access Layer
* @{
*/
/** CAU - Register Layout Typedef */
typedef struct {
__O uint32_t DIRECT[16]; /**< Direct access register 0..Direct access register 15, array offset: 0x0, array step: 0x4 */
uint8_t RESERVED_0[2048];
__O uint32_t LDR_CASR; /**< Status register - Load Register command, offset: 0x840 */
__O uint32_t LDR_CAA; /**< Accumulator register - Load Register command, offset: 0x844 */
__O uint32_t LDR_CA[9]; /**< General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command, array offset: 0x848, array step: 0x4 */
uint8_t RESERVED_1[20];
__I uint32_t STR_CASR; /**< Status register - Store Register command, offset: 0x880 */
__I uint32_t STR_CAA; /**< Accumulator register - Store Register command, offset: 0x884 */
__I uint32_t STR_CA[9]; /**< General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command, array offset: 0x888, array step: 0x4 */
uint8_t RESERVED_2[20];
__O uint32_t ADR_CASR; /**< Status register - Add Register command, offset: 0x8C0 */
__O uint32_t ADR_CAA; /**< Accumulator register - Add to register command, offset: 0x8C4 */
__O uint32_t ADR_CA[9]; /**< General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command, array offset: 0x8C8, array step: 0x4 */
uint8_t RESERVED_3[20];
__O uint32_t RADR_CASR; /**< Status register - Reverse and Add to Register command, offset: 0x900 */
__O uint32_t RADR_CAA; /**< Accumulator register - Reverse and Add to Register command, offset: 0x904 */
__O uint32_t RADR_CA[9]; /**< General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command, array offset: 0x908, array step: 0x4 */
uint8_t RESERVED_4[84];
__O uint32_t XOR_CASR; /**< Status register - Exclusive Or command, offset: 0x980 */
__O uint32_t XOR_CAA; /**< Accumulator register - Exclusive Or command, offset: 0x984 */
__O uint32_t XOR_CA[9]; /**< General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command, array offset: 0x988, array step: 0x4 */
uint8_t RESERVED_5[20];
__O uint32_t ROTL_CASR; /**< Status register - Rotate Left command, offset: 0x9C0 */
__O uint32_t ROTL_CAA; /**< Accumulator register - Rotate Left command, offset: 0x9C4 */
__O uint32_t ROTL_CA[9]; /**< General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command, array offset: 0x9C8, array step: 0x4 */
uint8_t RESERVED_6[276];
__O uint32_t AESC_CASR; /**< Status register - AES Column Operation command, offset: 0xB00 */
__O uint32_t AESC_CAA; /**< Accumulator register - AES Column Operation command, offset: 0xB04 */
__O uint32_t AESC_CA[9]; /**< General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command, array offset: 0xB08, array step: 0x4 */
uint8_t RESERVED_7[20];
__O uint32_t AESIC_CASR; /**< Status register - AES Inverse Column Operation command, offset: 0xB40 */
__O uint32_t AESIC_CAA; /**< Accumulator register - AES Inverse Column Operation command, offset: 0xB44 */
__O uint32_t AESIC_CA[9]; /**< General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command, array offset: 0xB48, array step: 0x4 */
} CAU_Type;
/* ----------------------------------------------------------------------------
-- CAU Register Masks
---------------------------------------------------------------------------- */
/**
* @addtogroup CAU_Register_Masks CAU Register Masks
* @{
*/
/* LDR_CASR Bit Fields */
#define CAU_LDR_CASR_IC_MASK 0x1u
#define CAU_LDR_CASR_IC_SHIFT 0
#define CAU_LDR_CASR_DPE_MASK 0x2u
#define CAU_LDR_CASR_DPE_SHIFT 1
#define CAU_LDR_CASR_VER_MASK 0xF0000000u
#define CAU_LDR_CASR_VER_SHIFT 28
#define CAU_LDR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CASR_VER_SHIFT))&CAU_LDR_CASR_VER_MASK)
/* STR_CASR Bit Fields */
#define CAU_STR_CASR_IC_MASK 0x1u
#define CAU_STR_CASR_IC_SHIFT 0
#define CAU_STR_CASR_DPE_MASK 0x2u
#define CAU_STR_CASR_DPE_SHIFT 1
#define CAU_STR_CASR_VER_MASK 0xF0000000u
#define CAU_STR_CASR_VER_SHIFT 28
#define CAU_STR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CASR_VER_SHIFT))&CAU_STR_CASR_VER_MASK)
/* ADR_CASR Bit Fields */
#define CAU_ADR_CASR_IC_MASK 0x1u
#define CAU_ADR_CASR_IC_SHIFT 0
#define CAU_ADR_CASR_DPE_MASK 0x2u
#define CAU_ADR_CASR_DPE_SHIFT 1
#define CAU_ADR_CASR_VER_MASK 0xF0000000u
#define CAU_ADR_CASR_VER_SHIFT 28
#define CAU_ADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CASR_VER_SHIFT))&CAU_ADR_CASR_VER_MASK)
/* RADR_CASR Bit Fields */
#define CAU_RADR_CASR_IC_MASK 0x1u
#define CAU_RADR_CASR_IC_SHIFT 0
#define CAU_RADR_CASR_DPE_MASK 0x2u
#define CAU_RADR_CASR_DPE_SHIFT 1
#define CAU_RADR_CASR_VER_MASK 0xF0000000u
#define CAU_RADR_CASR_VER_SHIFT 28
#define CAU_RADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CASR_VER_SHIFT))&CAU_RADR_CASR_VER_MASK)
/* XOR_CASR Bit Fields */
#define CAU_XOR_CASR_IC_MASK 0x1u
#define CAU_XOR_CASR_IC_SHIFT 0
#define CAU_XOR_CASR_DPE_MASK 0x2u
#define CAU_XOR_CASR_DPE_SHIFT 1
#define CAU_XOR_CASR_VER_MASK 0xF0000000u
#define CAU_XOR_CASR_VER_SHIFT 28
#define CAU_XOR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CASR_VER_SHIFT))&CAU_XOR_CASR_VER_MASK)
/* ROTL_CASR Bit Fields */
#define CAU_ROTL_CASR_IC_MASK 0x1u
#define CAU_ROTL_CASR_IC_SHIFT 0
#define CAU_ROTL_CASR_DPE_MASK 0x2u
#define CAU_ROTL_CASR_DPE_SHIFT 1
#define CAU_ROTL_CASR_VER_MASK 0xF0000000u
#define CAU_ROTL_CASR_VER_SHIFT 28
#define CAU_ROTL_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CASR_VER_SHIFT))&CAU_ROTL_CASR_VER_MASK)
/* AESC_CASR Bit Fields */
#define CAU_AESC_CASR_IC_MASK 0x1u
#define CAU_AESC_CASR_IC_SHIFT 0
#define CAU_AESC_CASR_DPE_MASK 0x2u
#define CAU_AESC_CASR_DPE_SHIFT 1
#define CAU_AESC_CASR_VER_MASK 0xF0000000u
#define CAU_AESC_CASR_VER_SHIFT 28
#define CAU_AESC_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CASR_VER_SHIFT))&CAU_AESC_CASR_VER_MASK)
/* AESIC_CASR Bit Fields */
#define CAU_AESIC_CASR_IC_MASK 0x1u
#define CAU_AESIC_CASR_IC_SHIFT 0
#define CAU_AESIC_CASR_DPE_MASK 0x2u
#define CAU_AESIC_CASR_DPE_SHIFT 1
#define CAU_AESIC_CASR_VER_MASK 0xF0000000u
#define CAU_AESIC_CASR_VER_SHIFT 28
#define CAU_AESIC_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CASR_VER_SHIFT))&CAU_AESIC_CASR_VER_MASK)
/**
* @}
*/ /* end of group CAU_Register_Masks */
/* CAU - Peripheral instance base addresses */
/** Peripheral CAU base address */
#define CAU_BASE (0xE0081000u)
/** Peripheral CAU base pointer */
#define CAU ((CAU_Type *)CAU_BASE)
/**
* @}
*/ /* end of group CAU_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- CMP Peripheral Access Layer
---------------------------------------------------------------------------- */
/**
* @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
* @{
*/
/** CMP - Register Layout Typedef */
typedef struct {
__IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
__IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
__IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
__IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
__IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
__IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
} CMP_Type;
/* ----------------------------------------------------------------------------
-- CMP Register Masks
---------------------------------------------------------------------------- */
/**
* @addtogroup CMP_Register_Masks CMP Register Masks
* @{
*/
/* CR0 Bit Fields */
#define CMP_CR0_HYSTCTR_MASK 0x3u
#define CMP_CR0_HYSTCTR_SHIFT 0
#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
#define CMP_CR0_FILTER_CNT_MASK 0x70u
#define CMP_CR0_FILTER_CNT_SHIFT 4
#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
/* CR1 Bit Fields */
#define CMP_CR1_EN_MASK 0x1u
#define CMP_CR1_EN_SHIFT 0
#define CMP_CR1_OPE_MASK 0x2u
#define CMP_CR1_OPE_SHIFT 1
#define CMP_CR1_COS_MASK 0x4u
#define CMP_CR1_COS_SHIFT 2
#define CMP_CR1_INV_MASK 0x8u
#define CMP_CR1_INV_SHIFT 3
#define CMP_CR1_PMODE_MASK 0x10u
#define CMP_CR1_PMODE_SHIFT 4
#define CMP_CR1_WE_MASK 0x40u
#define CMP_CR1_WE_SHIFT 6
#define CMP_CR1_SE_MASK 0x80u
#define CMP_CR1_SE_SHIFT 7
/* FPR Bit Fields */
#define CMP_FPR_FILT_PER_MASK 0xFFu
#define CMP_FPR_FILT_PER_SHIFT 0
#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
/* SCR Bit Fields */
#define CMP_SCR_COUT_MASK 0x1u
#define CMP_SCR_COUT_SHIFT 0
#define CMP_SCR_CFF_MASK 0x2u
#define CMP_SCR_CFF_SHIFT 1
#define CMP_SCR_CFR_MASK 0x4u
#define CMP_SCR_CFR_SHIFT 2
#define CMP_SCR_IEF_MASK 0x8u
#define CMP_SCR_IEF_SHIFT 3
#define CMP_SCR_IER_MASK 0x10u
#define CMP_SCR_IER_SHIFT 4
#define CMP_SCR_SMELB_MASK 0x20u
#define CMP_SCR_SMELB_SHIFT 5
#define CMP_SCR_DMAEN_MASK 0x40u
#define CMP_SCR_DMAEN_SHIFT 6
/* DACCR Bit Fields */
#define CMP_DACCR_VOSEL_MASK 0x3Fu
#define CMP_DACCR_VOSEL_SHIFT 0
#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
#define CMP_DACCR_VRSEL_MASK 0x40u
#define CMP_DACCR_VRSEL_SHIFT 6
#define CMP_DACCR_DACEN_MASK 0x80u
#define CMP_DACCR_DACEN_SHIFT 7
/* MUXCR Bit Fields */
#define CMP_MUXCR_MSEL_MASK 0x7u
#define CMP_MUXCR_MSEL_SHIFT 0
#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
#define CMP_MUXCR_PSEL_MASK 0x38u
#define CMP_MUXCR_PSEL_SHIFT 3
#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
#define CMP_MUXCR_MEN_MASK 0x40u
#define CMP_MUXCR_MEN_SHIFT 6
#define CMP_MUXCR_PEN_MASK 0x80u
#define CMP_MUXCR_PEN_SHIFT 7
/**
* @}
*/ /* end of group CMP_Register_Masks */
/* CMP - Peripheral instance base addresses */
/** Peripheral CMP0 base address */
#define CMP0_BASE (0x40073000u)
/** Peripheral CMP0 base pointer */
#define CMP0 ((CMP_Type *)CMP0_BASE)
/** Peripheral CMP1 base address */
#define CMP1_BASE (0x40073008u)
/** Peripheral CMP1 base pointer */
#define CMP1 ((CMP_Type *)CMP1_BASE)
/** Peripheral CMP2 base address */
#define CMP2_BASE (0x40073010u)
/** Peripheral CMP2 base pointer */
#define CMP2 ((CMP_Type *)CMP2_BASE)
/**
* @}
*/ /* end of group CMP_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- CMT Peripheral Access Layer
---------------------------------------------------------------------------- */
/**
* @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer
* @{
*/
/** CMT - Register Layout Typedef */
typedef struct {
__IO uint8_t CGH1; /**< CMT Carrier Generator High Data Register 1, offset: 0x0 */
__IO uint8_t CGL1; /**< CMT Carrier Generator Low Data Register 1, offset: 0x1 */
__IO uint8_t CGH2; /**< CMT Carrier Generator High Data Register 2, offset: 0x2 */
__IO uint8_t CGL2; /**< CMT Carrier Generator Low Data Register 2, offset: 0x3 */
__IO uint8_t OC; /**< CMT Output Control Register, offset: 0x4 */
__IO uint8_t MSC; /**< CMT Modulator Status and Control Register, offset: 0x5 */
__IO uint8_t CMD1; /**< CMT Modulator Data Register Mark High, offset: 0x6 */
__IO uint8_t CMD2; /**< CMT Modulator Data Register Mark Low, offset: 0x7 */
__IO uint8_t CMD3; /**< CMT Modulator Data Register Space High, offset: 0x8 */
__IO uint8_t CMD4; /**< CMT Modulator Data Register Space Low, offset: 0x9 */
__IO uint8_t PPS; /**< CMT Primary Prescaler Register, offset: 0xA */
__IO uint8_t DMA; /**< CMT Direct Memory Access, offset: 0xB */
} CMT_Type;
/* ----------------------------------------------------------------------------
-- CMT Register Masks
---------------------------------------------------------------------------- */
/**
* @addtogroup CMT_Register_Masks CMT Register Masks
* @{
*/
/* CGH1 Bit Fields */
#define CMT_CGH1_PH_MASK 0xFFu
#define CMT_CGH1_PH_SHIFT 0
#define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH1_PH_SHIFT))&CMT_CGH1_PH_MASK)
/* CGL1 Bit Fields */
#define CMT_CGL1_PL_MASK 0xFFu
#define CMT_CGL1_PL_SHIFT 0
#define CMT_CGL1_PL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL1_PL_SHIFT))&CMT_CGL1_PL_MASK)
/* CGH2 Bit Fields */
#define CMT_CGH2_SH_MASK 0xFFu
#define CMT_CGH2_SH_SHIFT 0
#define CMT_CGH2_SH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH2_SH_SHIFT))&CMT_CGH2_SH_MASK)
/* CGL2 Bit Fields */
#define CMT_CGL2_SL_MASK 0xFFu
#define CMT_CGL2_SL_SHIFT 0
#define CMT_CGL2_SL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL2_SL_SHIFT))&CMT_CGL2_SL_MASK)
/* OC Bit Fields */
#define CMT_OC_IROPEN_MASK 0x20u
#define CMT_OC_IROPEN_SHIFT 5
#define CMT_OC_CMTPOL_MASK 0x40u
#define CMT_OC_CMTPOL_SHIFT 6
#define CMT_OC_IROL_MASK 0x80u
#define CMT_OC_IROL_SHIFT 7
/* MSC Bit Fields */
#define CMT_MSC_MCGEN_MASK 0x1u
#define CMT_MSC_MCGEN_SHIFT 0
#define CMT_MSC_EOCIE_MASK 0x2u
#define CMT_MSC_EOCIE_SHIFT 1
#define CMT_MSC_FSK_MASK 0x4u
#define CMT_MSC_FSK_SHIFT 2
#define CMT_MSC_BASE_MASK 0x8u
#define CMT_MSC_BASE_SHIFT 3
#define CMT_MSC_EXSPC_MASK 0x10u
#define CMT_MSC_EXSPC_SHIFT 4
#define CMT_MSC_CMTDIV_MASK 0x60u
#define CMT_MSC_CMTDIV_SHIFT 5
#define CMT_MSC_CMTDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_MSC_CMTDIV_SHIFT))&CMT_MSC_CMTDIV_MASK)
#define CMT_MSC_EOCF_MASK 0x80u
#define CMT_MSC_EOCF_SHIFT 7
/* CMD1 Bit Fields */
#define CMT_CMD1_MB_MASK 0xFFu
#define CMT_CMD1_MB_SHIFT 0
#define CMT_CMD1_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD1_MB_SHIFT))&CMT_CMD1_MB_MASK)
/* CMD2 Bit Fields */
#define CMT_CMD2_MB_MASK 0xFFu
#define CMT_CMD2_MB_SHIFT 0
#define CMT_CMD2_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD2_MB_SHIFT))&CMT_CMD2_MB_MASK)
/* CMD3 Bit Fields */
#define CMT_CMD3_SB_MASK 0xFFu
#define CMT_CMD3_SB_SHIFT 0
#define CMT_CMD3_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD3_SB_SHIFT))&CMT_CMD3_SB_MASK)
/* CMD4 Bit Fields */
#define CMT_CMD4_SB_MASK 0xFFu
#define CMT_CMD4_SB_SHIFT 0
#define CMT_CMD4_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD4_SB_SHIFT))&CMT_CMD4_SB_MASK)
/* PPS Bit Fields */
#define CMT_PPS_PPSDIV_MASK 0xFu
#define CMT_PPS_PPSDIV_SHIFT 0
#define CMT_PPS_PPSDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_PPS_PPSDIV_SHIFT))&CMT_PPS_PPSDIV_MASK)
/* DMA Bit Fields */
#define CMT_DMA_DMA_MASK 0x1u
#define CMT_DMA_DMA_SHIFT 0
/**
* @}
*/ /* end of group CMT_Register_Masks */
/* CMT - Peripheral instance base addresses */
/** Peripheral CMT base address */
#define CMT_BASE (0x40062000u)
/** Peripheral CMT base pointer */
#define CMT ((CMT_Type *)CMT_BASE)
/**
* @}
*/ /* end of group CMT_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- CRC Peripheral Access Layer
---------------------------------------------------------------------------- */
/**
* @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
* @{
*/
/** CRC - Register Layout Typedef */
typedef struct {
union { /* offset: 0x0 */
struct { /* offset: 0x0 */
__IO uint16_t CRCL; /**< CRC_CRCL register., offset: 0x0 */
__IO uint16_t CRCH; /**< CRC_CRCH register., offset: 0x2 */
} ACCESS16BIT;
__IO uint32_t CRC; /**< CRC Data Register, offset: 0x0 */
struct { /* offset: 0x0 */
__IO uint8_t CRCLL; /**< CRC_CRCLL register., offset: 0x0 */
__IO uint8_t CRCLU; /**< CRC_CRCLU register., offset: 0x1 */
__IO uint8_t CRCHL; /**< CRC_CRCHL register., offset: 0x2 */
__IO uint8_t CRCHU; /**< CRC_CRCHU register., offset: 0x3 */
} ACCESS8BIT;
};
union { /* offset: 0x4 */
struct { /* offset: 0x4 */
__IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */
__IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */
} GPOLY_ACCESS16BIT;
__IO uint32_t GPOLY; /**< CRC Polynomial Register, offset: 0x4 */
struct { /* offset: 0x4 */
__IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */
__IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */
__IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */
__IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */
} GPOLY_ACCESS8BIT;
};
union { /* offset: 0x8 */
__IO uint32_t CTRL; /**< CRC Control Register, offset: 0x8 */
struct { /* offset: 0x8 */
uint8_t RESERVED_0[3];
__IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */
} CTRL_ACCESS8BIT;
};
} CRC_Type;
/* ----------------------------------------------------------------------------
-- CRC Register Masks
---------------------------------------------------------------------------- */
/**
* @addtogroup CRC_Register_Masks CRC Register Masks
* @{
*/
/* CRCL Bit Fields */
#define CRC_CRCL_CRCL_MASK 0xFFFFu
#define CRC_CRCL_CRCL_SHIFT 0
#define CRC_CRCL_CRCL(x) (((uint16_t)(((uint16_t)(x))<<CRC_CRCL_CRCL_SHIFT))&CRC_CRCL_CRCL_MASK)
/* CRCH Bit Fields */
#define CRC_CRCH_CRCH_MASK 0xFFFFu
#define CRC_CRCH_CRCH_SHIFT 0
#define CRC_CRCH_CRCH(x) (((uint16_t)(((uint16_t)(x))<<CRC_CRCH_CRCH_SHIFT))&CRC_CRCH_CRCH_MASK)
/* CRC Bit Fields */
#define CRC_CRC_LL_MASK 0xFFu
#define CRC_CRC_LL_SHIFT 0
#define CRC_CRC_LL(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_LL_SHIFT))&CRC_CRC_LL_MASK)
#define CRC_CRC_LU_MASK 0xFF00u
#define CRC_CRC_LU_SHIFT 8
#define CRC_CRC_LU(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_LU_SHIFT))&CRC_CRC_LU_MASK)
#define CRC_CRC_HL_MASK 0xFF0000u
#define CRC_CRC_HL_SHIFT 16
#define CRC_CRC_HL(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_HL_SHIFT))&CRC_CRC_HL_MASK)
#define CRC_CRC_HU_MASK 0xFF000000u
#define CRC_CRC_HU_SHIFT 24
#define CRC_CRC_HU(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_HU_SHIFT))&CRC_CRC_HU_MASK)
/* CRCLL Bit Fields */
#define CRC_CRCLL_CRCLL_MASK 0xFFu
#define CRC_CRCLL_CRCLL_SHIFT 0
#define CRC_CRCLL_CRCLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCLL_CRCLL_SHIFT))&CRC_CRCLL_CRCLL_MASK)
/* CRCLU Bit Fields */
#define CRC_CRCLU_CRCLU_MASK 0xFFu
#define CRC_CRCLU_CRCLU_SHIFT 0
#define CRC_CRCLU_CRCLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCLU_CRCLU_SHIFT))&CRC_CRCLU_CRCLU_MASK)
/* CRCHL Bit Fields */
#define CRC_CRCHL_CRCHL_MASK 0xFFu
#define CRC_CRCHL_CRCHL_SHIFT 0
#define CRC_CRCHL_CRCHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCHL_CRCHL_SHIFT))&CRC_CRCHL_CRCHL_MASK)
/* CRCHU Bit Fields */
#define CRC_CRCHU_CRCHU_MASK 0xFFu
#define CRC_CRCHU_CRCHU_SHIFT 0
#define CRC_CRCHU_CRCHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCHU_CRCHU_SHIFT))&CRC_CRCHU_CRCHU_MASK)
/* GPOLYL Bit Fields */
#define CRC_GPOLYL_GPOLYL_MASK 0xFFFFu
#define CRC_GPOLYL_GPOLYL_SHIFT 0
#define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYL_GPOLYL_SHIFT))&CRC_GPOLYL_GPOLYL_MASK)
/* GPOLYH Bit Fields */
#define CRC_GPOLYH_GPOLYH_MASK 0xFFFFu
#define CRC_GPOLYH_GPOLYH_SHIFT 0
#define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYH_GPOLYH_SHIFT))&CRC_GPOLYH_GPOLYH_MASK)
/* GPOLY Bit Fields */
#define CRC_GPOLY_LOW_MASK 0xFFFFu
#define CRC_GPOLY_LOW_SHIFT 0
#define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_LOW_SHIFT))&CRC_GPOLY_LOW_MASK)
#define CRC_GPOLY_HIGH_MASK 0xFFFF0000u
#define CRC_GPOLY_HIGH_SHIFT 16
#define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_HIGH_SHIFT))&CRC_GPOLY_HIGH_MASK)
/* GPOLYLL Bit Fields */
#define CRC_GPOLYLL_GPOLYLL_MASK 0xFFu
#define CRC_GPOLYLL_GPOLYLL_SHIFT 0
#define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLL_GPOLYLL_SHIFT))&CRC_GPOLYLL_GPOLYLL_MASK)
/* GPOLYLU Bit Fields */
#define CRC_GPOLYLU_GPOLYLU_MASK 0xFFu
#define CRC_GPOLYLU_GPOLYLU_SHIFT 0
#define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLU_GPOLYLU_SHIFT))&CRC_GPOLYLU_GPOLYLU_MASK)
/* GPOLYHL Bit Fields */
#define CRC_GPOLYHL_GPOLYHL_MASK 0xFFu
#define CRC_GPOLYHL_GPOLYHL_SHIFT 0
#define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHL_GPOLYHL_SHIFT))&CRC_GPOLYHL_GPOLYHL_MASK)
/* GPOLYHU Bit Fields */
#define CRC_GPOLYHU_GPOLYHU_MASK 0xFFu
#define CRC_GPOLYHU_GPOLYHU_SHIFT 0
#define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHU_GPOLYHU_SHIFT))&CRC_GPOLYHU_GPOLYHU_MASK)
/* CTRL Bit Fields */
#define CRC_CTRL_TCRC_MASK 0x1000000u
#define CRC_CTRL_TCRC_SHIFT 24
#define CRC_CTRL_WAS_MASK 0x2000000u
#define CRC_CTRL_WAS_SHIFT 25
#define CRC_CTRL_FXOR_MASK 0x4000000u
#define CRC_CTRL_FXOR_SHIFT 26
#define CRC_CTRL_TOTR_MASK 0x30000000u
#define CRC_CTRL_TOTR_SHIFT 28
#define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOTR_SHIFT))&CRC_CTRL_TOTR_MASK)
#define CRC_CTRL_TOT_MASK 0xC0000000u
#define CRC_CTRL_TOT_SHIFT 30
#define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOT_SHIFT))&CRC_CTRL_TOT_MASK)
/* CTRLHU Bit Fields */
#define CRC_CTRLHU_TCRC_MASK 0x1u
#define CRC_CTRLHU_TCRC_SHIFT 0
#define CRC_CTRLHU_WAS_MASK 0x2u
#define CRC_CTRLHU_WAS_SHIFT 1
#define CRC_CTRLHU_FXOR_MASK 0x4u
#define CRC_CTRLHU_FXOR_SHIFT 2
#define CRC_CTRLHU_TOTR_MASK 0x30u
#define CRC_CTRLHU_TOTR_SHIFT 4
#define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOTR_SHIFT))&CRC_CTRLHU_TOTR_MASK)
#define CRC_CTRLHU_TOT_MASK 0xC0u
#define CRC_CTRLHU_TOT_SHIFT 6
#define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOT_SHIFT))&CRC_CTRLHU_TOT_MASK)
/**
* @}
*/ /* end of group CRC_Register_Masks */
/* CRC - Peripheral instance base addresses */
/** Peripheral CRC base address */
#define CRC_BASE (0x40032000u)
/** Peripheral CRC base pointer */
#define CRC0 ((CRC_Type *)CRC_BASE)
/**
* @}
*/ /* end of group CRC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- DAC Peripheral Access Layer
---------------------------------------------------------------------------- */
/**
* @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
* @{
*/
/** DAC - Register Layout Typedef */
typedef struct {
struct { /* offset: 0x0, array step: 0x2 */
__IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
__IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
} DAT[16];
__IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
__IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
__IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
__IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
} DAC_Type;
/* ----------------------------------------------------------------------------
-- DAC Register Masks
---------------------------------------------------------------------------- */
/**
* @addtogroup DAC_Register_Masks DAC Register Masks
* @{
*/
/* DATL Bit Fields */
#define DAC_DATL_DATA_MASK 0xFFu
#define DAC_DATL_DATA_SHIFT 0
#define DAC_DATL_DATA(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA_SHIFT))&DAC_DATL_DATA_MASK)
/* DATH Bit Fields */
#define DAC_DATH_DATA_MASK 0xFu
#define DAC_DATH_DATA_SHIFT 0
#define DAC_DATH_DATA(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA_SHIFT))&DAC_DATH_DATA_MASK)
/* SR Bit Fields */
#define DAC_SR_DACBFRPBF_MASK 0x1u
#define DAC_SR_DACBFRPBF_SHIFT 0
#define DAC_SR_DACBFRPTF_MASK 0x2u
#define DAC_SR_DACBFRPTF_SHIFT 1
#define DAC_SR_DACBFWMF_MASK 0x4u
#define DAC_SR_DACBFWMF_SHIFT 2
/* C0 Bit Fields */
#define DAC_C0_DACBBIEN_MASK 0x1u
#define DAC_C0_DACBBIEN_SHIFT 0
#define DAC_C0_DACBTIEN_MASK 0x2u
#define DAC_C0_DACBTIEN_SHIFT 1
#define DAC_C0_DACBWIEN_MASK 0x4u
#define DAC_C0_DACBWIEN_SHIFT 2
#define DAC_C0_LPEN_MASK 0x8u
#define DAC_C0_LPEN_SHIFT 3
#define DAC_C0_DACSWTRG_MASK 0x10u
#define DAC_C0_DACSWTRG_SHIFT 4
#define DAC_C0_DACTRGSEL_MASK 0x20u
#define DAC_C0_DACTRGSEL_SHIFT 5
#define DAC_C0_DACRFS_MASK 0x40u
#define DAC_C0_DACRFS_SHIFT 6
#define DAC_C0_DACEN_MASK 0x80u
#define DAC_C0_DACEN_SHIFT 7
/* C1 Bit Fields */
#define DAC_C1_DACBFEN_MASK 0x1u
#define DAC_C1_DACBFEN_SHIFT 0
#define DAC_C1_DACBFMD_MASK 0x6u
#define DAC_C1_DACBFMD_SHIFT 1
#define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFMD_SHIFT))&DAC_C1_DACBFMD_MASK)
#define DAC_C1_DACBFWM_MASK 0x18u
#define DAC_C1_DACBFWM_SHIFT 3
#define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFWM_SHIFT))&DAC_C1_DACBFWM_MASK)
#define DAC_C1_DMAEN_MASK 0x80u
#define DAC_C1_DMAEN_SHIFT 7
/* C2 Bit Fields */
#define DAC_C2_DACBFUP_MASK 0xFu
#define DAC_C2_DACBFUP_SHIFT 0
#define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFUP_SHIFT))&DAC_C2_DACBFUP_MASK)
#define DAC_C2_DACBFRP_MASK 0xF0u
#define DAC_C2_DACBFRP_SHIFT 4
#define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFRP_SHIFT))&DAC_C2_DACBFRP_MASK)
/**
* @}
*/ /* end of group DAC_Register_Masks */
/* DAC - Peripheral instance base addresses */
/** Peripheral DAC0 base address */
#define DAC0_BASE (0x400CC000u)
/** Peripheral DAC0 base pointer */
#define DAC0 ((DAC_Type *)DAC0_BASE)
/** Peripheral DAC1 base address */
#define DAC1_BASE (0x400CD000u)
/** Peripheral DAC1 base pointer */
#define DAC1 ((DAC_Type *)DAC1_BASE)
/**
* @}
*/ /* end of group DAC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- DMA Peripheral Access Layer
---------------------------------------------------------------------------- */
/**
* @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
* @{
*/
/** DMA - Register Layout Typedef */
typedef struct {
__IO uint32_t CR; /**< Control Register, offset: 0x0 */
__I uint32_t ES; /**< Error Status Register, offset: 0x4 */
uint8_t RESERVED_0[4];
__IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */
uint8_t RESERVED_1[4];
__IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */
__O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */
__O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */
__O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */
__O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */
__O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */
__O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */
__O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */
__O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */
uint8_t RESERVED_2[4];
__IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */
uint8_t RESERVED_3[4];
__IO uint32_t ERR; /**< Error Register, offset: 0x2C */
uint8_t RESERVED_4[4];
__IO uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */
uint8_t RESERVED_5[200];
__IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */
__IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */
__IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */
__IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */
__IO uint8_t DCHPRI7; /**< Channel n Priority Register, offset: 0x104 */
__IO uint8_t DCHPRI6; /**< Channel n Priority Register, offset: 0x105 */
__IO uint8_t DCHPRI5; /**< Channel n Priority Register, offset: 0x106 */
__IO uint8_t DCHPRI4; /**< Channel n Priority Register, offset: 0x107 */
__IO uint8_t DCHPRI11; /**< Channel n Priority Register, offset: 0x108 */
__IO uint8_t DCHPRI10; /**< Channel n Priority Register, offset: 0x109 */
__IO uint8_t DCHPRI9; /**< Channel n Priority Register, offset: 0x10A */
__IO uint8_t DCHPRI8; /**< Channel n Priority Register, offset: 0x10B */
__IO uint8_t DCHPRI15; /**< Channel n Priority Register, offset: 0x10C */
__IO uint8_t DCHPRI14; /**< Channel n Priority Register, offset: 0x10D */
__IO uint8_t DCHPRI13; /**< Channel n Priority Register, offset: 0x10E */
__IO uint8_t DCHPRI12; /**< Channel n Priority Register, offset: 0x10F */
uint8_t RESERVED_6[3824];
struct { /* offset: 0x1000, array step: 0x20 */
__IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
__IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
__IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
union { /* offset: 0x1008, array step: 0x20 */
__IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 */
__IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
__IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 */