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127 lines
3.5 KiB
C
127 lines
3.5 KiB
C
/*
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* Copyright (C) 2015 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_cortexm_common
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* @{
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*
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* @file
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* @brief Default interrupt vectors shared by Cortex-M based CPUs
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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*/
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#ifndef VECTORS_DEFAULT_H
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#define VECTORS_DEFAULT_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Use this macro to make interrupt functions overridable with the
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* dummy_handler as fallback in case they are not implemented
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*/
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#define WEAK_DEFAULT __attribute__((weak,alias("dummy_handler")))
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/**
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* @brief Put this macro in front of the array holding the interrupt vectors
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*/
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#define ISR_VECTORS __attribute__((used,section(".vectors")))
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/**
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* @brief Number of Cortex-M non-ISR exceptions
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*
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* This means those that are no hardware interrupts, or the ones with a
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* negative interrupt number.
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*/
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#define CPU_NONISR_EXCEPTIONS (15)
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/**
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* @brief This function is the default entry point after a system reset
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*
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* After a system reset, the following steps are necessary and carried out:
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* 1. load data section from flash to ram
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* 2. overwrite uninitialized data section (BSS) with zeros
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* 3. initialize the board (sync clock, setup std-IO)
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* 4. initialize the newlib (optional, on when newlib is used)
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* 5. initialize and start RIOTs kernel
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*/
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void reset_handler_default(void);
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/**
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* @brief Non-maskable interrupt handler
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*
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* Non-maskable interrupts have the highest priority other than the reset event
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* and can not be masked (surprise surprise...). They can be triggered by
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* software and some peripherals. So far, they are not used in RIOT.
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*/
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void nmi_default(void);
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/**
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* @brief Hard fault exception handler
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*
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* Hard faults are triggered on errors during exception processing. Typical
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* causes of hard faults are access to un-aligned pointers on Cortex-M0 CPUs
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* and calls of function pointers that are set to NULL.
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*/
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void hard_fault_default(void);
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/* The following four exceptions are only present for Cortex-M3 and -M4 CPUs */
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#if defined(CPU_ARCH_CORTEX_M3) || defined(CPU_ARCH_CORTEX_M4) || \
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defined(CPU_ARCH_CORTEX_M4F) || defined(CPU_ARCH_CORTEX_M7)
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/**
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* @brief Memory management exception handler
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*
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* Memory management exceptions are triggered on access to protected memory
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* regions.
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*/
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void mem_manage_default(void);
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/**
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* @brief Bus fault exception handler
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*
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* Bus faults are triggered on errors that are related to memory transactions.
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*/
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void bus_fault_default(void);
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/**
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* @brief Usage fault exception handler
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*
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* Usage fault exceptions are triggered by faults related to the execution of
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* instructions, e.g. execution of undefined opcodes, illegal alignment, or
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* or invalid exception return codes.
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*/
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void usage_fault_default(void);
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/**
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* @brief Debug monitor exception handler
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*
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* The debug monitor exception is triggered, when a software debug event occurs
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* while in debug mode.
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*/
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void debug_mon_default(void);
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#endif
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/**
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* @brief Default handler used as weak alias for not implemented ISR vectors
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*
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* Per default, all interrupt handlers are mapped to the dummy handler using a
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* weak symbol. This means the handlers can be (should be) overwritten in the
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* RIOT code by just implementing a function with the name of the targeted
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* interrupt routine.
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*/
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void dummy_handler_default(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* VECTORS_DEFAULT_H */
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/** @} */
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