removed f3 example for now
Christoph Groß
5 years ago
parent
2feff5b9fa
commit
6fb99f9dc5
@ -1,31 +0,0 @@
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[package]
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name = "f3_stm32f30x"
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version = "0.1.0"
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authors = ["Christoph Groß <christoph.gross@student.uni-tuebingen.de>"]
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[dependencies]
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#f3 = "0.6.0"
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f3 = "0.5.3"
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#cortex-m = {version = "0.5.2"}
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cortex-m = {version = "0.4.3"}
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eink_waveshare_rs = { git = "https://github.com/Caemor/eink-waveshare-rs", rev = "ba5d44a"}
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#eink_waveshare_rs = { path = "../../"}
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# only temporary until Digital::InputPin has arrived in f3
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#TODO: update to 0.2.1
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embedded-hal = { version = "0.1.2", features = ["unproven"] }
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# for #no_std
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panic-abort = "0.1.1"
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# for handling 'language item required, but not found: 'eh_personality' in #no_std
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# see https://os.phil-opp.com/freestanding-rust-binary/ for more infos
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[profile.dev]
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panic = "abort"
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[profile.release]
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panic = "abort"
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@ -1,121 +0,0 @@
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#![feature(start)]
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#![deny(unsafe_code)]
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#![no_std]
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extern crate cortex_m;
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extern crate f3;
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extern crate eink_waveshare_rs;
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extern crate embedded_hal as hal;
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// For handling 'language item required, but not found: panic_fmt' in #no_std
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// see https://os.phil-opp.com/freestanding-rust-binary/ for more infos
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extern crate panic_abort;
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use f3::hal::prelude::*;
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use f3::hal::stm32f30x;
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use f3::hal::spi::Spi;
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use f3::hal::delay::Delay;
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use eink_waveshare_rs::{epd4in2::EPD4in2, SPI_MODE};
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use hal::digital::{InputPin, OutputPin};
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//from https://github.com/rudihorn/max31865/tree/extra_examples/examples
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struct HackInputPin<'a> {
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pin: &'a OutputPin
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}
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impl<'a> HackInputPin<'a> {
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fn new(p : &'a OutputPin) -> HackInputPin {
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HackInputPin {
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pin: p
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}
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}
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}
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impl<'a> InputPin for HackInputPin<'a> {
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fn is_low(&self) -> bool {
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self.pin.is_low()
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}
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fn is_high(&self) -> bool {
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self.pin.is_high()
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}
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}
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/*
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*
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* BE CAREFUL: this wasn't tested yet, and the pins are also not choosen correctly (just some random ones atm)
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*
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*/
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#[start]
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fn main() {
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let cp = cortex_m::Peripherals::take().unwrap();
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let p = stm32f30x::Peripherals::take().unwrap();
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let mut flash = p.FLASH.constrain();
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let mut rcc = p.RCC.constrain();
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// TRY the other clock configuration
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let clocks = rcc.cfgr.freeze(&mut flash.acr);
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// let clocks = rcc.cfgr.sysclk(64.mhz()).pclk1(32.mhz()).freeze(&mut flash.acr);
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let mut gpioa = p.GPIOA.split(&mut rcc.ahb);
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let mut gpioe = p.GPIOE.split(&mut rcc.ahb);
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let mut cs = gpioe
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.pe3
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.into_push_pull_output(&mut gpioe.moder, &mut gpioe.otyper);
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cs.set_high();
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//TODO: Fix when f3::hal includes Digital::InputPin
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//using the hack from rudihorn that Digital::OutputPin basically
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//contains the needed functions for Digital::InputPin
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//let busy = gpioe.pe4.into_floating_input(&mut gpioe.moder, &mut gpioe.pupdr);
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let busy = gpioe.pe4.into_push_pull_output(&mut gpioe.moder, &mut gpioe.otyper);
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let busy_in = HackInputPin::new(&busy);
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let dc = gpioe.pe5.into_push_pull_output(&mut gpioe.moder, &mut gpioe.otyper);
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let rst = gpioe.pe6.into_push_pull_output(&mut gpioe.moder, &mut gpioe.otyper);
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let delay = Delay::new(cp.SYST, clocks);
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// The `L3gd20` abstraction exposed by the `f3` crate requires a specific pin configuration to
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// be used and won't accept any configuration other than the one used here. Trying to use a
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// different pin configuration will result in a compiler error.
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let sck = gpioa.pa5.into_af5(&mut gpioa.moder, &mut gpioa.afrl);
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let miso = gpioa.pa6.into_af5(&mut gpioa.moder, &mut gpioa.afrl);
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let mosi = gpioa.pa7.into_af5(&mut gpioa.moder, &mut gpioa.afrl);
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let spi = Spi::spi1(
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p.SPI1,
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(sck, miso, mosi),
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SPI_MODE,
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2.mhz(),
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clocks,
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&mut rcc.apb2,
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);
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//TODO wait for f3::hal update to include Digital::InputPin
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let mut epd4in2 = EPD4in2::new(spi, cs, busy_in, dc, rst, delay).unwrap();
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//let mut buffer = [0u8, epd4in2.get_width() / 8 * epd4in2.get_height()];
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let mut buffer = [0u8; 15000];
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// draw something into the buffer
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buffer[0] = 0xFF;
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epd4in2.display_and_transfer_frame(&buffer, None).unwrap();
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epd4in2.delay_ms(3000);
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epd4in2.clear_frame(None).unwrap();
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epd4in2.sleep().unwrap();
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}
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