WIP for i2c
This commit is contained in:
parent
44dfef354d
commit
e0f51c6cb8
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@ -14,6 +14,7 @@ targets = ["riscv64gc-unknown-none-elf"]
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[dependencies]
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embedded-hal = "1.0.0-alpha.1"
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## embedded-hal = { version = "0.2.4", features = ["unproven"] }
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nb = "0.1.1"
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k210-pac = "0.2.0"
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k210-pac = { pat="../k210-pac"}
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bitflags = "1.2.1"
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@ -87,7 +87,7 @@ pub mod io_pins {
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use core::marker::PhantomData;
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use super::{Function, IoPin, Mode, FUNCTION_DEFAULTS};
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use crate::pac::FPIOA;
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$(
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/// Programmable I/O pin
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pub struct $IoX<FUNC> {
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@ -148,8 +148,8 @@ def_io_pin! {
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Io27: (27, io27, GPIOHS11);
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Io28: (28, io28, GPIOHS12);
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Io29: (29, io29, GPIOHS13);
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Io30: (30, io30, GPIOHS14);
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Io31: (31, io31, GPIOHS15);
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Io30: (30, io30, I2C1_SCLK);
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Io31: (31, io31, I2C1_SDA);
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Io32: (32, io32, GPIOHS16);
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Io33: (33, io33, GPIOHS17);
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Io34: (34, io34, GPIOHS18);
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@ -117,15 +117,15 @@ impl<MODE> Gpiohs0<MODE> {
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impl<MODE> InputPin for Gpiohs0<Input<MODE>> {
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type Error = core::convert::Infallible;
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fn try_is_high(&self) -> Result<bool, Self::Error> {
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Ok(unsafe {
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fn try_is_high(&self) -> Result<bool, Self::Error> {
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Ok(unsafe {
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let p = &(*GPIOHS::ptr()).input_val as *const _ as *const _;
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u32_bit_is_set(p, 0)
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})
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}
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fn try_is_low(&self) -> Result<bool, Self::Error> {
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Ok(unsafe {
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fn try_is_low(&self) -> Result<bool, Self::Error> {
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Ok(unsafe {
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let p = &(*GPIOHS::ptr()).input_val as *const _ as *const _;
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u32_bit_is_clear(p, 0)
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})
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@ -136,7 +136,7 @@ impl<MODE> OutputPin for Gpiohs0<Output<MODE>> {
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type Error = core::convert::Infallible;
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fn try_set_high(&mut self) -> Result<(), Self::Error> {
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unsafe {
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unsafe {
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let p = &(*GPIOHS::ptr()).output_val as *const _ as *mut _;
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u32_set_bit(p, true, 0);
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}
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@ -144,7 +144,7 @@ impl<MODE> OutputPin for Gpiohs0<Output<MODE>> {
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}
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fn try_set_low(&mut self) -> Result<(), Self::Error> {
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unsafe {
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unsafe {
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let p = &(*GPIOHS::ptr()).output_val as *const _ as *mut _;
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u32_set_bit(p, false, 0);
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}
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@ -156,187 +156,186 @@ trait GpiohsAccess {
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fn peripheral() -> &'static mut crate::pac::gpiohs::RegisterBlock;
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fn set_drive(index: usize, bit: bool) {
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unsafe {
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let p = &mut Self::peripheral().drive as *mut _ as *mut _;
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unsafe {
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let p = &mut Self::peripheral().drive as *mut _ as *mut _;
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u32_set_bit(p, bit, index);
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}
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}
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fn input_value(index: usize) -> bool {
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unsafe {
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let p = &mut Self::peripheral().input_val as *mut _ as *mut _;
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let p = &mut Self::peripheral().input_val as *mut _ as *mut _;
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u32_bit_is_set(p, index)
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}
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}
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fn set_input_en(index: usize, bit: bool) {
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unsafe {
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let p = &mut Self::peripheral().input_en as *mut _ as *mut _;
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unsafe {
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let p = &mut Self::peripheral().input_en as *mut _ as *mut _;
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u32_set_bit(p, bit, index);
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}
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}
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fn set_iof_en(index: usize, bit: bool) {
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unsafe {
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let p = &mut Self::peripheral().iof_en as *mut _ as *mut _;
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unsafe {
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let p = &mut Self::peripheral().iof_en as *mut _ as *mut _;
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u32_set_bit(p, bit, index);
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}
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}
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fn set_iof_sel(index: usize, bit: bool) {
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unsafe {
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let p = &mut Self::peripheral().iof_sel as *mut _ as *mut _;
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unsafe {
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let p = &mut Self::peripheral().iof_sel as *mut _ as *mut _;
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u32_set_bit(p, bit, index);
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}
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}
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fn set_output_en(index: usize, bit: bool) {
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unsafe {
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let p = &mut Self::peripheral().output_en as *mut _ as *mut _;
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unsafe {
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let p = &mut Self::peripheral().output_en as *mut _ as *mut _;
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u32_set_bit(p, bit, index);
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}
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}
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fn set_output_value(index: usize, bit: bool) {
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unsafe {
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let p = &mut Self::peripheral().output_val as *mut _ as *mut _;
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unsafe {
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let p = &mut Self::peripheral().output_val as *mut _ as *mut _;
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u32_set_bit(p, bit, index);
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}
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}
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fn set_output_xor(index: usize, bit: bool) {
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unsafe {
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let p = &mut Self::peripheral().output_xor as *mut _ as *mut _;
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let p = &mut Self::peripheral().output_xor as *mut _ as *mut _;
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u32_set_bit(p, bit, index);
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}
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}
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fn toggle_pin(index: usize) {
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unsafe {
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let p = &mut Self::peripheral().output_val as *mut _ as *mut _;
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let p = &mut Self::peripheral().output_val as *mut _ as *mut _;
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u32_toggle_bit(p, index);
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}
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}
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fn set_pullup_en(index: usize, bit: bool) {
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unsafe {
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let p = &mut Self::peripheral().pullup_en as *mut _ as *mut _;
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unsafe {
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let p = &mut Self::peripheral().pullup_en as *mut _ as *mut _;
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u32_set_bit(p, bit, index);
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}
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}
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fn set_rise_ie(index: usize, bit: bool) {
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unsafe {
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let p = &mut Self::peripheral().rise_ie as *mut _ as *mut _;
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let p = &mut Self::peripheral().rise_ie as *mut _ as *mut _;
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u32_set_bit(p, bit, index);
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}
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}
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fn clear_rise_ip(index: usize) {
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unsafe {
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let p = &mut Self::peripheral().rise_ip as *mut _ as *mut _;
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let p = &mut Self::peripheral().rise_ip as *mut _ as *mut _;
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u32_set_bit(p, true, index);
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}
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}
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fn set_fall_ie(index: usize, bit: bool) {
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unsafe {
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let p = &mut Self::peripheral().fall_ie as *mut _ as *mut _;
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let p = &mut Self::peripheral().fall_ie as *mut _ as *mut _;
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u32_set_bit(p, bit, index);
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}
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}
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fn clear_fall_ip(index: usize) {
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unsafe {
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let p = &mut Self::peripheral().fall_ip as *mut _ as *mut _;
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let p = &mut Self::peripheral().fall_ip as *mut _ as *mut _;
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u32_set_bit(p, true, index);
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}
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}
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fn set_high_ie(index: usize, bit: bool) {
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unsafe {
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let p = &mut Self::peripheral().high_ie as *mut _ as *mut _;
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let p = &mut Self::peripheral().high_ie as *mut _ as *mut _;
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u32_set_bit(p, bit, index);
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}
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}
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fn clear_high_ip(index: usize,) {
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unsafe {
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let p = &mut Self::peripheral().high_ip as *mut _ as *mut _;
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let p = &mut Self::peripheral().high_ip as *mut _ as *mut _;
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u32_set_bit(p, true, index);
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}
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}
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fn set_low_ie(index: usize, bit: bool) {
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unsafe {
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let p = &mut Self::peripheral().low_ie as *mut _ as *mut _;
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let p = &mut Self::peripheral().low_ie as *mut _ as *mut _;
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u32_set_bit(p, bit, index);
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}
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}
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fn clear_low_ip(index: usize) {
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unsafe {
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let p = &mut Self::peripheral().low_ip as *mut _ as *mut _;
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let p = &mut Self::peripheral().low_ip as *mut _ as *mut _;
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u32_set_bit(p, true, index);
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}
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}
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fn has_rise_ie(index: usize) -> bool {
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unsafe {
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let p = &mut Self::peripheral().rise_ie as *mut _ as *mut _;
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let p = &mut Self::peripheral().rise_ie as *mut _ as *mut _;
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u32_bit_is_set(p, index)
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}
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}
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fn has_fall_ie(index: usize) -> bool {
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unsafe {
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let p = &mut Self::peripheral().fall_ie as *mut _ as *mut _;
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let p = &mut Self::peripheral().fall_ie as *mut _ as *mut _;
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u32_bit_is_set(p, index)
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}
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}
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fn has_high_ie(index: usize) -> bool {
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unsafe {
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let p = &mut Self::peripheral().high_ie as *mut _ as *mut _;
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let p = &mut Self::peripheral().high_ie as *mut _ as *mut _;
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u32_bit_is_set(p, index)
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}
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}
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fn has_low_ie(index: usize) -> bool {
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unsafe {
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let p = &mut Self::peripheral().low_ie as *mut _ as *mut _;
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let p = &mut Self::peripheral().low_ie as *mut _ as *mut _;
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u32_bit_is_set(p, index)
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}
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}
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fn has_rise_ip(index: usize) -> bool {
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unsafe {
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let p = &mut Self::peripheral().rise_ip as *mut _ as *mut _;
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let p = &mut Self::peripheral().rise_ip as *mut _ as *mut _;
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u32_bit_is_set(p, index)
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}
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}
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fn has_fall_ip(index: usize) -> bool {
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unsafe {
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let p = &mut Self::peripheral().fall_ip as *mut _ as *mut _;
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let p = &mut Self::peripheral().fall_ip as *mut _ as *mut _;
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u32_bit_is_set(p, index)
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}
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}
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fn has_high_ip(index: usize) -> bool {
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unsafe {
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let p = &mut Self::peripheral().high_ip as *mut _ as *mut _;
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let p = &mut Self::peripheral().high_ip as *mut _ as *mut _;
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u32_bit_is_set(p, index)
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}
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}
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fn has_low_ip(index: usize) -> bool {
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unsafe {
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let p = &mut Self::peripheral().low_ip as *mut _ as *mut _;
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let p = &mut Self::peripheral().low_ip as *mut _ as *mut _;
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u32_bit_is_set(p, index)
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}
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}
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}
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impl GpiohsAccess for GPIOHS {
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@ -0,0 +1,349 @@
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//! Inter-Integrated Circuit (I2C) bus
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use crate::pac::I2C1;
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use core::marker::PhantomData;
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use crate::bit_utils::{u32_set_bit, u32_toggle_bit, u32_bit_is_set, u32_bit_is_clear};
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use embedded_hal::digital::v2::{InputPin, OutputPin};
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use embedded_hal::blocking::i2c::{Read, Write, WriteRead};
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use crate::{
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fpioa::{
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io_pins::{Io30, Io31},
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functions::{I2C1_SCLK, I2C1_SDA},
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},
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time::Hertz,
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};
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// use crate::{
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// gpio::{
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// gpioa::{PA6, PA7},
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// gpiob::{PB2, PB3},
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// gpiod::{PD0, PD1},
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// gpioe::{PE4, PE5},
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// AlternateFunction, Floating, OpenDrain, OutputMode, AF3,
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// },
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// hal::blocking::i2c::{Read, Write, WriteRead},
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// sysctl::{self, Clocks},
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// };
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/// I2C error
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#[derive(Debug)]
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pub enum Error {
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/// Bus error
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Bus,
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/// Arbitration loss
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Arbitration,
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/// Missing Data ACK
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DataAck,
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/// Missing Addrees ACK
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AdrAck,
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#[doc(hidden)]
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_Extensible,
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}
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// FIXME these should be "closed" traits
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/// SCL pin -- DO NOT IMPLEMENT THIS TRAIT
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pub unsafe trait SclPin<I2C> {}
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/// SDA pin -- DO NOT IMPLEMENT THIS TRAIT
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pub unsafe trait SdaPin<I2C> {}
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unsafe impl SclPin<I2C1> for Io30<I2C1_SCLK> {}
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unsafe impl SdaPin<I2C1> for Io31<I2C1_SDA> {}
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/// I2C peripheral operating in master mode
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pub struct I2c<I2C, PINS> {
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i2c: I2C,
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pins: PINS,
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}
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// macro_rules! busy_wait {
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// ($i2c:expr, $flag:ident, $op:ident) => {
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// // in 'release' builds, the time between setting the `run` bit and checking the `busy`
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// // bit is too short and the `busy` bit is not reliably set by the time you get there,
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// // it can take up to 8 clock cycles for the `run` to begin so this delay allows time
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// // for that hardware synchronization
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// delay(2);
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// loop {
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// let mcs = $i2c.mcs.read();
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// if mcs.error().bit_is_set() {
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// if mcs.adrack().bit_is_set() {
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// return Err(Error::AdrAck);
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// } else if mcs.datack().bit_is_set() {
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// return Err(Error::DataAck);
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// }
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// return Err(Error::Bus);
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// } else if mcs.arblst().bit_is_set() {
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// return Err(Error::Arbitration);
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// } else if mcs.$flag().$op() {
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// break;
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// } else {
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// // try again
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// }
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// }
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// };
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// }
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macro_rules! hal {
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($($I2CX:ident: ($powerDomain:ident, $i2cX:ident),)+) => {
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$(
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impl<SCL, SDA> I2c<$I2CX, (SCL, SDA)> {
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/// Configures the I2C peripheral to work in master mode
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pub fn $i2cX<F>(
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i2c: $I2CX,
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pins: (SCL, SDA),
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freq: F,
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// clocks: &Clocks,
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// pc: &sysctl::PowerControl,
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) -> Self where
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F: Into<Hertz>,
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SCL: SclPin<$I2CX>,
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SDA: SdaPin<$I2CX>,
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{
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// sysctl::control_power(
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// pc, sysctl::Domain::$powerDomain,
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// sysctl::RunMode::Run, sysctl::PowerState::On);
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// sysctl::reset(pc, sysctl::Domain::$powerDomain);
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// // set Master Function Enable, and clear other bits.
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// i2c.mcr.write(|w| w.mfe().set_bit());
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// // Write TimerPeriod configuration and clear other bits.
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// let freq = freq.into().0;
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// let tpr = ((clocks.sysclk.0/(2*10*freq))-1) as u8;
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// i2c.mtpr.write(|w| unsafe {w.tpr().bits(tpr)});
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I2c { i2c, pins }
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}
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/// Releases the I2C peripheral and associated pins
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pub fn free(self) -> ($I2CX, (SCL, SDA)) {
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(self.i2c, self.pins)
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}
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}
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impl<PINS> Write for I2c<$I2CX, PINS> {
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type Error = Error;
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fn write(&mut self, addr: u8, bytes: &[u8]) -> Result<(), Error> {
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// Write Slave address and clear Receive bit
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// self.i2c.msa.write(|w| unsafe {
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// w.sa().bits(addr)
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// });
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// // Put first byte in data register
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// self.i2c.mdr.write(|w| unsafe {
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// w.data().bits(bytes[0])
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// });
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// let sz = bytes.len();
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// busy_wait!(self.i2c, busbsy, bit_is_clear);
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// // Send START + RUN
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// // If single byte transfer, set STOP
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// self.i2c.mcs.write(|w| {
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// if sz == 1 {
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// w.stop().set_bit();
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// }
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// w.start().set_bit()
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// .run().set_bit()
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// });
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||||
|
||||
// for (i,byte) in (&bytes[1..]).iter().enumerate() {
|
||||
// busy_wait!(self.i2c, busy, bit_is_clear);
|
||||
|
||||
// // Put next byte in data register
|
||||
// self.i2c.mdr.write(|w| unsafe {
|
||||
// w.data().bits(*byte)
|
||||
// });
|
||||
|
||||
// // Send RUN command (Burst continue)
|
||||
// // Set STOP on last byte
|
||||
// self.i2c.mcs.write(|w| {
|
||||
// if (i+1) == (sz-1) {
|
||||
// w.stop().set_bit();
|
||||
// }
|
||||
// w.run().set_bit()
|
||||
// });
|
||||
// }
|
||||
|
||||
// busy_wait!(self.i2c, busy, bit_is_clear);
|
||||
|
||||
Ok(())
|
||||
}
|
||||
}
|
||||
|
||||
impl<PINS> Read for I2c<$I2CX, PINS> {
|
||||
type Error = Error;
|
||||
|
||||
fn read(
|
||||
&mut self,
|
||||
addr: u8,
|
||||
buffer: &mut [u8],
|
||||
) -> Result<(), Error> {
|
||||
|
||||
// // Write Slave address and set Receive bit
|
||||
// self.i2c.msa.write(|w| unsafe {
|
||||
// w.sa().bits(addr)
|
||||
// .rs().set_bit()
|
||||
// });
|
||||
|
||||
// busy_wait!(self.i2c, busbsy, bit_is_clear);
|
||||
// let recv_sz = buffer.len();
|
||||
|
||||
// if recv_sz == 1 {
|
||||
// // Single receive
|
||||
// self.i2c.mcs.write(|w| {
|
||||
// w.run().set_bit()
|
||||
// .start().set_bit()
|
||||
// .stop().set_bit()
|
||||
// });
|
||||
|
||||
// busy_wait!(self.i2c, busy, bit_is_clear);
|
||||
// buffer[0] = self.i2c.mdr.read().data().bits();
|
||||
// } else {
|
||||
// self.i2c.mcs.write(|w| {
|
||||
// w.start().set_bit()
|
||||
// .run().set_bit()
|
||||
// .ack().set_bit()
|
||||
// });
|
||||
|
||||
// busy_wait!(self.i2c, busy, bit_is_clear);
|
||||
// buffer[0] = self.i2c.mdr.read().data().bits();
|
||||
|
||||
// for byte in &mut buffer[1..recv_sz-1] {
|
||||
// self.i2c.mcs.write(|w| {
|
||||
// w.run().set_bit()
|
||||
// .ack().set_bit()
|
||||
// });
|
||||
// busy_wait!(self.i2c, busy, bit_is_clear);
|
||||
// *byte = self.i2c.mdr.read().data().bits();
|
||||
// }
|
||||
// self.i2c.mcs.write(|w| {
|
||||
// w.run().set_bit()
|
||||
// .stop().set_bit()
|
||||
// });
|
||||
|
||||
// busy_wait!(self.i2c, busy, bit_is_clear);
|
||||
// buffer[recv_sz-1] = self.i2c.mdr.read().data().bits();
|
||||
// }
|
||||
|
||||
Ok(())
|
||||
}
|
||||
}
|
||||
|
||||
impl<PINS> WriteRead for I2c<$I2CX, PINS> {
|
||||
type Error = Error;
|
||||
|
||||
fn write_read(
|
||||
&mut self,
|
||||
addr: u8,
|
||||
bytes: &[u8],
|
||||
buffer: &mut [u8],
|
||||
) -> Result<(), Error> {
|
||||
|
||||
// let write_len = bytes.len();
|
||||
|
||||
// if buffer.len() == 0 {
|
||||
// return self.write(addr, bytes);
|
||||
// }
|
||||
|
||||
// if bytes.len() == 0 {
|
||||
// return self.read(addr, buffer);
|
||||
// }
|
||||
|
||||
// // Write Slave address and clear Receive bit
|
||||
// self.i2c.msa.write(|w| unsafe {
|
||||
// w.sa().bits(addr)
|
||||
// });
|
||||
|
||||
// // send first byte
|
||||
// self.i2c.mdr.write(|w| unsafe {
|
||||
// w.data().bits(bytes[0])
|
||||
// });
|
||||
|
||||
// busy_wait!(self.i2c, busbsy, bit_is_clear);
|
||||
|
||||
// self.i2c.mcs.write(|w| {
|
||||
// w.start().set_bit()
|
||||
// .run().set_bit()
|
||||
// });
|
||||
|
||||
// busy_wait!(self.i2c, busy, bit_is_clear);
|
||||
|
||||
// for byte in (&bytes[1..write_len]).iter() {
|
||||
// self.i2c.mdr.write(|w| unsafe {
|
||||
// w.data().bits(*byte)
|
||||
// });
|
||||
|
||||
// self.i2c.mcs.write(|w| {
|
||||
// w.run().set_bit()
|
||||
// });
|
||||
|
||||
// busy_wait!(self.i2c, busy, bit_is_clear);
|
||||
// }
|
||||
|
||||
// // Write Slave address and set Receive bit
|
||||
// self.i2c.msa.write(|w| unsafe {
|
||||
// w.sa().bits(addr)
|
||||
// .rs().set_bit()
|
||||
// });
|
||||
|
||||
// let recv_sz = buffer.len();
|
||||
|
||||
// if recv_sz == 1 {
|
||||
// // emit Repeated START and STOP for single receive
|
||||
// self.i2c.mcs.write(|w| {
|
||||
// w.run().set_bit()
|
||||
// .start().set_bit()
|
||||
// .stop().set_bit()
|
||||
// });
|
||||
|
||||
// busy_wait!(self.i2c, busy, bit_is_clear);
|
||||
// buffer[0] = self.i2c.mdr.read().data().bits();
|
||||
// } else {
|
||||
// // emit Repeated START
|
||||
// self.i2c.mcs.write(|w| {
|
||||
// w.run().set_bit()
|
||||
// .start().set_bit()
|
||||
// .ack().set_bit()
|
||||
// });
|
||||
|
||||
// busy_wait!(self.i2c, busy, bit_is_clear);
|
||||
// buffer[0] = self.i2c.mdr.read().data().bits();
|
||||
|
||||
// for byte in &mut buffer[1..recv_sz-1] {
|
||||
// self.i2c.mcs.write(|w| {
|
||||
// w.run().set_bit()
|
||||
// .ack().set_bit()
|
||||
// });
|
||||
// busy_wait!(self.i2c, busy, bit_is_clear);
|
||||
// *byte = self.i2c.mdr.read().data().bits();
|
||||
// }
|
||||
|
||||
// self.i2c.mcs.write(|w| {
|
||||
// w.run().set_bit()
|
||||
// .stop().set_bit()
|
||||
// });
|
||||
|
||||
// busy_wait!(self.i2c, busy, bit_is_clear);
|
||||
// buffer[recv_sz-1] = self.i2c.mdr.read().data().bits();
|
||||
// }
|
||||
|
||||
Ok(())
|
||||
}
|
||||
}
|
||||
)+
|
||||
}
|
||||
}
|
||||
|
||||
hal! {
|
||||
I2C1: (I2c1, i2c1),
|
||||
}
|
||||
|
|
@ -15,6 +15,7 @@ pub mod clock;
|
|||
pub mod dmac;
|
||||
pub mod fft;
|
||||
pub mod fpioa;
|
||||
pub mod i2c;
|
||||
pub mod gpio;
|
||||
pub mod gpiohs;
|
||||
pub mod plic;
|
||||
|
|
|
|||
Loading…
Reference in New Issue