diff --git a/kicad/startracker.dsn b/kicad/startracker.dsn new file mode 100644 index 0000000..31d2200 --- /dev/null +++ b/kicad/startracker.dsn @@ -0,0 +1,475 @@ +(pcb /home/marc/git/startracker/kicad/startracker.dsn + (parser + (string_quote ") + (space_in_quoted_tokens on) + (host_cad "KiCad's Pcbnew") + (host_version "4.0.5+dfsg1-4") + ) + (resolution um 10) + (unit um) + (structure + (layer F.Cu + (type signal) + (property + (index 0) + ) + ) + (layer B.Cu + (type signal) + (property + (index 1) + ) + ) + (boundary + (rect pcb 142287 -96103.8 221880 -144544) + ) + (via "Via[0-1]_600:400_um") + (rule + (width 250) + (clearance 200.1) + (clearance 200.1 (type default_smd)) + (clearance 50 (type smd_smd)) + ) + ) + (placement + (component Modules:Arduino_Nano_WithMountingHoles + (place A1 186461 -102159 front 0 (PN Arduino_Nano_v3.x)) + ) + (component "Modules:Pololu_Breakout-16_15.2x20.3mm" + (place A2 158572 -119418 front 0 (PN Pololu_Breakout_DRV8825)) + ) + (component Resistors_ThroughHole:Resistor_Horizontal_RM7mm + (place R1 179654 -106832 front 90 (PN R)) + (place R2 157251 -106655 front 0 (PN R)) + (place R3 172580 -113741 front 90 (PN R)) + (place R4 157963 -113551 front 0 (PN R)) + ) + (component "sparkfun:SF-ROTARY-ENCODER" + (place SW1 214580 -105207 front 0 (PN Rotary_Encoder_Switch)) + ) + (component Pin_Headers:Pin_Header_Straight_1x06_Pitch2.54mm + (place J5 147320 -136982 front 180 (PN CONN_01X06)) + ) + (component Pin_Headers:Pin_Header_Straight_2x04_Pitch2.54mm + (place LCD1 211811 -127406 front 0 (PN CONN_02X04)) + ) + (component Pin_Headers:Pin_Header_Straight_1x02_Pitch2.54mm + (place J1 152819 -136881 front 180 (PN CONN_01X02)) + ) + (component Pin_Headers:Pin_Header_Straight_2x03_Pitch2.54mm + (place J2 147320 -106820 front 0 (PN CONN_02X03)) + ) + ) + (library + (image Modules:Arduino_Nano_WithMountingHoles + (outline (path signal 120 1270 -1270 1270 1270)) + (outline (path signal 120 1270 1270 -1400 1270)) + (outline (path signal 120 -1400 -1270 -1400 -39500)) + (outline (path signal 120 -1400 3940 -1400 1270)) + (outline (path signal 120 13970 1270 16640 1270)) + (outline (path signal 120 13970 1270 13970 -36830)) + (outline (path signal 120 13970 -36830 16640 -36830)) + (outline (path signal 120 1270 -1270 -1400 -1270)) + (outline (path signal 120 1270 -1270 1270 -36830)) + (outline (path signal 120 1270 -36830 -1400 -36830)) + (outline (path signal 100 3810 -31750 11430 -31750)) + (outline (path signal 100 11430 -31750 11430 -41910)) + (outline (path signal 100 11430 -41910 3810 -41910)) + (outline (path signal 100 3810 -41910 3810 -31750)) + (outline (path signal 120 -1400 -39500 16640 -39500)) + (outline (path signal 120 16640 -39500 16640 3940)) + (outline (path signal 120 16640 3940 -1400 3940)) + (outline (path signal 100 16510 -39370 -1270 -39370)) + (outline (path signal 100 -1270 -39370 -1270 2540)) + (outline (path signal 100 -1270 2540 0 3810)) + (outline (path signal 100 0 3810 16510 3810)) + (outline (path signal 100 16510 3810 16510 -39370)) + (outline (path signal 50 -1530 4060 16750 4060)) + (outline (path signal 50 -1530 4060 -1530 -42160)) + (outline (path signal 50 16750 -42160 16750 4060)) + (outline (path signal 50 16750 -42160 -1530 -42160)) + (pin Rect[A]Pad_1600x1600_um 1 0 0) + (pin Oval[A]Pad_1600x1600_um 17 15240 -33020) + (pin Oval[A]Pad_1600x1600_um 2 0 -2540) + (pin Oval[A]Pad_1600x1600_um 18 15240 -30480) + (pin Oval[A]Pad_1600x1600_um 3 0 -5080) + (pin Oval[A]Pad_1600x1600_um 19 15240 -27940) + (pin Oval[A]Pad_1600x1600_um 4 0 -7620) + (pin Oval[A]Pad_1600x1600_um 20 15240 -25400) + (pin Oval[A]Pad_1600x1600_um 5 0 -10160) + (pin Oval[A]Pad_1600x1600_um 21 15240 -22860) + (pin Oval[A]Pad_1600x1600_um 6 0 -12700) + (pin Oval[A]Pad_1600x1600_um 22 15240 -20320) + (pin Oval[A]Pad_1600x1600_um 7 0 -15240) + (pin Oval[A]Pad_1600x1600_um 23 15240 -17780) + (pin Oval[A]Pad_1600x1600_um 8 0 -17780) + (pin Oval[A]Pad_1600x1600_um 24 15240 -15240) + (pin Oval[A]Pad_1600x1600_um 9 0 -20320) + (pin Oval[A]Pad_1600x1600_um 25 15240 -12700) + (pin Oval[A]Pad_1600x1600_um 10 0 -22860) + (pin Oval[A]Pad_1600x1600_um 26 15240 -10160) + (pin Oval[A]Pad_1600x1600_um 11 0 -25400) + (pin Oval[A]Pad_1600x1600_um 27 15240 -7620) + (pin Oval[A]Pad_1600x1600_um 12 0 -27940) + (pin Oval[A]Pad_1600x1600_um 28 15240 -5080) + (pin Oval[A]Pad_1600x1600_um 13 0 -30480) + (pin Oval[A]Pad_1600x1600_um 29 15240 -2540) + (pin Oval[A]Pad_1600x1600_um 14 0 -33020) + (pin Oval[A]Pad_1600x1600_um 30 15240 0) + (pin Oval[A]Pad_1600x1600_um 15 0 -35560) + (pin Oval[A]Pad_1600x1600_um 16 15240 -35560) + (keepout "" (circle F.Cu 1780 0 2540)) + (keepout "" (circle B.Cu 1780 0 2540)) + (keepout "" (circle F.Cu 1780 15240 2540)) + (keepout "" (circle B.Cu 1780 15240 2540)) + (keepout "" (circle F.Cu 1780 15240 -38100)) + (keepout "" (circle B.Cu 1780 15240 -38100)) + (keepout "" (circle F.Cu 1780 0 -38100)) + (keepout "" (circle B.Cu 1780 0 -38100)) + ) + (image "Modules:Pololu_Breakout-16_15.2x20.3mm" + (outline (path signal 120 11430 1400 11430 -19180)) + (outline (path signal 120 1270 -1270 1270 -19180)) + (outline (path signal 120 0 1400 -1400 1400)) + (outline (path signal 120 -1400 1400 -1400 0)) + (outline (path signal 120 1270 1400 1270 -1270)) + (outline (path signal 120 1270 -1270 -1400 -1270)) + (outline (path signal 120 -1400 -1270 -1400 -19180)) + (outline (path signal 120 -1400 -19180 14100 -19180)) + (outline (path signal 120 14100 -19180 14100 1400)) + (outline (path signal 120 14100 1400 1270 1400)) + (outline (path signal 100 -1270 0 0 1270)) + (outline (path signal 100 0 1270 13970 1270)) + (outline (path signal 100 13970 1270 13970 -19050)) + (outline (path signal 100 13970 -19050 -1270 -19050)) + (outline (path signal 100 -1270 -19050 -1270 0)) + (outline (path signal 50 -1530 1520 14210 1520)) + (outline (path signal 50 -1530 1520 -1530 -19300)) + (outline (path signal 50 14210 -19300 14210 1520)) + (outline (path signal 50 14210 -19300 -1530 -19300)) + (pin Rect[A]Pad_1600x1600_um 1 0 0) + (pin Oval[A]Pad_1600x1600_um 9 12700 -17780) + (pin Oval[A]Pad_1600x1600_um 2 0 -2540) + (pin Oval[A]Pad_1600x1600_um 10 12700 -15240) + (pin Oval[A]Pad_1600x1600_um 3 0 -5080) + (pin Oval[A]Pad_1600x1600_um 11 12700 -12700) + (pin Oval[A]Pad_1600x1600_um 4 0 -7620) + (pin Oval[A]Pad_1600x1600_um 12 12700 -10160) + (pin Oval[A]Pad_1600x1600_um 5 0 -10160) + (pin Oval[A]Pad_1600x1600_um 13 12700 -7620) + (pin Oval[A]Pad_1600x1600_um 6 0 -12700) + (pin Oval[A]Pad_1600x1600_um 14 12700 -5080) + (pin Oval[A]Pad_1600x1600_um 7 0 -15240) + (pin Oval[A]Pad_1600x1600_um 15 12700 -2540) + (pin Oval[A]Pad_1600x1600_um 8 0 -17780) + (pin Oval[A]Pad_1600x1600_um 16 12700 0) + ) + (image Resistors_ThroughHole:Resistor_Horizontal_RM7mm + (outline (path signal 50 -1250 1500 8850 1500)) + (outline (path signal 50 -1250 -1500 -1250 1500)) + (outline (path signal 50 8850 1500 8850 -1500)) + (outline (path signal 50 -1250 -1500 8850 -1500)) + (outline (path signal 150 1270 1270 6350 1270)) + (outline (path signal 150 6350 1270 6350 -1270)) + (outline (path signal 150 6350 -1270 1270 -1270)) + (outline (path signal 150 1270 -1270 1270 1270)) + (pin Round[A]Pad_1998.98_um 1 0 0) + (pin Round[A]Pad_1998.98_um 2 7620 0) + ) + (image "sparkfun:SF-ROTARY-ENCODER" + (outline (path signal 203.2 3000 1500 -3000 1500)) + (outline (path signal 203.2 3500 0 3328.7 -1081.56 2831.56 -2057.25 2057.25 -2831.56 + 1081.56 -3328.7 0 -3500 -1081.56 -3328.7 -2057.25 -2831.56 + -2831.56 -2057.25 -3328.7 -1081.56 -3500 0 -3328.7 1081.56 + -2831.56 2057.25 -2057.25 2831.56 -1081.56 3328.7 0 3500 + 1081.56 3328.7 2057.25 2831.56 2831.56 2057.25 3328.7 1081.56)) + (outline (path signal 203.2 6000 -6500 -6000 -6500)) + (outline (path signal 203.2 -6000 -6500 -6000 6500)) + (outline (path signal 203.2 -6000 6500 6000 6500)) + (outline (path signal 203.2 6000 6500 6000 -6500)) + (pin Round[A]Pad_1800_um 1 -2500 7000) + (pin Round[A]Pad_1800_um 2 -2500 -7500) + (pin Round[A]Pad_1800_um 3 0 -7500) + (pin Round[A]Pad_1800_um 4 2500 -7500) + (pin Round[A]Pad_1800_um 5 2500 7000) + (pin Round[A]Pad_3000_um @1 5600 0) + (pin Round[A]Pad_3000_um @2 -5600 0) + ) + (image Pin_Headers:Pin_Header_Straight_1x06_Pitch2.54mm + (outline (path signal 100 -1270 1270 -1270 -13970)) + (outline (path signal 100 -1270 -13970 1270 -13970)) + (outline (path signal 100 1270 -13970 1270 1270)) + (outline (path signal 100 1270 1270 -1270 1270)) + (outline (path signal 120 -1330 -1270 -1330 -14030)) + (outline (path signal 120 -1330 -14030 1330 -14030)) + (outline (path signal 120 1330 -14030 1330 -1270)) + (outline (path signal 120 1330 -1270 -1330 -1270)) + (outline (path signal 120 -1330 0 -1330 1330)) + (outline (path signal 120 -1330 1330 0 1330)) + (outline (path signal 50 -1800 1800 -1800 -14500)) + (outline (path signal 50 -1800 -14500 1800 -14500)) + (outline (path signal 50 1800 -14500 1800 1800)) + (outline (path signal 50 1800 1800 -1800 1800)) + (pin Rect[A]Pad_1700x1700_um 1 0 0) + (pin Oval[A]Pad_1700x1700_um 2 0 -2540) + (pin Oval[A]Pad_1700x1700_um 3 0 -5080) + (pin Oval[A]Pad_1700x1700_um 4 0 -7620) + (pin Oval[A]Pad_1700x1700_um 5 0 -10160) + (pin Oval[A]Pad_1700x1700_um 6 0 -12700) + ) + (image Pin_Headers:Pin_Header_Straight_2x04_Pitch2.54mm + (outline (path signal 100 -1270 1270 -1270 -8890)) + (outline (path signal 100 -1270 -8890 3810 -8890)) + (outline (path signal 100 3810 -8890 3810 1270)) + (outline (path signal 100 3810 1270 -1270 1270)) + (outline (path signal 120 -1330 -1270 -1330 -8950)) + (outline (path signal 120 -1330 -8950 3870 -8950)) + (outline (path signal 120 3870 -8950 3870 1330)) + (outline (path signal 120 3870 1330 1270 1330)) + (outline (path signal 120 1270 1330 1270 -1270)) + (outline (path signal 120 1270 -1270 -1330 -1270)) + (outline (path signal 120 -1330 0 -1330 1330)) + (outline (path signal 120 -1330 1330 0 1330)) + (outline (path signal 50 -1800 1800 -1800 -9400)) + (outline (path signal 50 -1800 -9400 4350 -9400)) + (outline (path signal 50 4350 -9400 4350 1800)) + (outline (path signal 50 4350 1800 -1800 1800)) + (pin Rect[A]Pad_1700x1700_um 1 0 0) + (pin Oval[A]Pad_1700x1700_um 2 2540 0) + (pin Oval[A]Pad_1700x1700_um 3 0 -2540) + (pin Oval[A]Pad_1700x1700_um 4 2540 -2540) + (pin Oval[A]Pad_1700x1700_um 5 0 -5080) + (pin Oval[A]Pad_1700x1700_um 6 2540 -5080) + (pin Oval[A]Pad_1700x1700_um 7 0 -7620) + (pin Oval[A]Pad_1700x1700_um 8 2540 -7620) + ) + (image Pin_Headers:Pin_Header_Straight_1x02_Pitch2.54mm + (outline (path signal 100 -1270 1270 -1270 -3810)) + (outline (path signal 100 -1270 -3810 1270 -3810)) + (outline (path signal 100 1270 -3810 1270 1270)) + (outline (path signal 100 1270 1270 -1270 1270)) + (outline (path signal 120 -1330 -1270 -1330 -3870)) + (outline (path signal 120 -1330 -3870 1330 -3870)) + (outline (path signal 120 1330 -3870 1330 -1270)) + (outline (path signal 120 1330 -1270 -1330 -1270)) + (outline (path signal 120 -1330 0 -1330 1330)) + (outline (path signal 120 -1330 1330 0 1330)) + (outline (path signal 50 -1800 1800 -1800 -4350)) + (outline (path signal 50 -1800 -4350 1800 -4350)) + (outline (path signal 50 1800 -4350 1800 1800)) + (outline (path signal 50 1800 1800 -1800 1800)) + (pin Rect[A]Pad_1700x1700_um 1 0 0) + (pin Oval[A]Pad_1700x1700_um 2 0 -2540) + ) + (image Pin_Headers:Pin_Header_Straight_2x03_Pitch2.54mm + (outline (path signal 100 -1270 1270 -1270 -6350)) + (outline (path signal 100 -1270 -6350 3810 -6350)) + (outline (path signal 100 3810 -6350 3810 1270)) + (outline (path signal 100 3810 1270 -1270 1270)) + (outline (path signal 120 -1330 -1270 -1330 -6410)) + (outline (path signal 120 -1330 -6410 3870 -6410)) + (outline (path signal 120 3870 -6410 3870 1330)) + (outline (path signal 120 3870 1330 1270 1330)) + (outline (path signal 120 1270 1330 1270 -1270)) + (outline (path signal 120 1270 -1270 -1330 -1270)) + (outline (path signal 120 -1330 0 -1330 1330)) + (outline (path signal 120 -1330 1330 0 1330)) + (outline (path signal 50 -1800 1800 -1800 -6850)) + (outline (path signal 50 -1800 -6850 4350 -6850)) + (outline (path signal 50 4350 -6850 4350 1800)) + (outline (path signal 50 4350 1800 -1800 1800)) + (pin Rect[A]Pad_1700x1700_um 1 0 0) + (pin Oval[A]Pad_1700x1700_um 2 2540 0) + (pin Oval[A]Pad_1700x1700_um 3 0 -2540) + (pin Oval[A]Pad_1700x1700_um 4 2540 -2540) + (pin Oval[A]Pad_1700x1700_um 5 0 -5080) + (pin Oval[A]Pad_1700x1700_um 6 2540 -5080) + ) + (padstack Round[A]Pad_1800_um + (shape (circle F.Cu 1800)) + (shape (circle B.Cu 1800)) + (attach off) + ) + (padstack Round[A]Pad_1998.98_um + (shape (circle F.Cu 1998.98)) + (shape (circle B.Cu 1998.98)) + (attach off) + ) + (padstack Round[A]Pad_3000_um + (shape (circle F.Cu 3000)) + (shape (circle B.Cu 3000)) + (attach off) + ) + (padstack Oval[A]Pad_1600x1600_um + (shape (path F.Cu 1600 0 0 0 0)) + (shape (path B.Cu 1600 0 0 0 0)) + (attach off) + ) + (padstack Oval[A]Pad_1700x1700_um + (shape (path F.Cu 1700 0 0 0 0)) + (shape (path B.Cu 1700 0 0 0 0)) + (attach off) + ) + (padstack Rect[A]Pad_1600x1600_um + (shape (rect F.Cu -800 -800 800 800)) + (shape (rect B.Cu -800 -800 800 800)) + (attach off) + ) + (padstack Rect[A]Pad_1700x1700_um + (shape (rect F.Cu -850 -850 850 850)) + (shape (rect B.Cu -850 -850 850 850)) + (attach off) + ) + (padstack "Via[0-1]_600:400_um" + (shape (circle F.Cu 600)) + (shape (circle B.Cu 600)) + (attach off) + ) + ) + (network + (net "Net-(A1-Pad1)" + (pins A1-1) + ) + (net "Net-(A1-Pad17)" + (pins A1-17) + ) + (net "Net-(A1-Pad2)" + (pins A1-2) + ) + (net "Net-(A1-Pad18)" + (pins A1-18) + ) + (net "Net-(A1-Pad3)" + (pins A1-3) + ) + (net "Net-(A1-Pad19)" + (pins A1-19) + ) + (net GND + (pins A1-4 A1-29 A2-1 A2-7 SW1-2 LCD1-1 J1-2 J2-2 J2-4 J2-6) + ) + (net "Net-(A1-Pad20)" + (pins A1-20) + ) + (net "Net-(A1-Pad5)" + (pins A1-5 A2-16) + ) + (net "Net-(A1-Pad21)" + (pins A1-21) + ) + (net "Net-(A1-Pad6)" + (pins A1-6 A2-15) + ) + (net "Net-(A1-Pad22)" + (pins A1-22) + ) + (net /BTN1 + (pins A1-7 R2-2 J2-5) + ) + (net "Net-(A1-Pad23)" + (pins A1-23) + ) + (net "Net-(A1-Pad24)" + (pins A1-24) + ) + (net /RS + (pins A1-25 LCD1-5) + ) + (net ROT_BUT + (pins A1-10 SW1-4) + ) + (net /EN + (pins A1-26 LCD1-7) + ) + (net ROT_C + (pins A1-11 SW1-3) + ) + (net +5V + (pins A1-27 A2-13 A2-14 R1-2 R2-1 R3-2 R4-1 LCD1-3) + ) + (net ROT_A + (pins A1-12 SW1-1) + ) + (net "Net-(A1-Pad28)" + (pins A1-28) + ) + (net /D4 + (pins A1-13 LCD1-2) + ) + (net /D5 + (pins A1-14 LCD1-4) + ) + (net +12V + (pins A2-8 J1-1) + ) + (net /D6 + (pins A1-15 LCD1-6) + ) + (net /D7 + (pins A1-16 LCD1-8) + ) + (net "Net-(A2-Pad9)" + (pins A2-9) + ) + (net "Net-(A2-Pad2)" + (pins A2-2) + ) + (net "Net-(A2-Pad10)" + (pins A2-10) + ) + (net "Net-(A2-Pad3)" + (pins A2-3 J5-3) + ) + (net "Net-(A2-Pad11)" + (pins A2-11) + ) + (net "Net-(A2-Pad4)" + (pins A2-4 J5-1) + ) + (net "Net-(A2-Pad12)" + (pins A2-12) + ) + (net "Net-(A2-Pad5)" + (pins A2-5 J5-4) + ) + (net "Net-(A2-Pad6)" + (pins A2-6 J5-6) + ) + (net "Net-(R4-Pad2)" + (pins R4-2 SW1-5) + ) + (net "Net-(J5-Pad2)" + (pins J5-2) + ) + (net "Net-(J5-Pad5)" + (pins J5-5) + ) + (net +6V + (pins A1-30) + ) + (net "Net-(A1-Pad8)" + (pins A1-8 R3-1 J2-3) + ) + (net "Net-(A1-Pad9)" + (pins A1-9 R1-1 J2-1) + ) + (class kicad_default "" +12V +5V +6V /BTN1 /D4 /D5 /D6 /D7 /EN /RS GND + "Net-(A1-Pad1)" "Net-(A1-Pad17)" "Net-(A1-Pad18)" "Net-(A1-Pad19)" "Net-(A1-Pad2)" + "Net-(A1-Pad20)" "Net-(A1-Pad21)" "Net-(A1-Pad22)" "Net-(A1-Pad23)" + "Net-(A1-Pad24)" "Net-(A1-Pad28)" "Net-(A1-Pad3)" "Net-(A1-Pad5)" "Net-(A1-Pad6)" + "Net-(A1-Pad8)" "Net-(A1-Pad9)" "Net-(A2-Pad10)" "Net-(A2-Pad11)" "Net-(A2-Pad12)" + "Net-(A2-Pad2)" "Net-(A2-Pad3)" "Net-(A2-Pad4)" "Net-(A2-Pad5)" "Net-(A2-Pad6)" + "Net-(A2-Pad9)" "Net-(J5-Pad2)" "Net-(J5-Pad5)" "Net-(R4-Pad2)" ROT_A + ROT_BUT ROT_C + (circuit + (use_via Via[0-1]_600:400_um) + ) + (rule + (width 250) + (clearance 200.1) + ) + ) + ) + (wiring + ) +) diff --git a/kicad/startracker.kicad_pcb b/kicad/startracker.kicad_pcb index aca054d..8f49a37 100644 --- a/kicad/startracker.kicad_pcb +++ b/kicad/startracker.kicad_pcb @@ -5,7 +5,7 @@ (no_connects 3) (area 140.310799 93.447799 226.719201 154.051001) (thickness 1.6) - (drawings 8) + (drawings 13) (tracks 226) (zones 0) (modules 13) @@ -782,10 +782,25 @@ ) ) + (gr_text StarTracker (at 213.5378 149.4155) (layer F.SilkS) + (effects (font (size 1.5 1.5) (thickness 0.3))) + ) + (gr_text 12V (at 148.2471 150.7744) (layer F.SilkS) + (effects (font (size 1.5 1.5) (thickness 0.3))) + ) + (gr_text USB (at 194.3227 144.9832) (layer F.SilkS) + (effects (font (size 1.5 1.5) (thickness 0.3))) + ) + (gr_text 7.5V (at 207.7593 106.3371) (layer F.SilkS) + (effects (font (size 1.5 1.5) (thickness 0.3))) + ) + (gr_text LCD (at 213.106 139.6365) (layer F.SilkS) + (effects (font (size 1.5 1.5) (thickness 0.3))) + ) (gr_text 7.5V (at 207.645 105.8926) (layer B.Cu) (effects (font (size 1.5 1.5) (thickness 0.3)) (justify mirror)) ) - (gr_text "StartTracker 0.9" (at 215.3158 151.511) (layer B.Cu) + (gr_text "StarTracker 0.9" (at 215.3158 151.511) (layer B.Cu) (effects (font (size 1.5 1.5) (thickness 0.3)) (justify mirror)) ) (gr_text 12V (at 148.1963 150.0378) (layer B.Cu) diff --git a/kicad/startracker.rules b/kicad/startracker.rules new file mode 100644 index 0000000..818f0ed --- /dev/null +++ b/kicad/startracker.rules @@ -0,0 +1,81 @@ + +(rules PCB startracker + (snap_angle + fortyfive_degree + ) + (autoroute_settings + (fanout off) + (autoroute on) + (postroute on) + (vias on) + (via_costs 50) + (plane_via_costs 5) + (start_ripup_costs 100) + (start_pass_no 1046) + (layer_rule F.Cu + (active on) + (preferred_direction horizontal) + (preferred_direction_trace_costs 50.0) + (against_preferred_direction_trace_costs 2.6) + ) + (layer_rule B.Cu + (active on) + (preferred_direction vertical) + (preferred_direction_trace_costs 1.0) + (against_preferred_direction_trace_costs 1.6) + ) + ) + (rule + (width 400.0) + (clear 200.2) + (clear 125.0 (type smd_to_turn_gap)) + (clear 50.0 (type smd_smd)) + ) + (padstack "Via[0-1]_600:400_um" + (shape + (circle F.Cu 600.0 0.0 0.0) + ) + (shape + (circle B.Cu 600.0 0.0 0.0) + ) + (attach off) + ) + (via + "Via[0-1]_600:400_um" "Via[0-1]_600:400_um" default + ) + (via + "Via[0-1]_600:400_um-kicad_default" "Via[0-1]_600:400_um" "kicad_default" + ) + (via_rule + default "Via[0-1]_600:400_um" + ) + (via_rule + "kicad_default" "Via[0-1]_600:400_um-kicad_default" + ) + (class default + (clearance_class default) + (via_rule default) + (rule + (width 400.0) + ) + (circuit + (use_layer F.Cu B.Cu) + ) + ) + (class "kicad_default" + "Net-(A1-Pad1)" "Net-(A1-Pad17)" "Net-(A1-Pad2)" "Net-(A1-Pad18)" "Net-(A1-Pad3)" "Net-(A1-Pad19)" GND "Net-(A1-Pad20)" + "Net-(A1-Pad5)" "Net-(A1-Pad21)" "Net-(A1-Pad6)" "Net-(A1-Pad22)" /BTN1 "Net-(A1-Pad23)" "Net-(A1-Pad24)" /RS + "ROT_BUT" /EN "ROT_C" +5V "ROT_A" "Net-(A1-Pad28)" /D4 /D5 + +12V /D6 /D7 "Net-(A2-Pad9)" "Net-(A2-Pad2)" "Net-(A2-Pad10)" "Net-(A2-Pad3)" "Net-(A2-Pad11)" + "Net-(A2-Pad4)" "Net-(A2-Pad12)" "Net-(A2-Pad5)" "Net-(A2-Pad6)" "Net-(R4-Pad2)" "Net-(J5-Pad2)" "Net-(J5-Pad5)" +6V + "Net-(A1-Pad8)" "Net-(A1-Pad9)" + (clearance_class "kicad_default") + (via_rule kicad_default) + (rule + (width 400.0) + ) + (circuit + (use_layer F.Cu B.Cu) + ) + ) +) \ No newline at end of file diff --git a/kicad/startracker.ses b/kicad/startracker.ses new file mode 100644 index 0000000..5f0c8d0 --- /dev/null +++ b/kicad/startracker.ses @@ -0,0 +1,802 @@ + +(session startracker.ses + (base_design startracker.dsn) + (placement + (resolution um 10) + (component Modules:Arduino_Nano_WithMountingHoles + (place A1 1864610 -1021590 front 0) + ) + (component "Modules:Pololu_Breakout-16_15.2x20.3mm" + (place A2 1585720 -1194180 front 0) + ) + (component Resistors_ThroughHole:Resistor_Horizontal_RM7mm + (place R1 1796540 -1068320 front 90) + (place R2 1572510 -1066550 front 0) + (place R3 1725800 -1137410 front 90) + (place R4 1579630 -1135510 front 0) + ) + (component "sparkfun:SF-ROTARY-ENCODER" + (place SW1 2145800 -1052070 front 0) + ) + (component Pin_Headers:Pin_Header_Straight_1x06_Pitch2.54mm + (place J5 1473200 -1369820 front 180) + ) + (component Pin_Headers:Pin_Header_Straight_2x04_Pitch2.54mm + (place LCD1 2118110 -1274060 front 0) + ) + (component Pin_Headers:Pin_Header_Straight_1x02_Pitch2.54mm + (place J1 1528190 -1368810 front 180) + ) + (component Pin_Headers:Pin_Header_Straight_2x03_Pitch2.54mm + (place J2 1473200 -1068200 front 0) + ) + ) + (was_is + ) + (routes + (resolution um 10) + (parser + (host_cad "KiCad's Pcbnew") + (host_version "4.0.5+dfsg1-4") + ) + (library_out + (padstack "Via[0-1]_600:400_um" + (shape + (circle F.Cu 6000 0 0) + ) + (shape + (circle B.Cu 6000 0 0) + ) + (attach off) + ) + ) + (network_out + (net GND + (wire + (path B.Cu 4000 + 1864610 -1097790 + 1876613 -1097790 + ) + ) + (wire + (path B.Cu 4000 + 1876613 -1097790 + 1927413 -1046990 + 2017010 -1046990 + ) + ) + (wire + (path B.Cu 4000 + 1858609 -1097790 + 1864610 -1097790 + ) + ) + (wire + (path B.Cu 4000 + 1460205 -1080900 + 1460205 -1058532 + 1469340 -1049397 + 1506463 -1049397 + 1564679 -1107613 + 1564679 -1141013 + 1573252 -1149586 + 1585373 -1149586 + 1594059 -1140900 + 1594059 -1092416 + 1639972 -1046503 + 1657862 -1046503 + 1669246 -1057887 + 1669246 -1102105 + 1641627 -1129724 + 1641627 -1141364 + 1649865 -1149602 + 1672083 -1149602 + 1767415 -1054270 + 1809087 -1054270 + 1852607 -1097790 + ) + ) + (wire + (path B.Cu 4000 + 1585720 -1194180 + 1521488 -1194180 + 1454100 -1126792 + 1454100 -1087005 + 1460205 -1080900 + ) + ) + (wire + (path B.Cu 4000 + 1498600 -1080900 + 1460205 -1080900 + ) + ) + (wire + (path B.Cu 4000 + 1498600 -1080900 + 1498600 -1068200 + ) + ) + (wire + (path B.Cu 4000 + 1498600 -1093600 + 1498600 -1080900 + ) + ) + (wire + (path B.Cu 4000 + 1498600 -1119000 + 1498600 -1093600 + ) + ) + (wire + (path B.Cu 4000 + 2133976 -1140246 + 2120800 -1127070 + ) + ) + (wire + (path B.Cu 4000 + 2017010 -1046990 + 2040464 -1046990 + 2064548 -1071074 + 2133665 -1071074 + 2184290 -1121699 + 2184290 -1132314 + 2176358 -1140246 + 2133976 -1140246 + ) + ) + (wire + (path B.Cu 4000 + 2118110 -1274060 + 2118110 -1156112 + 2133976 -1140246 + ) + ) + (wire + (path B.Cu 4000 + 1858609 -1097790 + 1852607 -1097790 + ) + ) + (wire + (path B.Cu 4000 + 1585720 -1206183 + 1589471 -1206183 + 1604155 -1220867 + 1604155 -1340148 + 1597723 -1346580 + ) + ) + (wire + (path B.Cu 4000 + 1585720 -1346580 + 1597723 -1346580 + ) + ) + (wire + (path B.Cu 4000 + 1585720 -1194180 + 1585720 -1206183 + ) + ) + (wire + (path B.Cu 4000 + 1528190 -1343410 + 1540693 -1343410 + ) + ) + (wire + (path B.Cu 4000 + 1585720 -1346580 + 1543863 -1346580 + 1540693 -1343410 + ) + ) + ) + (net "Net-(A1-Pad5)" + (wire + (path B.Cu 4000 + 1864610 -1123190 + 1876613 -1123190 + ) + ) + (wire + (path B.Cu 4000 + 1712720 -1194180 + 1724723 -1194180 + ) + ) + (wire + (path B.Cu 4000 + 1724723 -1194180 + 1767520 -1236977 + 1872927 -1236977 + 1888705 -1221199 + 1888705 -1135282 + 1876613 -1123190 + ) + ) + ) + (net "Net-(A1-Pad6)" + (wire + (path B.Cu 4000 + 1864610 -1148590 + 1864610 -1160593 + ) + ) + (wire + (path B.Cu 4000 + 1712720 -1219580 + 1712720 -1207577 + ) + ) + (wire + (path B.Cu 4000 + 1712720 -1207577 + 1708969 -1207577 + 1700628 -1199236 + 1700628 -1189185 + 1708080 -1181733 + 1720768 -1181733 + 1751125 -1212090 + 1869020 -1212090 + 1876613 -1204497 + 1876613 -1168866 + 1868340 -1160593 + 1864610 -1160593 + ) + ) + ) + (net /BTN1 + (wire + (path B.Cu 4000 + 1617611 -1134326 + 1617611 -1097649 + 1648710 -1066550 + ) + ) + (wire + (path B.Cu 4000 + 1485703 -1119000 + 1485703 -1124470 + 1522825 -1161592 + 1590345 -1161592 + 1617611 -1134326 + ) + ) + (wire + (path B.Cu 4000 + 1617611 -1134326 + 1644893 -1161608 + 1677055 -1161608 + 1715455 -1123208 + 1801825 -1123208 + 1852607 -1173990 + ) + ) + (wire + (path B.Cu 4000 + 1864610 -1173990 + 1852607 -1173990 + ) + ) + (wire + (path B.Cu 4000 + 1473200 -1119000 + 1485703 -1119000 + ) + ) + ) + (net /RS + (wire + (path B.Cu 4000 + 2118110 -1312357 + 2112640 -1312357 + 2036409 -1236126 + 2036409 -1176262 + 2020740 -1160593 + 2017010 -1160593 + ) + ) + (wire + (path B.Cu 4000 + 2017010 -1148590 + 2017010 -1160593 + ) + ) + (wire + (path B.Cu 4000 + 2118110 -1324860 + 2118110 -1312357 + ) + ) + ) + (net ROT_BUT + (wire + (path B.Cu 4000 + 1864610 -1250190 + 1868938 -1250190 + 1914001 -1205127 + 1914001 -1158159 + 2011853 -1060307 + 2045290 -1060307 + 2064766 -1079783 + 2123513 -1079783 + 2170800 -1127070 + ) + ) + ) + (net /EN + (wire + (path B.Cu 4000 + 2017010 -1123190 + 2017010 -1135193 + ) + ) + (wire + (path B.Cu 4000 + 2118110 -1350260 + 2118110 -1337757 + ) + ) + (wire + (path B.Cu 4000 + 2118110 -1337757 + 2112640 -1337757 + 2030405 -1255522 + 2030405 -1221196 + 2021299 -1212090 + 2012134 -1212090 + 2004679 -1204635 + 2004679 -1143793 + 2013279 -1135193 + 2017010 -1135193 + ) + ) + ) + (net ROT_C + (wire + (path B.Cu 4000 + 1864610 -1263587 + 1868340 -1263587 + 1931227 -1200700 + 1931227 -1166116 + 2011557 -1085786 + 2104516 -1085786 + 2145800 -1127070 + ) + ) + (wire + (path B.Cu 4000 + 1864610 -1275590 + 1864610 -1263587 + ) + ) + ) + (net +5V + (wire + (path B.Cu 4000 + 1725800 -1061210 + 1705090 -1040500 + 1612800 -1040500 + 1579630 -1073670 + ) + ) + (wire + (path B.Cu 4000 + 1572510 -1066550 + 1549354 -1043394 + 1466854 -1043394 + 1448028 -1062220 + 1448028 -1367716 + 1462636 -1382324 + 1491733 -1382324 + 1517751 -1356306 + 1558041 -1356306 + 1560675 -1358940 + 1650256 -1358940 + 1700716 -1308480 + 1717453 -1308480 + 1740138 -1285795 + ) + ) + (wire + (path B.Cu 4000 + 1579630 -1073670 + 1579630 -1135510 + ) + ) + (wire + (path B.Cu 4000 + 1572510 -1066550 + 1579630 -1073670 + ) + ) + (wire + (path B.Cu 4000 + 1740138 -1285795 + 1724723 -1270380 + ) + ) + (wire + (path B.Cu 4000 + 2017010 -1104086 + 1987595 -1133501 + 1987595 -1169625 + 1869494 -1287726 + 1742069 -1287726 + 1740138 -1285795 + ) + ) + (wire + (path B.Cu 4000 + 1712720 -1270380 + 1724723 -1270380 + ) + ) + (wire + (path B.Cu 4000 + 2017010 -1104086 + 2017010 -1109793 + ) + ) + (wire + (path B.Cu 4000 + 2017010 -1098379 + 2017010 -1104086 + ) + ) + (wire + (path B.Cu 4000 + 2118110 -1299460 + 2118110 -1286957 + ) + ) + (wire + (path B.Cu 4000 + 1725800 -1061210 + 1794890 -992120 + 1796540 -992120 + ) + ) + (wire + (path B.Cu 4000 + 2017010 -1098379 + 2017010 -1097790 + ) + ) + (wire + (path B.Cu 4000 + 2017010 -1109793 + 2020740 -1109793 + 2098149 -1187202 + 2098149 -1277158 + 2107948 -1286957 + 2118110 -1286957 + ) + ) + (wire + (path B.Cu 4000 + 1712720 -1270380 + 1712720 -1244980 + ) + ) + ) + (net ROT_A + (wire + (path B.Cu 4000 + 1864610 -1312993 + 1860879 -1312993 + 1845643 -1328229 + 1845643 -1402532 + 1864757 -1421646 + 2107507 -1421646 + 2190294 -1338859 + 2190294 -1067439 + 2120800 -997945 + 2120800 -982070 + ) + ) + (wire + (path B.Cu 4000 + 1864610 -1300990 + 1864610 -1312993 + ) + ) + ) + (net /D4 + (wire + (path B.Cu 4000 + 1864610 -1326390 + 1876613 -1326390 + ) + ) + (wire + (path B.Cu 4000 + 2143510 -1274060 + 2143510 -1286563 + ) + ) + (wire + (path B.Cu 4000 + 2143510 -1286563 + 2138039 -1286563 + 2131007 -1293595 + 2131007 -1355087 + 2123231 -1362863 + 2046085 -1362863 + 2022312 -1339090 + 1889313 -1339090 + 1876613 -1326390 + ) + ) + ) + (net /D5 + (wire + (path B.Cu 4000 + 2143510 -1311963 + 2148980 -1311963 + 2162500 -1325483 + 2162500 -1357502 + 2104372 -1415630 + 1897452 -1415630 + 1871076 -1389254 + 1859676 -1389254 + 1852272 -1381850 + 1852272 -1372400 + 1860879 -1363793 + 1864610 -1363793 + ) + ) + (wire + (path B.Cu 4000 + 1864610 -1351790 + 1864610 -1363793 + ) + ) + (wire + (path B.Cu 4000 + 2143510 -1299460 + 2143510 -1311963 + ) + ) + ) + (net +12V + (wire + (path B.Cu 4000 + 1585720 -1371980 + 1573717 -1371980 + ) + ) + (wire + (path B.Cu 4000 + 1528190 -1368810 + 1570547 -1368810 + 1573717 -1371980 + ) + ) + ) + (net /D6 + (wire + (path B.Cu 4000 + 1864610 -1377190 + 1876613 -1377190 + ) + ) + (wire + (path B.Cu 4000 + 2143510 -1324860 + 2143510 -1337363 + ) + ) + (wire + (path B.Cu 4000 + 2143510 -1337363 + 2148980 -1337363 + 2156254 -1344637 + 2156254 -1355226 + 2122226 -1389254 + 1888677 -1389254 + 1876613 -1377190 + ) + ) + ) + (net /D7 + (wire + (path B.Cu 4000 + 2143510 -1350260 + 2143510 -1351263 + 2117583 -1377190 + 2017010 -1377190 + ) + ) + ) + (net "Net-(A2-Pad3)" + (wire + (path B.Cu 4000 + 1585720 -1244980 + 1573717 -1244980 + ) + ) + (wire + (path B.Cu 4000 + 1473200 -1319020 + 1473200 -1306517 + ) + ) + (wire + (path B.Cu 4000 + 1473200 -1306517 + 1467730 -1306517 + 1454391 -1293178 + 1454391 -1235243 + 1465667 -1223967 + 1552704 -1223967 + 1573717 -1244980 + ) + ) + ) + (net "Net-(A2-Pad4)" + (wire + (path B.Cu 4000 + 1473200 -1369820 + 1485703 -1369820 + ) + ) + (wire + (path B.Cu 4000 + 1585720 -1270380 + 1585720 -1282383 + ) + ) + (wire + (path B.Cu 4000 + 1585720 -1282383 + 1589471 -1282383 + 1598058 -1290970 + 1598058 -1325863 + 1590650 -1333271 + 1579809 -1333271 + 1577088 -1330550 + 1522629 -1330550 + 1485703 -1367476 + 1485703 -1369820 + ) + ) + ) + (net "Net-(A2-Pad5)" + (wire + (path B.Cu 4000 + 1585720 -1295780 + 1573717 -1295780 + ) + ) + (wire + (path B.Cu 4000 + 1473200 -1293620 + 1473200 -1281117 + ) + ) + (wire + (path B.Cu 4000 + 1473200 -1281117 + 1467730 -1281117 + 1460516 -1273903 + 1460516 -1237707 + 1467907 -1230316 + 1508253 -1230316 + 1573717 -1295780 + ) + ) + ) + (net "Net-(A2-Pad6)" + (wire + (path B.Cu 4000 + 1473200 -1242820 + 1485703 -1242820 + ) + ) + (wire + (path B.Cu 4000 + 1485703 -1242820 + 1564063 -1321180 + 1585720 -1321180 + ) + ) + ) + (net "Net-(R4-Pad2)" + (wire + (path B.Cu 4000 + 2170800 -982070 + 2157629 -968899 + 1844106 -968899 + 1677495 -1135510 + 1655830 -1135510 + ) + ) + ) + (net "Net-(A1-Pad8)" + (wire + (path B.Cu 4000 + 1473200 -1106103 + 1467730 -1106103 + 1460673 -1113160 + 1460673 -1124874 + 1503410 -1167611 + 1695599 -1167611 + 1725800 -1137410 + ) + ) + (wire + (path B.Cu 4000 + 1473200 -1093600 + 1473200 -1106103 + ) + ) + (wire + (path B.Cu 4000 + 1864610 -1199390 + 1787780 -1199390 + 1725800 -1137410 + ) + ) + ) + (net "Net-(A1-Pad9)" + (wire + (path B.Cu 4000 + 1485703 -1068200 + 1485703 -1063232 + 1493535 -1055400 + 1503507 -1055400 + 1556555 -1108448 + 1556555 -1141378 + 1570766 -1155589 + 1587859 -1155589 + 1602003 -1141445 + 1602003 -1093302 + 1642799 -1052506 + 1654714 -1052506 + 1663226 -1061018 + 1663226 -1099636 + 1635624 -1127238 + 1635624 -1143850 + 1647379 -1155605 + 1674569 -1155605 + 1757815 -1072359 + 1796540 -1072359 + ) + ) + (wire + (path B.Cu 4000 + 1473200 -1068200 + 1485703 -1068200 + ) + ) + (wire + (path B.Cu 4000 + 1796540 -1072359 + 1796540 -1068320 + ) + ) + (wire + (path B.Cu 4000 + 1876613 -1224790 + 1882616 -1218787 + 1882616 -1149619 + 1868191 -1135194 + 1859375 -1135194 + 1796540 -1072359 + ) + ) + (wire + (path B.Cu 4000 + 1864610 -1224790 + 1876613 -1224790 + ) + ) + ) + ) + ) +) \ No newline at end of file