Stm32f04x additions for RCC (#17)
Some new logic to select clock source
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3691709340
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1924bb15cc
154
src/rcc.rs
154
src/rcc.rs
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@ -1,3 +1,4 @@
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use core::cmp;
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use crate::time::Hertz;
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/// Extension trait that constrains the `RCC` peripheral
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@ -14,6 +15,8 @@ impl RccExt for crate::stm32::RCC {
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hclk: None,
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pclk: None,
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sysclk: None,
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enable_hsi: true,
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enable_hsi48: false,
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},
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}
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}
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@ -26,12 +29,32 @@ pub struct Rcc {
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#[allow(unused)]
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const HSI: u32 = 8_000_000; // Hz
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#[allow(unused)]
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const HSI48: u32 = 48_000_000; // Hz - (available on STM32F04x, STM32F07x and STM32F09x devices only)
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#[allow(unused)]
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enum SysClkSource {
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HSI = 0b00,
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HSE = 0b01,
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PLL = 0b10,
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HSI48 = 0b11,
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}
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#[allow(unused)]
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enum PllSource {
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HSI_DIV2 = 0b00,
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HSI = 0b01,
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HSE = 0b10,
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HSI48 = 0b11,
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}
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#[allow(unused)]
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pub struct CFGR {
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hclk: Option<u32>,
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pclk: Option<u32>,
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sysclk: Option<u32>,
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enable_hsi: bool,
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enable_hsi48: bool,
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}
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#[cfg(feature = "device-selected")]
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@ -60,20 +83,58 @@ impl CFGR {
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self
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}
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pub fn freeze(self) -> Clocks {
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let pllmul = (4 * self.sysclk.unwrap_or(HSI) + HSI) / HSI / 2;
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let pllmul = core::cmp::min(core::cmp::max(pllmul, 2), 16);
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let sysclk = pllmul * HSI / 2;
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pub fn enable_hsi(mut self, is_enabled: bool) -> Self {
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self.enable_hsi = is_enabled;
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self
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}
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let pllmul_bits = if pllmul == 2 {
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None
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#[cfg(feature = "stm32f042")]
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pub fn enable_hsi48(mut self, is_enabled: bool) -> Self {
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self.enable_hsi48 = is_enabled;
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self
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}
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pub fn freeze(self) -> Clocks {
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// Default to lowest frequency clock on all systems.
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let sysclk = self.sysclk.unwrap_or(HSI);
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let r_sysclk; // The "real" sysclock value, calculated below
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let src_clk_freq; // Frequency of source clock for PLL and etc, HSI, or HSI48 on supported systems.
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let pllmul_bits;
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// Select clock source based on user input and capability
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// Highest selected frequency source available takes precedent.
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// For F04x, F07x, F09x parts, use HSI48 if requested.
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if self.enable_hsi48 {
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src_clk_freq = HSI48; // Use HSI48 if requested and available.
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} else if self.enable_hsi {
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src_clk_freq = HSI; // HSI if requested
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} else {
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Some(pllmul as u8 - 2)
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};
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src_clk_freq = HSI; // If no clock source is selected use HSI.
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}
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// Pll check
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if sysclk == src_clk_freq {
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// Bypass pll if src clk and requested sysclk are the same, to save power.
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// The only reason to override this behaviour is if the sysclk source were HSI, and you
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// were running the USB off the PLL...
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pllmul_bits = None;
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r_sysclk = src_clk_freq;
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} else {
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let pllmul = (4 * self.sysclk.unwrap_or(src_clk_freq) + src_clk_freq) / src_clk_freq / 2;
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let pllmul = cmp::min(cmp::max(pllmul, 2), 16);
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r_sysclk = pllmul * src_clk_freq / 2;
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pllmul_bits = if pllmul == 2 {
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None
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} else {
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Some(pllmul as u8 - 2)
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};
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}
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let hpre_bits = self
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.hclk
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.map(|hclk| match sysclk / hclk {
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.map(|hclk| match r_sysclk / hclk {
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0 => unreachable!(),
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1 => 0b0111,
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2 => 0b1000,
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@ -119,24 +180,69 @@ impl CFGR {
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}
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let rcc = unsafe { &*crate::stm32::RCC::ptr() };
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if let Some(pllmul_bits) = pllmul_bits {
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// use PLL as source
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rcc.cfgr.write(|w| unsafe { w.pllmul().bits(pllmul_bits) });
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rcc.cr.write(|w| w.pllon().set_bit());
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while rcc.cr.read().pllrdy().bit_is_clear() {}
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rcc.cfgr.modify(|_, w| unsafe {
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w.ppre().bits(ppre_bits).hpre().bits(hpre_bits).sw().bits(2)
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});
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} else {
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// use HSI as source
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rcc.cfgr
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.write(|w| unsafe { w.ppre().bits(ppre_bits).hpre().bits(hpre_bits).sw().bits(0) });
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// Set up rcc based on above calculated configuration.
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// Enable requested clock sources
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// HSI
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if self.enable_hsi {
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rcc.cr.write(|w| w.hsion().set_bit());
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while rcc.cr.read().hsirdy().bit_is_clear() { }
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}
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// HSI48
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if self.enable_hsi48 {
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rcc.cr2.modify(|_, w| w.hsi48on().set_bit());
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while rcc.cr2.read().hsi48rdy().bit_is_clear() { }
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}
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// Enable PLL
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if let Some(pllmul_bits) = pllmul_bits {
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rcc.cfgr.write(|w| unsafe { w.pllmul().bits(pllmul_bits) });
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// Set PLL source based on configuration.
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if self.enable_hsi48 {
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rcc.cfgr.modify(|_, w| w.pllsrc().bits(PllSource::HSI48 as u8));
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} else if self.enable_hsi {
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rcc.cfgr.modify(|_, w| w.pllsrc().bits(PllSource::HSI_DIV2 as u8));
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} else {
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rcc.cfgr.modify(|_, w| w.pllsrc().bits(PllSource::HSI_DIV2 as u8));
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}
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rcc.cr.write(|w| w.pllon().set_bit());
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while rcc.cr.read().pllrdy().bit_is_clear() { }
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rcc.cfgr.modify(|_, w| unsafe {
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w.ppre()
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.bits(ppre_bits)
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.hpre()
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.bits(hpre_bits)
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.sw()
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.bits(SysClkSource::PLL as u8)
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});
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} else { // No PLL required.
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// Setup requested clocks.
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if self.enable_hsi48 {
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rcc.cfgr.modify(|_, w| unsafe {
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w.ppre().bits(ppre_bits)
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.hpre().bits(hpre_bits)
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.sw().bits(SysClkSource::HSI48 as u8)
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});
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} else if self.enable_hsi {
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rcc.cfgr.modify(|_, w| unsafe {
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w.ppre().bits(ppre_bits)
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.hpre().bits(hpre_bits)
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.sw().bits(SysClkSource::HSI as u8)
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});
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} else { // Default to HSI
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rcc.cfgr.modify(|_, w| unsafe {
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w.ppre().bits(ppre_bits)
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.hpre().bits(hpre_bits)
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.sw().bits(SysClkSource::HSI as u8)
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});
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}
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}
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Clocks {
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hclk: Hertz(hclk),
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pclk: Hertz(pclk),
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