Fixed a number of deprecation warnings and lints

Signed-off-by: Daniel Egger <daniel@eggers-club.de>

CHANGELOG.md

@@ -9,6 +9,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ### Changed
 
+- Fixed a few deprecation warning and lints
 - Enabled commented out and now available GPIOE support for 07x and 09x families
 - Extract register block address only once
 

src/gpio.rs

@@ -66,7 +66,7 @@ use embedded_hal::digital::{toggleable, InputPin, OutputPin, StatefulOutputPin};
 /// Fully erased pin
 pub struct Pin<MODE> {
     i: u8,
-    port: *const GpioRegExt,
+    port: *const dyn GpioRegExt,
     _mode: PhantomData<MODE>,
 }
 
@@ -476,7 +476,7 @@ macro_rules! gpio {
                     pub fn downgrade(self) -> Pin<Output<MODE>> {
                         Pin {
                             i: $i,
-                            port: $GPIOX::ptr() as *const GpioRegExt,
+                            port: $GPIOX::ptr() as *const dyn GpioRegExt,
                             _mode: self._mode,
                         }
                     }
@@ -522,7 +522,7 @@ macro_rules! gpio {
                     pub fn downgrade(self) -> Pin<Input<MODE>> {
                         Pin {
                             i: $i,
-                            port: $GPIOX::ptr() as *const GpioRegExt,
+                            port: $GPIOX::ptr() as *const dyn GpioRegExt,
                             _mode: self._mode,
                         }
                     }

src/rcc.rs

@@ -37,10 +37,7 @@ pub struct Rcc {
     pub(crate) regs: RCC,
 }
 
-#[cfg(any(
-    feature = "stm32f030",
-    feature = "stm32f070",
-))]
+#[cfg(any(feature = "stm32f030", feature = "stm32f070",))]
 mod inner {
     use crate::stm32::{rcc::cfgr::SWW, RCC};
 
@@ -177,7 +174,7 @@ mod inner {
 
         // Set PLL source and multiplier
         rcc.cfgr
-            .modify(|_, w| unsafe { w.pllsrc().bits(pllsrc_bit).pllmul().bits(pllmul_bits) });
+            .modify(|_, w| w.pllsrc().bits(pllsrc_bit).pllmul().bits(pllmul_bits));
 
         rcc.cr.write(|w| w.pllon().set_bit());
         while rcc.cr.read().pllrdy().bit_is_clear() {}
@@ -313,12 +310,12 @@ impl CFGR {
                 0 => unreachable!(),
                 1 => 0b0111,
                 2 => 0b1000,
-                3...5 => 0b1001,
-                6...11 => 0b1010,
-                12...39 => 0b1011,
-                40...95 => 0b1100,
-                96...191 => 0b1101,
-                192...383 => 0b1110,
+                3..=5 => 0b1001,
+                6..=11 => 0b1010,
+                12..=39 => 0b1011,
+                40..=95 => 0b1100,
+                96..=191 => 0b1101,
+                192..=383 => 0b1110,
                 _ => 0b1111,
             })
             .unwrap_or(0b0111);
@@ -331,8 +328,8 @@ impl CFGR {
                 0 => unreachable!(),
                 1 => 0b011,
                 2 => 0b100,
-                3...5 => 0b101,
-                6...11 => 0b110,
+                3..=5 => 0b101,
+                6..=11 => 0b110,
                 _ => 0b111,
             })
             .unwrap_or(0b011);

src/spi.rs

@@ -281,13 +281,13 @@ where
 
         let br = match clocks.pclk().0 / speed.into().0 {
             0 => unreachable!(),
-            1...2 => 0b000,
-            3...5 => 0b001,
-            6...11 => 0b010,
-            12...23 => 0b011,
-            24...47 => 0b100,
-            48...95 => 0b101,
-            96...191 => 0b110,
+            1..=2 => 0b000,
+            3..=5 => 0b001,
+            6..=11 => 0b010,
+            12..=23 => 0b011,
+            24..=47 => 0b100,
+            48..=95 => 0b101,
+            96..=191 => 0b110,
             _ => 0b111,
         };
 

src/timers.rs

@@ -188,7 +188,7 @@ macro_rules! timers {
                     let ticks = self.clocks.pclk().0 / frequency;
 
                     let psc = cast::u16((ticks - 1) / (1 << 16)).unwrap();
-                    self.tim.psc.write(|w| unsafe { w.psc().bits(psc) });
+                    self.tim.psc.write(|w| w.psc().bits(psc));
 
                     let arr = cast::u16(ticks / cast::u32(psc + 1)).unwrap();
                     self.tim.arr.write(|w| unsafe { w.bits(cast::u32(arr)) });