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Added interupt enabling/disabling support to USART ports

Signed-off-by: Daniel Egger <daniel@eggers-club.de>
trying.tmp
Daniel Egger 4 years ago
parent
commit
4c81088ce5
  1. 1
      CHANGELOG.md
  2. 55
      src/serial.rs

1
CHANGELOG.md

@ -10,6 +10,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
### Added
- Added ADC helper functions to read more intuitive values (#22) - @HarkonenBade
- Added interrupt enabling/disabling support to USART ports
### Changed

55
src/serial.rs

@ -36,13 +36,6 @@ use embedded_hal::prelude::*;
#[allow(unused)]
use crate::{gpio::*, rcc::Clocks, time::Bps};
/// Interrupt event
pub enum Event {
/// New data has been received
Rxne,
/// New data can be sent
Txe,
}
/// Serial error
#[derive(Debug)]
@ -59,6 +52,16 @@ pub enum Error {
_Extensible,
}
/// Interrupt event
pub enum Event {
/// New data has been received
Rxne,
/// New data can be sent
Txe,
/// Idle line state detected
Idle,
}
pub trait TxPin<USART> {}
pub trait RxPin<USART> {}
@ -178,22 +181,52 @@ macro_rules! usart {
// NOTE(unsafe) This executes only during initialisation
let rcc = unsafe { &(*crate::stm32::RCC::ptr()) };
/* Enable clock for USART */
// Enable clock for USART
rcc.$apbenr.modify(|_, w| w.$usartXen().set_bit());
// Calculate correct baudrate divisor on the fly
let brr = clocks.pclk().0 / baud_rate.0;
usart.brr.write(|w| unsafe { w.bits(brr) });
/* Reset other registers to disable advanced USART features */
// Reset other registers to disable advanced USART features
usart.cr2.reset();
usart.cr3.reset();
/* Enable transmission and receiving */
usart.cr1.modify(|_, w| unsafe { w.bits(0xD) });
// Enable transmission and receiving
usart.cr1.modify(|_, w| w.te().set_bit().re().set_bit().ue().set_bit());
Serial { usart, pins }
}
/// Starts listening for an interrupt event
pub fn listen(&mut self, event: Event) {
match event {
Event::Rxne => {
self.usart.cr1.modify(|_, w| w.rxneie().set_bit())
},
Event::Txe => {
self.usart.cr1.modify(|_, w| w.txeie().set_bit())
},
Event::Idle => {
self.usart.cr1.modify(|_, w| w.idleie().set_bit())
},
}
}
/// Stop listening for an interrupt event
pub fn unlisten(&mut self, event: Event) {
match event {
Event::Rxne => {
self.usart.cr1.modify(|_, w| w.rxneie().clear_bit())
},
Event::Txe => {
self.usart.cr1.modify(|_, w| w.txeie().clear_bit())
},
Event::Idle => {
self.usart.cr1.modify(|_, w| w.idleie().clear_bit())
},
}
}
}
)+
}

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