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stm32f0xx-hal
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Review all device datasheets and fix inconsistencies

trying.tmp
Jesse Braham 4 years ago
parent
81f56fb4a2
commit
63bbfd3068
5 changed files with 60 additions and 40 deletions
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  1. 34
      src/gpio.rs
  2. 30
      src/i2c.rs
  3. 23
      src/serial.rs
  4. 12
      src/spi.rs
  5. 1
      src/timers.rs

34
src/gpio.rs
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@ -561,7 +561,12 @@ gpio!(GPIOB, gpiob, iopben, PB, [
PB15: (pb15, 15, Input<Floating>),
]);
#[cfg(any(feature = "stm32f038", feature = "stm32f042", feature = "stm32f048"))]
#[cfg(any(
feature = "stm32f031",
feature = "stm32f038",
feature = "stm32f042",
feature = "stm32f048",
))]
gpio!(GPIOC, gpioc, iopcen, PC, [
PC13: (pc13, 13, Input<Floating>),
PC14: (pc14, 14, Input<Floating>),
@ -634,7 +639,6 @@ gpio!(GPIOD, gpiod, iopden, PD, [
// TODO: The ST SVD files are missing the entire PE enable register.
// Re-enable as soon as this gets fixed.
// #[cfg(any(
// feature = "stm32f071",
// feature = "stm32f072",
@ -661,7 +665,13 @@ gpio!(GPIOD, gpiod, iopden, PD, [
// PE15: (pe15, 15, Input<Floating>),
// ]);
#[cfg(any(feature = "stm32f030", feature = "stm32f051", feature = "stm32f058"))]
#[cfg(any(
feature = "stm32f030x4",
feature = "stm32f030x6",
feature = "stm32f030x8",
feature = "stm32f051",
feature = "stm32f058",
))]
gpio!(GPIOF, gpiof, iopfen, PF, [
PF0: (pf0, 0, Input<Floating>),
PF1: (pf1, 1, Input<Floating>),
@ -670,34 +680,24 @@ gpio!(GPIOF, gpiof, iopfen, PF, [
PF6: (pf6, 6, Input<Floating>),
PF7: (pf7, 7, Input<Floating>),
]);
#[cfg(feature = "stm32f031")]
#[cfg(any(feature = "stm32f030xc", feature = "stm32f070"))]
gpio!(GPIOF, gpiof, iopfen, PF, [
PF6: (pf6, 6, Input<Floating>),
PF7: (pf7, 7, Input<Floating>),
PF0: (pf0, 0, Input<Floating>),
PF1: (pf1, 1, Input<Floating>),
]);
#[cfg(feature = "stm32f038")]
#[cfg(any(feature = "stm32f031", feature = "stm32f038"))]
gpio!(GPIOF, gpiof, iopfen, PF, [
PF0: (pf0, 0, Input<Floating>),
PF1: (pf1, 1, Input<Floating>),
PF6: (pf6, 6, Input<Floating>),
PF7: (pf7, 7, Input<Floating>),
]);
#[cfg(any(feature = "stm32f042", feature = "stm32f048"))]
gpio!(GPIOF, gpiof, iopfen, PF, [
PF0: (pf0, 0, Input<Floating>),
PF1: (pf1, 1, Input<Floating>),
PF11: (pf11, 11, Input<Floating>),
]);
#[cfg(feature = "stm32f070")]
gpio!(GPIOF, gpiof, iopfen, PF, [
PF0: (pf0, 0, Input<Floating>),
PF1: (pf1, 1, Input<Floating>),
]);
#[cfg(any(
feature = "stm32f071",
feature = "stm32f072",

30
src/i2c.rs
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@ -55,11 +55,14 @@ i2c_pins! {
}
}
#[cfg(any(
feature = "stm32f030x4",
feature = "stm32f030x6",
feature = "stm32f030xc",
feature = "stm32f031",
feature = "stm32f038",
feature = "stm32f042",
feature = "stm32f048",
feature = "stm32f070x6",
feature = "stm32f091",
feature = "stm32f098",
))]
@ -77,11 +80,12 @@ i2c_pins! {
}
}
#[cfg(any(
feature = "stm32f030x4",
feature = "stm32f030x6",
feature = "stm32f031",
feature = "stm32f038",
feature = "stm32f042",
feature = "stm32f048",
feature = "stm32f030x6",
))]
i2c_pins! {
I2C1 => {
@ -96,21 +100,14 @@ i2c_pins! {
sda => [gpiob::PB14<Alternate<AF5>>],
}
}
#[cfg(any(feature = "stm32f042", feature = "stm32f030xc", feature = "stm32f098"))]
i2c_pins! {
I2C1 => {
scl => [gpiof::PF1<Alternate<AF1>>],
sda => [gpiof::PF0<Alternate<AF1>>],
}
}
#[cfg(feature = "stm32f070x6")]
i2c_pins! {
I2C1 => {
scl => [gpioa::PA9<Alternate<AF4>>, gpiof::PF0<Alternate<AF1>>],
sda => [gpioa::PA10<Alternate<AF4>>, gpiof::PF1<Alternate<AF1>>],
}
}
#[cfg(feature = "stm32f091")]
#[cfg(any(
feature = "stm32f030xc",
feature = "stm32f042",
feature = "stm32f048",
feature = "stm32f070x6",
feature = "stm32f091",
feature = "stm32f098",
))]
i2c_pins! {
I2C1 => {
scl => [gpiof::PF1<Alternate<AF1>>],
@ -182,6 +179,7 @@ i2c! {
}
#[cfg(any(
feature = "stm32f030x8",
feature = "stm32f030xc",
feature = "stm32f051",
feature = "stm32f058",

23
src/serial.rs
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@ -135,7 +135,12 @@ usart_pins! {
rx => [gpioa::PA10<Alternate<AF1>>, gpiob::PB7<Alternate<AF0>>],
}
}
#[cfg(any(feature = "stm32f030x6", feature = "stm32f031", feature = "stm32f038"))]
#[cfg(any(
feature = "stm32f030x4",
feature = "stm32f030x6",
feature = "stm32f031",
feature = "stm32f038",
))]
usart_pins! {
USART1 => {
tx => [gpioa::PA2<Alternate<AF1>>, gpioa::PA14<Alternate<AF1>>],
@ -164,8 +169,8 @@ usart_pins! {
}
}
#[cfg(any(
feature = "stm32f072",
feature = "stm32f071",
feature = "stm32f072",
feature = "stm32f078",
feature = "stm32f091",
feature = "stm32f098",
@ -210,10 +215,9 @@ usart_pins! {
rx => [gpiod::PD9<Alternate<AF0>>],
}
}
// TODO: The ST SVD files are missing the entire PE enable register.
// Re-enable as soon as this gets fixed.
// #[cfg(feature = "stm32f091")]
// #[cfg(any(feature = "stm32f091", feature = "stm32f098"))]
// usart_pins! {
// USART4 => {
// tx => [gpioe::PE8<Alternate<AF1>>],
@ -224,14 +228,21 @@ usart_pins! {
#[cfg(any(feature = "stm32f030xc", feature = "stm32f091", feature = "stm32f098"))]
usart_pins! {
USART5 => {
tx => [gpiob::PB3<Alternate<AF4>>, gpioc::PC12<Alternate<AF2>>],
rx => [gpiob::PB4<Alternate<AF4>>, gpiod::PD2<Alternate<AF2>>],
tx => [gpioc::PC12<Alternate<AF2>>],
rx => [gpiod::PD2<Alternate<AF2>>],
}
USART6 => {
tx => [gpioa::PA4<Alternate<AF5>>, gpioc::PC0<Alternate<AF2>>],
rx => [gpioa::PA5<Alternate<AF5>>, gpioc::PC1<Alternate<AF2>>],
}
}
#[cfg(any(feature = "stm32f030xc", feature = "stm32f091"))]
usart_pins! {
USART5 => {
tx => [gpiob::PB3<Alternate<AF4>>],
rx => [gpiob::PB4<Alternate<AF4>>],
}
}
// TODO: The ST SVD files are missing the entire PE enable register.
// Re-enable as soon as this gets fixed.
#[cfg(any(feature = "stm32f091", feature = "stm32f098"))]

12
src/spi.rs
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@ -49,11 +49,13 @@ use crate::stm32::SPI1;
#[cfg(any(
feature = "stm32f030x8",
feature = "stm32f030xc",
feature = "stm32f042",
feature = "stm32f048",
feature = "stm32f051",
feature = "stm32f058",
feature = "stm32f070xb",
feature = "stm32f071",
feature = "stm32f072",
feature = "stm32f078",
feature = "stm32f091",
feature = "stm32f098",
@ -116,7 +118,12 @@ spi_pins! {
mosi => [gpioa::PA7<Alternate<AF0>>, gpiob::PB5<Alternate<AF0>>],
}
}
#[cfg(any(feature = "stm32f030x6", feature = "stm32f038"))]
#[cfg(any(
feature = "stm32f030x4",
feature = "stm32f030x6",
feature = "stm32f031",
feature = "stm32f038",
))]
spi_pins! {
SPI1 => {
sck => [gpiob::PB13<Alternate<AF0>>],
@ -145,6 +152,7 @@ spi_pins! {
#[cfg(any(
feature = "stm32f030x8",
feature = "stm32f030xc",
feature = "stm32f042",
feature = "stm32f048",
feature = "stm32f051",
feature = "stm32f058",
@ -231,11 +239,13 @@ spi! {
#[cfg(any(
feature = "stm32f030x8",
feature = "stm32f030xc",
feature = "stm32f042",
feature = "stm32f048",
feature = "stm32f051",
feature = "stm32f058",
feature = "stm32f070xb",
feature = "stm32f071",
feature = "stm32f072",
feature = "stm32f078",
feature = "stm32f091",
feature = "stm32f098",

1
src/timers.rs
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@ -259,6 +259,7 @@ timers! {
#[cfg(any(
feature = "stm32f030xc",
feature = "stm32f070xb",
feature = "stm32f071",
feature = "stm32f072",
feature = "stm32f078",
feature = "stm32f091",

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