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Bump stm32f0 version to 0.9 and upgrade code accordingly

Signed-off-by: Daniel Egger <daniel@eggers-club.de>
trying.tmp
Daniel Egger 3 years ago
parent
commit
67e29bfa8b
  1. 2
      Cargo.toml
  2. 40
      src/adc.rs
  3. 10
      src/rcc.rs

2
Cargo.toml

@ -34,7 +34,7 @@ cast = { version = "0.2", default-features = false }
cortex-m = "0.6"
cortex-m-rt = "0.6"
embedded-hal = { version = "0.2", features = ["unproven"] }
stm32f0 = "0.8"
stm32f0 = "0.9"
nb = "0.1"
void = { version = "1.0", default-features = false }
stm32-usbd = { version = "0.5.0", features = ["ram_access_2x16"], optional = true }

40
src/adc.rs

@ -55,8 +55,8 @@ use crate::{
rcc::Rcc,
stm32::{
adc::{
cfgr1::{ALIGNW, RESW},
smpr::SMPW,
cfgr1::{ALIGN_A, RES_A},
smpr::SMP_A,
},
ADC,
},
@ -100,17 +100,17 @@ impl AdcSampleTime {
}
}
impl From<AdcSampleTime> for SMPW {
impl From<AdcSampleTime> for SMP_A {
fn from(val: AdcSampleTime) -> Self {
match val {
AdcSampleTime::T_1 => SMPW::CYCLES1_5,
AdcSampleTime::T_7 => SMPW::CYCLES7_5,
AdcSampleTime::T_13 => SMPW::CYCLES13_5,
AdcSampleTime::T_28 => SMPW::CYCLES28_5,
AdcSampleTime::T_41 => SMPW::CYCLES41_5,
AdcSampleTime::T_55 => SMPW::CYCLES55_5,
AdcSampleTime::T_71 => SMPW::CYCLES71_5,
AdcSampleTime::T_239 => SMPW::CYCLES239_5,
AdcSampleTime::T_1 => SMP_A::CYCLES1_5,
AdcSampleTime::T_7 => SMP_A::CYCLES7_5,
AdcSampleTime::T_13 => SMP_A::CYCLES13_5,
AdcSampleTime::T_28 => SMP_A::CYCLES28_5,
AdcSampleTime::T_41 => SMP_A::CYCLES41_5,
AdcSampleTime::T_55 => SMP_A::CYCLES55_5,
AdcSampleTime::T_71 => SMP_A::CYCLES71_5,
AdcSampleTime::T_239 => SMP_A::CYCLES239_5,
}
}
}
@ -145,12 +145,12 @@ impl AdcAlign {
}
}
impl From<AdcAlign> for ALIGNW {
impl From<AdcAlign> for ALIGN_A {
fn from(val: AdcAlign) -> Self {
match val {
AdcAlign::Left => ALIGNW::LEFT,
AdcAlign::Right => ALIGNW::RIGHT,
AdcAlign::LeftAsRM => ALIGNW::LEFT,
AdcAlign::Left => ALIGN_A::LEFT,
AdcAlign::Right => ALIGN_A::RIGHT,
AdcAlign::LeftAsRM => ALIGN_A::LEFT,
}
}
}
@ -175,13 +175,13 @@ impl AdcPrecision {
}
}
impl From<AdcPrecision> for RESW {
impl From<AdcPrecision> for RES_A {
fn from(val: AdcPrecision) -> Self {
match val {
AdcPrecision::B_12 => RESW::TWELVEBIT,
AdcPrecision::B_10 => RESW::TENBIT,
AdcPrecision::B_8 => RESW::EIGHTBIT,
AdcPrecision::B_6 => RESW::SIXBIT,
AdcPrecision::B_12 => RES_A::TWELVEBIT,
AdcPrecision::B_10 => RES_A::TENBIT,
AdcPrecision::B_8 => RES_A::EIGHTBIT,
AdcPrecision::B_6 => RES_A::SIXBIT,
}
}
}

10
src/rcc.rs

@ -133,7 +133,7 @@ mod inner {
feature = "stm32f098",
))]
mod inner {
use crate::stm32::{rcc::cfgr::SWW, RCC};
use crate::stm32::{rcc::cfgr::SW_A, RCC};
pub(super) const HSI: u32 = 8_000_000; // Hz
pub(super) const HSI48: u32 = 48_000_000; // Hz
@ -207,11 +207,11 @@ mod inner {
.modify(|_, w| unsafe { w.ppre().bits(ppre_bits).hpre().bits(hpre_bits).sw().pll() });
}
pub(super) fn get_sww(c_src: &SysClkSource) -> SWW {
pub(super) fn get_sww(c_src: &SysClkSource) -> SW_A {
match c_src {
SysClkSource::HSI => SWW::HSI,
SysClkSource::HSI48 => SWW::HSI48,
SysClkSource::HSE(_, _) => SWW::HSE,
SysClkSource::HSI => SW_A::HSI,
SysClkSource::HSI48 => SW_A::HSI48,
SysClkSource::HSE(_, _) => SW_A::HSE,
}
}
}

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