Add support for the STM32f091 (#35)
* Add GPIO support for the stm32f091 * Implement RCC, Serial and Timers for stm32f091 * Implement ADC, I2C and SPI for stm32f091 * Add STM32F091 to Travis config, CHANGELOG and README
This commit is contained in:
parent
35abc7a88f
commit
6f13445bfc
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@ -13,6 +13,7 @@ env:
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- MCU=stm32f070x6
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- MCU=stm32f070xb
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- MCU=stm32f072
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- MCU=stm32f091
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matrix:
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allow_failures:
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- rust: nightly
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@ -7,6 +7,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
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## [Unreleased]
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### Added
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- Support for STM32F091 - @jessebraham
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## [v0.11.1] - 2019-01-05
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### Added
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@ -56,6 +56,7 @@ stm32f070 = ["stm32f0/stm32f0x0", "device-selected"]
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stm32f070x6 = ["stm32f070"]
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stm32f070xb = ["stm32f070"]
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stm32f072 = ["stm32f0/stm32f0x2", "device-selected"]
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stm32f091 = ["stm32f0/stm32f0x1", "device-selected"]
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[profile.dev]
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debug = true
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@ -19,6 +19,7 @@ Currently supported configuration are:
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* stm32f070x6
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* stm32f070xb
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* stm32f072
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* stm32f091
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The idea behind this crate is to gloss over the slight differences in the
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various peripherals available on those MCUs so a HAL can be written for all
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@ -219,7 +219,8 @@ adc_pins!(
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#[cfg(any(
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feature = "stm32f030",
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feature = "stm32f070",
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feature = "stm32f072"
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feature = "stm32f072",
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feature = "stm32f091"
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))]
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adc_pins!(
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gpioc::PC0<Analog> => 10_u8,
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@ -364,17 +365,17 @@ impl VRef {
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}
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}
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#[cfg(any(feature = "stm32f042", feature = "stm32f072"))]
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#[cfg(any(feature = "stm32f042", feature = "stm32f072", feature = "stm32f091"))]
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#[derive(Debug, Default)]
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/// Battery reference voltage (ADC Channel 18)
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pub struct VBat;
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#[cfg(any(feature = "stm32f042", feature = "stm32f072"))]
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#[cfg(any(feature = "stm32f042", feature = "stm32f072", feature = "stm32f091"))]
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adc_pins!(
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VBat => 18_u8,
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);
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#[cfg(any(feature = "stm32f042", feature = "stm32f072"))]
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#[cfg(any(feature = "stm32f042", feature = "stm32f072", feature = "stm32f091"))]
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impl VBat {
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/// Init a new VBat
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pub fn new() -> Self {
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16
src/gpio.rs
16
src/gpio.rs
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@ -577,7 +577,8 @@ gpio!(GPIOC, gpioc, iopcen, PC, [
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#[cfg(any(
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feature = "stm32f030",
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feature = "stm32f070",
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feature = "stm32f072"
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feature = "stm32f072",
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feature = "stm32f091",
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))]
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gpio!(GPIOC, gpioc, iopcen, PC, [
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PC0: (pc0, 0, Input<Floating>),
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@ -598,15 +599,12 @@ gpio!(GPIOC, gpioc, iopcen, PC, [
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PC15: (pc15, 15, Input<Floating>),
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]);
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#[cfg(any(
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feature = "stm32f030",
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feature = "stm32f070"
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))]
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#[cfg(any(feature = "stm32f030", feature = "stm32f070"))]
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gpio!(GPIOD, gpiod, iopden, PD, [
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PD2: (pd2, 2, Input<Floating>),
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]);
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#[cfg(feature = "stm32f072")]
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#[cfg(any(feature = "stm32f072", feature = "stm32f091"))]
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gpio!(GPIOD, gpiod, iopden, PD, [
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PD0: (pd0, 0, Input<Floating>),
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PD1: (pd1, 1, Input<Floating>),
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@ -629,7 +627,7 @@ gpio!(GPIOD, gpiod, iopden, PD, [
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// TODO: The ST SVD files are missing the entire PE enable register.
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// Re-enable as soon as this gets fixed.
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// #[cfg(feature = "stm32f072")]
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// #[cfg(any(feature = "stm32f072", feature = "stm32f091"))]
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// gpio!(GPIOE, gpioe, iopeen, PE, [
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// PE0: (pe0, 0, Input<Floating>),
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// PE1: (pe1, 1, Input<Floating>),
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@ -672,7 +670,7 @@ gpio!(GPIOF, gpiof, iopfen, PF, [
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PF1: (pf1, 1, Input<Floating>),
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]);
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#[cfg(feature = "stm32f072")]
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#[cfg(any(feature = "stm32f072", feature = "stm32f091"))]
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gpio!(GPIOF, gpiof, iopfen, PF, [
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PF0: (pf0, 0, Input<Floating>),
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PF1: (pf1, 1, Input<Floating>),
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@ -681,4 +679,4 @@ gpio!(GPIOF, gpiof, iopfen, PF, [
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PF6: (pf6, 6, Input<Floating>),
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PF9: (pf9, 9, Input<Floating>),
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PF10: (pf10, 10, Input<Floating>),
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]);
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]);
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27
src/i2c.rs
27
src/i2c.rs
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@ -48,6 +48,7 @@ i2c_pins! {
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feature = "stm32f030x6",
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feature = "stm32f030xc",
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feature = "stm32f042",
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feature = "stm32f091",
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))]
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i2c_pins! {
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I2C1 => {
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@ -69,7 +70,7 @@ i2c_pins! {
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sda => [gpiob::PB14<Alternate<AF5>>, gpiof::PF0<Alternate<AF1>>],
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}
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}
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#[cfg(any(feature = "stm32f070", feature = "stm32f072"))]
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#[cfg(any(feature = "stm32f070", feature = "stm32f072", feature = "stm32f091"))]
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i2c_pins! {
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I2C1 => {
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scl => [gpiob::PB6<Alternate<AF1>>, gpiob::PB8<Alternate<AF1>>],
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@ -83,6 +84,13 @@ i2c_pins! {
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sda => [gpioa::PA10<Alternate<AF4>>, gpiof::PF1<Alternate<AF1>>],
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}
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}
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#[cfg(feature = "stm32f091")]
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i2c_pins! {
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I2C1 => {
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scl => [gpiof::PF1<Alternate<AF1>>],
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sda => [gpiof::PF0<Alternate<AF1>>],
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}
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}
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#[cfg(any(feature = "stm32f030x8"))]
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i2c_pins! {
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sda => [gpiob::PB11<Alternate<AF1>>],
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}
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}
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#[cfg(any(feature = "stm32f030xc", feature = "stm32f070xb", feature = "stm32f072"))]
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#[cfg(any(
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feature = "stm32f030xc",
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feature = "stm32f070xb",
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feature = "stm32f072",
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feature = "stm32f091",
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))]
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i2c_pins! {
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I2C2 => {
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scl => [gpiob::PB10<Alternate<AF1>>, gpiob::PB13<Alternate<AF5>>],
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sda => [gpiob::PB11<Alternate<AF1>>, gpiob::PB14<Alternate<AF5>>],
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}
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}
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#[cfg(feature = "stm32f091")]
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i2c_pins! {
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I2C2 => {
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scl => [gpioa::PA11<Alternate<AF5>>],
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sda => [gpioa::PA12<Alternate<AF5>>],
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}
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}
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#[derive(Debug)]
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pub enum Error {
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@ -142,7 +162,8 @@ i2c! {
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// XXX: This can't be right
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feature = "stm32f030xc",
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feature = "stm32f070xb",
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feature = "stm32f072"
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feature = "stm32f072",
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feature = "stm32f091",
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))]
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i2c! {
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I2C2: (i2c2, i2c2en, i2c2rst, apb1enr, apb1rstr),
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@ -3,12 +3,15 @@
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pub use stm32f0;
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#[cfg(any(feature = "stm32f042", feature = "stm32f072"))]
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pub use stm32f0::stm32f0x2 as stm32;
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#[cfg(any(feature = "stm32f030", feature = "stm32f070"))]
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pub use stm32f0::stm32f0x0 as stm32;
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#[cfg(feature = "stm32f091")]
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pub use stm32f0::stm32f0x1 as stm32;
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#[cfg(any(feature = "stm32f042", feature = "stm32f072"))]
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pub use stm32f0::stm32f0x2 as stm32;
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pub mod adc;
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pub mod delay;
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pub mod gpio;
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@ -87,7 +87,7 @@ impl CFGR {
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self
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}
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#[cfg(feature = "stm32f042")]
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#[cfg(any(feature = "stm32f042", feature = "stm32f091"))]
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pub fn enable_hsi48(mut self, is_enabled: bool) -> Self {
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self.enable_hsi48 = is_enabled;
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self
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@ -95,7 +95,7 @@ usart_pins! {
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rx => [gpioa::PA3<Alternate<AF1>>, gpioa::PA15<Alternate<AF1>>],
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}
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}
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#[cfg(any(feature = "stm32f070", feature = "stm32f072"))]
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#[cfg(any(feature = "stm32f070", feature = "stm32f072", feature = "stm32f091"))]
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usart_pins! {
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USART1 => {
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tx => [gpioa::PA9<Alternate<AF1>>, gpiob::PB6<Alternate<AF0>>],
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feature = "stm32f042",
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feature = "stm32f070",
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feature = "stm32f072",
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feature = "stm32f091",
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))]
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usart_pins! {
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USART2 => {
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@ -115,7 +116,7 @@ usart_pins! {
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rx => [gpioa::PA3<Alternate<AF1>>, gpioa::PA15<Alternate<AF1>>],
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}
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}
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#[cfg(feature = "stm32f072")]
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#[cfg(any(feature = "stm32f072", feature = "stm32f091"))]
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usart_pins! {
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USART2 => {
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tx => [gpiod::PD5<Alternate<AF0>>],
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@ -125,7 +126,8 @@ usart_pins! {
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#[cfg(any(
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feature = "stm32f030xc",
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feature = "stm32f070xb",
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feature = "stm32f072"
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feature = "stm32f072",
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feature = "stm32f091",
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))]
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usart_pins! {
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USART3 => {
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@ -138,14 +140,23 @@ usart_pins! {
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rx => [gpioa::PA1<Alternate<AF4>>, gpioc::PC11<Alternate<AF0>>],
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}
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}
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#[cfg(feature = "stm32f072")]
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#[cfg(any(feature = "stm32f072", feature = "stm32f091"))]
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usart_pins! {
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USART3 => {
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tx => [gpiod::PD8<Alternate<AF0>>],
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rx => [gpiod::PD9<Alternate<AF0>>],
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}
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}
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#[cfg(feature = "stm32f030xc")]
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// TODO: The ST SVD files are missing the entire PE enable register.
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// Re-enable as soon as this gets fixed.
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// #[cfg(feature = "stm32f091")]
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// usart_pins! {
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// USART4 => {
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// tx => [gpioe::PE8<Alternate<AF1>>],
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// rx => [gpioe::PE9<Alternate<AF1>>],
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// }
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// }
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#[cfg(any(feature = "stm32f030xc", feature = "stm32f091"))]
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usart_pins! {
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USART5 => {
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tx => [gpiob::PB3<Alternate<AF4>>, gpioc::PC12<Alternate<AF2>>],
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@ -156,6 +167,19 @@ usart_pins! {
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rx => [gpioa::PA5<Alternate<AF5>>, gpioc::PC1<Alternate<AF2>>],
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}
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}
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// TODO: The ST SVD files are missing the entire PE enable register.
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// Re-enable as soon as this gets fixed.
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#[cfg(feature = "stm32f091")]
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usart_pins! {
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// USART5 => {
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// tx => [gpioe::PE10<Alternate<AF1>>],
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// rx => [gpioe::PE11<Alternate<AF1>>],
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// }
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USART6 => {
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tx => [gpiof::PF9<Alternate<AF1>>],
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rx => [gpiof::PF10<Alternate<AF1>>],
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}
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}
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/// Serial abstraction
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#[allow(unused)]
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@ -260,6 +284,7 @@ usart! {
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feature = "stm32f042",
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feature = "stm32f070",
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feature = "stm32f072",
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feature = "stm32f091",
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))]
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usart! {
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USART2: (usart2, usart2en, apb1enr),
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@ -268,12 +293,13 @@ usart! {
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feature = "stm32f030xc",
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feature = "stm32f070xb",
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feature = "stm32f072",
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feature = "stm32f091",
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))]
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usart! {
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USART3: (usart3, usart3en, apb1enr),
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USART4: (usart4, usart4en, apb1enr),
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}
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#[cfg(feature = "stm32f030xc")]
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#[cfg(any(feature = "stm32f030xc", feature = "stm32f091"))]
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usart! {
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USART5: (usart5, usart5en, apb1enr),
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USART6: (usart6, usart6en, apb2enr),
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12
src/spi.rs
12
src/spi.rs
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@ -15,6 +15,7 @@ use crate::stm32::SPI1;
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feature = "stm32f030xc",
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feature = "stm32f070xb",
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feature = "stm32f072",
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feature = "stm32f091",
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))]
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use crate::stm32::SPI2;
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@ -88,11 +89,10 @@ spi_pins! {
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mosi => [gpiob::PB15<Alternate<AF0>>],
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}
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}
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// TODO: The ST SVD files are missing the entire PE enable register.
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// So those pins do not exist in the register definitions.
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// Re-enable as soon as this gets fixed.
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// #[cfg(feature = "stm32f072")]
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// #[cfg(any(feature = "stm32f072", feature = "stm32f091"))]
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// spi_pins! {
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// SPI1 => {
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// sck => [gpioe::PE13<Alternate<AF1>>],
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@ -100,11 +100,13 @@ spi_pins! {
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// mosi => [gpioe::PE15<Alternate<AF1>>],
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// }
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// }
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#[cfg(any(
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feature = "stm32f030x8",
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feature = "stm32f030xc",
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feature = "stm32f070xb",
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feature = "stm32f072",
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feature = "stm32f091",
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))]
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spi_pins! {
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SPI2 => {
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@ -117,6 +119,7 @@ spi_pins! {
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feature = "stm32f030xc",
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feature = "stm32f070xb",
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feature = "stm32f072",
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feature = "stm32f091",
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))]
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spi_pins! {
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SPI2 => {
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@ -125,7 +128,7 @@ spi_pins! {
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mosi => [gpioc::PC3<Alternate<AF1>>],
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}
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}
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#[cfg(feature = "stm32f072")]
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#[cfg(any(feature = "stm32f072", feature = "stm32f091"))]
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spi_pins! {
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SPI2 => {
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sck => [gpiod::PD1<Alternate<AF1>>],
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@ -175,7 +178,8 @@ spi! {
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#[cfg(any(
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feature = "stm32f030x8",
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feature = "stm32f030xc",
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feature = "stm32f070xb"
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feature = "stm32f070xb",
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feature = "stm32f091",
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))]
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spi! {
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SPI2: (spi2, spi2en, spi2rst, apb1enr, apb1rstr),
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|
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@ -225,6 +225,7 @@ timers! {
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feature = "stm32f030xc",
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feature = "stm32f070xb",
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feature = "stm32f072",
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feature = "stm32f091",
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))]
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timers! {
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TIM6: (tim6, tim6en, tim6rst, apb1enr, apb1rstr),
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@ -235,12 +236,13 @@ timers! {
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feature = "stm32f030xc",
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feature = "stm32f070xb",
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feature = "stm32f072",
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feature = "stm32f091",
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))]
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timers! {
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TIM7: (tim7, tim7en, tim7rst, apb1enr, apb1rstr),
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}
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#[cfg(any(feature = "stm32f042", feature = "stm32f072"))]
|
||||
#[cfg(any(feature = "stm32f042", feature = "stm32f072", feature = "stm32f091"))]
|
||||
timers! {
|
||||
TIM2: (tim2, tim2en, tim2rst, apb1enr, apb1rstr),
|
||||
}
|
||||
|
|
Loading…
Reference in New Issue