@ -577,7 +577,8 @@ gpio!(GPIOC, gpioc, iopcen, PC, [
#[ cfg(any(
feature = "stm32f030" ,
feature = "stm32f070" ,
feature = "stm32f072"
feature = "stm32f072" ,
feature = "stm32f091" ,
) ) ]
gpio ! ( GPIOC , gpioc , iopcen , PC , [
PC0 : ( pc0 , 0 , Input < Floating > ) ,
@ -598,15 +599,12 @@ gpio!(GPIOC, gpioc, iopcen, PC, [
PC15 : ( pc15 , 15 , Input < Floating > ) ,
] ) ;
#[ cfg(any(
feature = "stm32f030" ,
feature = "stm32f070"
) ) ]
#[ cfg(any(feature = " stm32f030 " , feature = " stm32f070 " )) ]
gpio ! ( GPIOD , gpiod , iopden , PD , [
PD2 : ( pd2 , 2 , Input < Floating > ) ,
] ) ;
#[ cfg(feature = " stm32f072 " ) ]
#[ cfg(any( feature = " stm32f072 " , feature = " stm32f091 " ) )]
gpio ! ( GPIOD , gpiod , iopden , PD , [
PD0 : ( pd0 , 0 , Input < Floating > ) ,
PD1 : ( pd1 , 1 , Input < Floating > ) ,
@ -629,7 +627,7 @@ gpio!(GPIOD, gpiod, iopden, PD, [
// TODO: The ST SVD files are missing the entire PE enable register.
// Re-enable as soon as this gets fixed.
// #[cfg(feature = "stm32f072")]
// #[cfg(any( feature = "stm32f072", feature = "stm32f091") )]
// gpio!(GPIOE, gpioe, iopeen, PE, [
// PE0: (pe0, 0, Input<Floating>),
// PE1: (pe1, 1, Input<Floating>),
@ -672,7 +670,7 @@ gpio!(GPIOF, gpiof, iopfen, PF, [
PF1 : ( pf1 , 1 , Input < Floating > ) ,
] ) ;
#[ cfg(feature = " stm32f072 " ) ]
#[ cfg(any( feature = " stm32f072 " , feature = " stm32f091 " ) )]
gpio ! ( GPIOF , gpiof , iopfen , PF , [
PF0 : ( pf0 , 0 , Input < Floating > ) ,
PF1 : ( pf1 , 1 , Input < Floating > ) ,
@ -681,4 +679,4 @@ gpio!(GPIOF, gpiof, iopfen, PF, [
PF6 : ( pf6 , 6 , Input < Floating > ) ,
PF9 : ( pf9 , 9 , Input < Floating > ) ,
PF10 : ( pf10 , 10 , Input < Floating > ) ,
] ) ;
] ) ;