Implement RCC and Timers for STM32F070

This commit is contained in:
Jesse Braham 2018-12-18 18:48:39 -08:00
parent c68731fd4d
commit 7ae024ed43
2 changed files with 8 additions and 8 deletions

View File

@ -1,8 +1,8 @@
use core::cmp;
use cast::u32;
#[cfg(any(feature = "stm32f042", feature = "stm32f030"))]
#[cfg(any(feature = "stm32f042", feature = "stm32f030", feature = "stm32f070"))]
use crate::stm32::{FLASH, RCC};
use cast::u32;
use crate::time::Hertz;
@ -12,7 +12,7 @@ pub trait RccExt {
fn constrain(self) -> Rcc;
}
#[cfg(any(feature = "stm32f042", feature = "stm32f030"))]
#[cfg(any(feature = "stm32f042", feature = "stm32f030", feature = "stm32f070"))]
impl RccExt for RCC {
fn constrain(self) -> Rcc {
Rcc {
@ -38,7 +38,7 @@ pub struct CFGR {
sysclk: Option<u32>,
}
#[cfg(any(feature = "stm32f042", feature = "stm32f030"))]
#[cfg(any(feature = "stm32f042", feature = "stm32f030", feature = "stm32f070"))]
impl CFGR {
pub fn hclk<F>(mut self, freq: F) -> Self
where

View File

@ -24,7 +24,7 @@
//! }
//! ```
#[cfg(feature = "stm32f030")]
#[cfg(any(feature = "stm32f030", feature = "stm32f070"))]
use crate::stm32::{RCC, TIM1, TIM14, TIM15, TIM16, TIM17, TIM3, TIM6, TIM7};
#[cfg(feature = "stm32f042")]
use crate::stm32::{RCC, TIM1, TIM14, TIM16, TIM17, TIM2, TIM3};
@ -212,7 +212,7 @@ macro_rules! timers {
}
}
#[cfg(any(feature = "stm32f030", feature = "stm32f042",))]
#[cfg(any(feature = "stm32f030", feature = "stm32f042", feature = "stm32f070"))]
timers! {
TIM1: (tim1, tim1en, tim1rst, apb2enr, apb2rstr),
TIM3: (tim3, tim3en, tim3rst, apb1enr, apb1rstr),
@ -221,13 +221,13 @@ timers! {
TIM17: (tim17, tim17en, tim17rst, apb2enr, apb2rstr),
}
#[cfg(any(feature = "stm32f030x8", feature = "stm32f030xc"))]
#[cfg(any(feature = "stm32f030x8", feature = "stm32f030xc", feature = "stm32f070"))]
timers! {
TIM6: (tim6, tim6en, tim6rst, apb1enr, apb1rstr),
TIM15: (tim15, tim15en, tim15rst, apb2enr, apb2rstr),
}
#[cfg(feature = "stm32f030xc")]
#[cfg(any(feature = "stm32f030xc", feature = "stm32f070"))]
timers! {
TIM7: (tim7, tim7en, tim7rst, apb1enr, apb1rstr),
}