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Added definitions for the stm32f072xx chips (#31)

* Fixed wrong gpio definitions with #[cfg(any(feature = "stm32f030", feature = "stm32f070"))]
* Added definitions for the 072 series
trying.tmp
Yatekii 4 years ago committed by Daniel Egger
parent
commit
7da190e507
  1. 1
      .travis.yml
  2. 5
      CHANGELOG.md
  3. 13
      Cargo.toml
  4. 1
      README.md
  5. 12
      src/adc.rs
  6. 97
      src/gpio.rs
  7. 18
      src/i2c.rs
  8. 2
      src/lib.rs
  9. 30
      src/serial.rs
  10. 32
      src/spi.rs
  11. 9
      src/timers.rs

1
.travis.yml

@ -12,6 +12,7 @@ env:
- MCU=stm32f070
- MCU=stm32f070x6
- MCU=stm32f070xb
- MCU=stm32f072
matrix:
allow_failures:
- rust: nightly

5
CHANGELOG.md

@ -9,6 +9,11 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
### Added
- Added peripheral definitions for the stm32f072xx line - @Yatekii
### Changed
- Fixed broken PC GPIO definitions with feature = "stm32f030" and feature = "stm32f070"
- More robust error handling for I2C
## [v0.11.0] - 2019-01-04

13
Cargo.toml

@ -48,13 +48,14 @@ device-selected = []
rt = ["stm32f0/rt"]
stm32f042 = ["stm32f0/stm32f0x2", "device-selected"]
stm32f030 = ["stm32f0/stm32f0x0", "device-selected"]
stm32f030x4 = ["stm32f030x6", "device-selected"]
stm32f030x6 = ["stm32f030", "device-selected"]
stm32f030x8 = ["stm32f030", "device-selected"]
stm32f030xc = ["stm32f030", "device-selected"]
stm32f030x4 = ["stm32f030x6"]
stm32f030x6 = ["stm32f030"]
stm32f030x8 = ["stm32f030"]
stm32f030xc = ["stm32f030"]
stm32f070 = ["stm32f0/stm32f0x0", "device-selected"]
stm32f070x6 = ["stm32f070", "device-selected"]
stm32f070xb = ["stm32f070", "device-selected"]
stm32f070x6 = ["stm32f070"]
stm32f070xb = ["stm32f070"]
stm32f072 = ["stm32f0/stm32f0x2", "device-selected"]
[profile.dev]
debug = true

1
README.md

@ -18,6 +18,7 @@ Currently supported configuration are:
* stm32f070
* stm32f070x6
* stm32f070xb
* stm32f072
The idea behind this crate is to gloss over the slight differences in the
various peripherals available on those MCUs so a HAL can be written for all

12
src/adc.rs

@ -216,7 +216,11 @@ adc_pins!(
gpiob::PB1<Analog> => 9_u8,
);
#[cfg(any(feature = "stm32f030", feature = "stm32f070",))]
#[cfg(any(
feature = "stm32f030",
feature = "stm32f070",
feature = "stm32f072"
))]
adc_pins!(
gpioc::PC0<Analog> => 10_u8,
gpioc::PC1<Analog> => 11_u8,
@ -360,17 +364,17 @@ impl VRef {
}
}
#[cfg(feature = "stm32f042")]
#[cfg(any(feature = "stm32f042", feature = "stm32f072"))]
#[derive(Debug, Default)]
/// Battery reference voltage (ADC Channel 18)
pub struct VBat;
#[cfg(feature = "stm32f042")]
#[cfg(any(feature = "stm32f042", feature = "stm32f072"))]
adc_pins!(
VBat => 18_u8,
);
#[cfg(feature = "stm32f042")]
#[cfg(any(feature = "stm32f042", feature = "stm32f072"))]
impl VBat {
/// Init a new VBat
pub fn new() -> Self {

97
src/gpio.rs

@ -574,31 +574,81 @@ gpio!(GPIOC, gpioc, iopcen, PC, [
PC15: (pc15, 15, Input<Floating>),
]);
#[cfg(any(feature = "stm32f030", feature = "stm32f070"))]
#[cfg(any(
feature = "stm32f030",
feature = "stm32f070",
feature = "stm32f072"
))]
gpio!(GPIOC, gpioc, iopcen, PC, [
PC0: (pb0, 0, Input<Floating>),
PC1: (pb1, 1, Input<Floating>),
PC2: (pb2, 2, Input<Floating>),
PC3: (pb3, 3, Input<Floating>),
PC4: (pb4, 4, Input<Floating>),
PC5: (pb5, 5, Input<Floating>),
PC6: (pb6, 6, Input<Floating>),
PC7: (pb7, 7, Input<Floating>),
PC8: (pb8, 8, Input<Floating>),
PC9: (pb9, 9, Input<Floating>),
PC10: (pb10, 10, Input<Floating>),
PC11: (pb11, 11, Input<Floating>),
PC12: (pb12, 12, Input<Floating>),
PC13: (pb13, 13, Input<Floating>),
PC14: (pb14, 14, Input<Floating>),
PC15: (pb15, 15, Input<Floating>),
PC0: (pc0, 0, Input<Floating>),
PC1: (pc1, 1, Input<Floating>),
PC2: (pc2, 2, Input<Floating>),
PC3: (pc3, 3, Input<Floating>),
PC4: (pc4, 4, Input<Floating>),
PC5: (pc5, 5, Input<Floating>),
PC6: (pc6, 6, Input<Floating>),
PC7: (pc7, 7, Input<Floating>),
PC8: (pc8, 8, Input<Floating>),
PC9: (pc9, 9, Input<Floating>),
PC10: (pc10, 10, Input<Floating>),
PC11: (pc11, 11, Input<Floating>),
PC12: (pc12, 12, Input<Floating>),
PC13: (pc13, 13, Input<Floating>),
PC14: (pc14, 14, Input<Floating>),
PC15: (pc15, 15, Input<Floating>),
]);
#[cfg(any(
feature = "stm32f030",
feature = "stm32f070"
))]
gpio!(GPIOD, gpiod, iopden, PD, [
PD2: (pd2, 2, Input<Floating>),
]);
#[cfg(any(feature = "stm32f030", feature = "stm32f070"))]
#[cfg(feature = "stm32f072")]
gpio!(GPIOD, gpiod, iopden, PD, [
PD0: (pd0, 0, Input<Floating>),
PD1: (pd1, 1, Input<Floating>),
PD2: (pd2, 2, Input<Floating>),
PD3: (pd3, 3, Input<Floating>),
PD4: (pd4, 4, Input<Floating>),
PD5: (pd5, 5, Input<Floating>),
PD6: (pd6, 6, Input<Floating>),
PD7: (pd7, 7, Input<Floating>),
PD8: (pd8, 8, Input<Floating>),
PD9: (pd9, 9, Input<Floating>),
PD10: (pd10, 10, Input<Floating>),
PD11: (pd11, 11, Input<Floating>),
PD12: (pd12, 12, Input<Floating>),
PD13: (pd13, 13, Input<Floating>),
PD14: (pd14, 14, Input<Floating>),
PD15: (pd15, 15, Input<Floating>),
]);
// TODO: The ST SVD files are missing the entire PE enable register.
// Re-enable as soon as this gets fixed.
// #[cfg(feature = "stm32f072")]
// gpio!(GPIOE, gpioe, iopeen, PE, [
// PE0: (pe0, 0, Input<Floating>),
// PE1: (pe1, 1, Input<Floating>),
// PE2: (pe2, 2, Input<Floating>),
// PE3: (pe3, 3, Input<Floating>),
// PE4: (pe4, 4, Input<Floating>),
// PE5: (pe5, 5, Input<Floating>),
// PE6: (pe6, 6, Input<Floating>),
// PE7: (pe7, 7, Input<Floating>),
// PE8: (pe8, 8, Input<Floating>),
// PE9: (pe9, 9, Input<Floating>),
// PE10: (pe10, 10, Input<Floating>),
// PE11: (pe11, 11, Input<Floating>),
// PE12: (pe12, 12, Input<Floating>),
// PE13: (pe13, 13, Input<Floating>),
// PE14: (pe14, 14, Input<Floating>),
// PE15: (pe15, 15, Input<Floating>),
// ]);
#[cfg(feature = "stm32f042")]
gpio!(GPIOF, gpiof, iopfen, PF, [
PF0: (pf0, 0, Input<Floating>),
@ -621,3 +671,14 @@ gpio!(GPIOF, gpiof, iopfen, PF, [
PF0: (pf0, 0, Input<Floating>),
PF1: (pf1, 1, Input<Floating>),
]);
#[cfg(feature = "stm32f072")]
gpio!(GPIOF, gpiof, iopfen, PF, [
PF0: (pf0, 0, Input<Floating>),
PF1: (pf1, 1, Input<Floating>),
PF2: (pf2, 2, Input<Floating>),
PF3: (pf3, 3, Input<Floating>),
PF6: (pf6, 6, Input<Floating>),
PF9: (pf9, 9, Input<Floating>),
PF10: (pf10, 10, Input<Floating>),
]);

18
src/i2c.rs

@ -69,7 +69,7 @@ i2c_pins! {
sda => [gpiob::PB14<Alternate<AF5>>, gpiof::PF0<Alternate<AF1>>],
}
}
#[cfg(feature = "stm32f070")]
#[cfg(any(feature = "stm32f070", feature = "stm32f072"))]
i2c_pins! {
I2C1 => {
scl => [gpiob::PB6<Alternate<AF1>>, gpiob::PB8<Alternate<AF1>>],
@ -83,22 +83,19 @@ i2c_pins! {
sda => [gpioa::PA10<Alternate<AF4>>, gpiof::PF1<Alternate<AF1>>],
}
}
#[cfg(any(
feature = "stm32f030x8",
feature = "stm32f030xc",
feature = "stm32f070xb"
))]
#[cfg(any(feature = "stm32f030x8"))]
i2c_pins! {
I2C2 => {
scl => [gpiob::PB10<Alternate<AF1>>],
sda => [gpiob::PB11<Alternate<AF1>>],
}
}
#[cfg(any(feature = "stm32f030xc", feature = "stm32f070xb"))]
#[cfg(any(feature = "stm32f030xc", feature = "stm32f070xb", feature = "stm32f072"))]
i2c_pins! {
I2C2 => {
scl => [gpiob::PB13<Alternate<AF5>>],
sda => [gpiob::PB14<Alternate<AF5>>],
scl => [gpiob::PB10<Alternate<AF1>>, gpiob::PB13<Alternate<AF5>>],
sda => [gpiob::PB11<Alternate<AF1>>, gpiob::PB14<Alternate<AF5>>],
}
}
@ -144,7 +141,8 @@ i2c! {
feature = "stm32f030xc",
// XXX: This can't be right
feature = "stm32f030xc",
feature = "stm32f070xb"
feature = "stm32f070xb",
feature = "stm32f072"
))]
i2c! {
I2C2: (i2c2, i2c2en, i2c2rst, apb1enr, apb1rstr),

2
src/lib.rs

@ -3,7 +3,7 @@
pub use stm32f0;
#[cfg(feature = "stm32f042")]
#[cfg(any(feature = "stm32f042", feature = "stm32f072"))]
pub use stm32f0::stm32f0x2 as stm32;
#[cfg(any(feature = "stm32f030", feature = "stm32f070"))]

30
src/serial.rs

@ -95,7 +95,7 @@ usart_pins! {
rx => [gpioa::PA3<Alternate<AF1>>, gpioa::PA15<Alternate<AF1>>],
}
}
#[cfg(feature = "stm32f070")]
#[cfg(any(feature = "stm32f070", feature = "stm32f072"))]
usart_pins! {
USART1 => {
tx => [gpioa::PA9<Alternate<AF1>>, gpiob::PB6<Alternate<AF0>>],
@ -107,6 +107,7 @@ usart_pins! {
feature = "stm32f030xc",
feature = "stm32f042",
feature = "stm32f070",
feature = "stm32f072",
))]
usart_pins! {
USART2 => {
@ -114,7 +115,18 @@ usart_pins! {
rx => [gpioa::PA3<Alternate<AF1>>, gpioa::PA15<Alternate<AF1>>],
}
}
#[cfg(any(feature = "stm32f030xc", feature = "stm32f070xb"))]
#[cfg(feature = "stm32f072")]
usart_pins! {
USART2 => {
tx => [gpiod::PD5<Alternate<AF0>>],
rx => [gpiod::PD6<Alternate<AF0>>],
}
}
#[cfg(any(
feature = "stm32f030xc",
feature = "stm32f070xb",
feature = "stm32f072"
))]
usart_pins! {
USART3 => {
// According to the datasheet PB10 is both tx and rx, but in stm32cubemx it's only tx
@ -126,6 +138,13 @@ usart_pins! {
rx => [gpioa::PA1<Alternate<AF4>>, gpioc::PC11<Alternate<AF0>>],
}
}
#[cfg(feature = "stm32f072")]
usart_pins! {
USART3 => {
tx => [gpiod::PD8<Alternate<AF0>>],
rx => [gpiod::PD9<Alternate<AF0>>],
}
}
#[cfg(feature = "stm32f030xc")]
usart_pins! {
USART5 => {
@ -240,11 +259,16 @@ usart! {
feature = "stm32f030xc",
feature = "stm32f042",
feature = "stm32f070",
feature = "stm32f072",
))]
usart! {
USART2: (usart2, usart2en, apb1enr),
}
#[cfg(any(feature = "stm32f030xc", feature = "stm32f070xb"))]
#[cfg(any(
feature = "stm32f030xc",
feature = "stm32f070xb",
feature = "stm32f072",
))]
usart! {
USART3: (usart3, usart3en, apb1enr),
USART4: (usart4, usart4en, apb1enr),

32
src/spi.rs

@ -13,7 +13,8 @@ use crate::stm32::SPI1;
#[cfg(any(
feature = "stm32f030x8",
feature = "stm32f030xc",
feature = "stm32f070xb"
feature = "stm32f070xb",
feature = "stm32f072",
))]
use crate::stm32::SPI2;
@ -87,10 +88,23 @@ spi_pins! {
mosi => [gpiob::PB15<Alternate<AF0>>],
}
}
// TODO: The ST SVD files are missing the entire PE enable register.
// So those pins do not exist in the register definitions.
// Re-enable as soon as this gets fixed.
// #[cfg(feature = "stm32f072")]
// spi_pins! {
// SPI1 => {
// sck => [gpioe::PE13<Alternate<AF1>>],
// miso => [gpioe::PE14<Alternate<AF1>>],
// mosi => [gpioe::PE15<Alternate<AF1>>],
// }
// }
#[cfg(any(
feature = "stm32f030x8",
feature = "stm32f030xc",
feature = "stm32f070xb"
feature = "stm32f070xb",
feature = "stm32f072",
))]
spi_pins! {
SPI2 => {
@ -99,7 +113,11 @@ spi_pins! {
mosi => [gpiob::PB15<Alternate<AF0>>],
}
}
#[cfg(any(feature = "stm32f030xc", feature = "stm32f070xb"))]
#[cfg(any(
feature = "stm32f030xc",
feature = "stm32f070xb",
feature = "stm32f072",
))]
spi_pins! {
SPI2 => {
sck => [gpiob::PB10<Alternate<AF5>>],
@ -107,6 +125,14 @@ spi_pins! {
mosi => [gpioc::PC3<Alternate<AF1>>],
}
}
#[cfg(feature = "stm32f072")]
spi_pins! {
SPI2 => {
sck => [gpiod::PD1<Alternate<AF1>>],
miso => [gpiod::PD3<Alternate<AF1>>],
mosi => [gpiod::PD4<Alternate<AF1>>],
}
}
#[allow(unused)]
macro_rules! spi {

9
src/timers.rs

@ -224,18 +224,23 @@ timers! {
feature = "stm32f030x8",
feature = "stm32f030xc",
feature = "stm32f070xb",
feature = "stm32f072",
))]
timers! {
TIM6: (tim6, tim6en, tim6rst, apb1enr, apb1rstr),
TIM15: (tim15, tim15en, tim15rst, apb2enr, apb2rstr),
}
#[cfg(any(feature = "stm32f030xc", feature = "stm32f070xb"))]
#[cfg(any(
feature = "stm32f030xc",
feature = "stm32f070xb",
feature = "stm32f072",
))]
timers! {
TIM7: (tim7, tim7en, tim7rst, apb1enr, apb1rstr),
}
#[cfg(feature = "stm32f042")]
#[cfg(any(feature = "stm32f042", feature = "stm32f072"))]
timers! {
TIM2: (tim2, tim2en, tim2rst, apb1enr, apb1rstr),
}

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