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@ -559,17 +559,15 @@ impl CFGR {
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feature = "stm32f091", |
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feature = "stm32f098", |
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))] |
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match self.crs { |
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Some(crs) => { |
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self.rcc.apb1enr.modify(|_, w| w.crsen().set_bit()); |
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// Initialize clock recovery
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// Set autotrim enabled.
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crs.cr.modify(|_, w| w.autotrimen().set_bit()); |
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// Enable CR
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crs.cr.modify(|_, w| w.cen().set_bit()); |
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} |
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_ => {} |
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if let Some(crs) = self.crs { |
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self.rcc.apb1enr.modify(|_, w| w.crsen().set_bit()); |
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// Initialize clock recovery
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// Set autotrim enabled.
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crs.cr.modify(|_, w| w.autotrimen().set_bit()); |
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// Enable CR
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crs.cr.modify(|_, w| w.cen().set_bit()); |
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} |
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// use HSI as source
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