Merge pull request #50 from jessebraham/stm32f0x8
Support stm32f0x8 line
This commit is contained in:
Daniel Egger
GitHub
commit
81f56fb4a2
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@ -7,6 +7,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
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## [Unreleased]
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### Added
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- Support for stm32f0x8 line - @jessebraham
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## [v0.12.0] - 2019-01-13
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### Added
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@ -50,19 +50,24 @@ panic-halt = "0.2.0"
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device-selected = []
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rt = ["stm32f0/rt"]
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stm32f030 = ["stm32f0/stm32f0x0", "device-selected"]
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stm32f030x4 = ["stm32f030x6"]
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stm32f030x4 = ["stm32f030"]
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stm32f030x6 = ["stm32f030"]
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stm32f030x8 = ["stm32f030"]
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stm32f030xc = ["stm32f030"]
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stm32f031 = ["stm32f0/stm32f0x1", "device-selected"]
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stm32f038 = ["stm32f0/stm32f0x8", "device-selected"]
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stm32f042 = ["stm32f0/stm32f0x2", "device-selected"]
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stm32f048 = ["stm32f0/stm32f0x8", "device-selected"]
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stm32f051 = ["stm32f0/stm32f0x1", "device-selected"]
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stm32f058 = ["stm32f0/stm32f0x8", "device-selected"]
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stm32f070 = ["stm32f0/stm32f0x0", "device-selected"]
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stm32f070x6 = ["stm32f070"]
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stm32f070xb = ["stm32f070"]
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stm32f071 = ["stm32f0/stm32f0x1", "device-selected"]
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stm32f072 = ["stm32f0/stm32f0x2", "device-selected"]
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stm32f078 = ["stm32f0/stm32f0x8", "device-selected"]
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stm32f091 = ["stm32f0/stm32f0x1", "device-selected"]
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stm32f098 = ["stm32f0/stm32f0x8", "device-selected"]
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[profile.dev]
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debug = true
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@ -7,7 +7,7 @@ stm32f0xx-hal
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[_stm32f0xx-hal_](https://github.com/stm32-rs/stm32f0xx-hal) contains a hardware abstraction on top of the peripheral access API for the STMicro STM32F0xx family of microcontrollers.
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This crate replaces the [stm32f042-hal](https://github.com/therealprof/stm32f042-hal) by a more ubiqitous version suitable for additional families. The idea behind this crate is to gloss over the slight differences in the various peripherals available on those MCUs so a HAL can be written for all chips in that same family without having to cut and paste crates for every single model.
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This crate replaces the [stm32f042-hal](https://github.com/therealprof/stm32f042-hal) by a more ubiquitous version suitable for additional families. The idea behind this crate is to gloss over the slight differences in the various peripherals available on those MCUs so a HAL can be written for all chips in that same family without having to cut and paste crates for every single model.
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This crate relies on Adam Greig's fantastic [stm32f0](https://crates.io/crates/stm32f0) crate to provide appropriate register definitions, and implements a partial set of the [embedded-hal](https://github.com/rust-embedded/embedded-hal) traits. Some of the implementation was shamelessly adapted from the [stm32f103xx-hal](https://github.com/japaric/stm32f103xx-hal) crate by Jorge Aparicio.
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@ -19,12 +19,17 @@ Supported Configurations
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* __stm32f030__ (stm32f030x4, stm32f030x6, stm32f030x8, stm32f030xc)
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* __stm32f031__
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* __stm32f038__
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* __stm32f042__
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* __stm32f048__
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* __stm32f051__
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* __stm32f058__
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* __stm32f070__ (stm32f070x6, stm32f070xb)
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* __stm32f071__
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* __stm32f072__
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* __stm32f078__
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* __stm32f091__
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* __stm32f098__
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Getting Started
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20
src/adc.rs
20
src/adc.rs
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@ -207,10 +207,13 @@ adc_pins!(
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#[cfg(any(
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feature = "stm32f030",
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feature = "stm32f051",
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feature = "stm32f058",
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feature = "stm32f070",
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feature = "stm32f071",
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feature = "stm32f072",
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feature = "stm32f091"
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feature = "stm32f078",
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feature = "stm32f091",
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feature = "stm32f098",
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))]
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adc_pins!(
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gpioc::PC0<Analog> => 10_u8,
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@ -354,11 +357,16 @@ impl VRef {
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#[cfg(any(
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feature = "stm32f031",
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feature = "stm32f038",
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feature = "stm32f042",
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feature = "stm32f048",
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feature = "stm32f051",
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feature = "stm32f058",
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feature = "stm32f071",
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feature = "stm32f072",
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feature = "stm32f078",
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feature = "stm32f091",
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feature = "stm32f098",
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))]
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#[derive(Debug, Default)]
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/// Battery reference voltage (ADC Channel 18)
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@ -366,11 +374,16 @@ pub struct VBat;
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#[cfg(any(
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feature = "stm32f031",
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feature = "stm32f038",
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feature = "stm32f042",
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feature = "stm32f048",
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feature = "stm32f051",
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feature = "stm32f058",
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feature = "stm32f071",
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feature = "stm32f072",
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feature = "stm32f078",
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feature = "stm32f091",
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feature = "stm32f098",
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))]
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adc_pins!(
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VBat => 18_u8,
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@ -378,11 +391,16 @@ adc_pins!(
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#[cfg(any(
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feature = "stm32f031",
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feature = "stm32f038",
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feature = "stm32f042",
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feature = "stm32f048",
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feature = "stm32f051",
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feature = "stm32f058",
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feature = "stm32f071",
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feature = "stm32f072",
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feature = "stm32f078",
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feature = "stm32f091",
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feature = "stm32f098",
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))]
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impl VBat {
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/// Init a new VBat
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62
src/gpio.rs
62
src/gpio.rs
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@ -561,20 +561,22 @@ gpio!(GPIOB, gpiob, iopben, PB, [
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PB15: (pb15, 15, Input<Floating>),
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]);
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#[cfg(feature = "stm32f042")]
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#[cfg(any(feature = "stm32f038", feature = "stm32f042", feature = "stm32f048"))]
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gpio!(GPIOC, gpioc, iopcen, PC, [
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PC13: (pc13, 13, Input<Floating>),
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PC14: (pc14, 14, Input<Floating>),
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PC15: (pc15, 15, Input<Floating>),
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]);
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#[cfg(any(
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feature = "stm32f030",
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feature = "stm32f051",
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feature = "stm32f058",
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feature = "stm32f070",
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feature = "stm32f071",
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feature = "stm32f072",
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feature = "stm32f078",
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feature = "stm32f091",
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feature = "stm32f098",
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))]
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gpio!(GPIOC, gpioc, iopcen, PC, [
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PC0: (pc0, 0, Input<Floating>),
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@ -595,12 +597,22 @@ gpio!(GPIOC, gpioc, iopcen, PC, [
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PC15: (pc15, 15, Input<Floating>),
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]);
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#[cfg(any(feature = "stm32f030", feature = "stm32f051", feature = "stm32f070"))]
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#[cfg(any(
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feature = "stm32f030",
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feature = "stm32f051",
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feature = "stm32f058",
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feature = "stm32f070",
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))]
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gpio!(GPIOD, gpiod, iopden, PD, [
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PD2: (pd2, 2, Input<Floating>),
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]);
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#[cfg(any(feature = "stm32f071", feature = "stm32f072", feature = "stm32f091"))]
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#[cfg(any(
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feature = "stm32f071",
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feature = "stm32f072",
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feature = "stm32f078",
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feature = "stm32f091",
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feature = "stm32f098",
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))]
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gpio!(GPIOD, gpiod, iopden, PD, [
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PD0: (pd0, 0, Input<Floating>),
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PD1: (pd1, 1, Input<Floating>),
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@ -623,7 +635,13 @@ gpio!(GPIOD, gpiod, iopden, PD, [
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// TODO: The ST SVD files are missing the entire PE enable register.
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// Re-enable as soon as this gets fixed.
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// #[cfg(any(feature = "stm32f071", feature = "stm32f072", feature = "stm32f091"))]
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// #[cfg(any(
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// feature = "stm32f071",
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// feature = "stm32f072",
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// feature = "stm32f078",
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// feature = "stm32f091",
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// feature = "stm32f098",
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// ))]
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// gpio!(GPIOE, gpioe, iopeen, PE, [
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// PE0: (pe0, 0, Input<Floating>),
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// PE1: (pe1, 1, Input<Floating>),
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@ -643,14 +661,7 @@ gpio!(GPIOD, gpiod, iopden, PD, [
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// PE15: (pe15, 15, Input<Floating>),
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// ]);
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#[cfg(feature = "stm32f042")]
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gpio!(GPIOF, gpiof, iopfen, PF, [
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PF0: (pf0, 0, Input<Floating>),
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PF1: (pf1, 1, Input<Floating>),
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PF11: (pf11, 11, Input<Floating>),
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]);
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#[cfg(any(feature = "stm32f030", feature = "stm32f051"))]
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#[cfg(any(feature = "stm32f030", feature = "stm32f051", feature = "stm32f058"))]
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gpio!(GPIOF, gpiof, iopfen, PF, [
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PF0: (pf0, 0, Input<Floating>),
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PF1: (pf1, 1, Input<Floating>),
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@ -666,13 +677,34 @@ gpio!(GPIOF, gpiof, iopfen, PF, [
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PF7: (pf7, 7, Input<Floating>),
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]);
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#[cfg(feature = "stm32f038")]
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gpio!(GPIOF, gpiof, iopfen, PF, [
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PF0: (pf0, 0, Input<Floating>),
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PF1: (pf1, 1, Input<Floating>),
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PF6: (pf6, 6, Input<Floating>),
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PF7: (pf7, 7, Input<Floating>),
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]);
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#[cfg(any(feature = "stm32f042", feature = "stm32f048"))]
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gpio!(GPIOF, gpiof, iopfen, PF, [
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PF0: (pf0, 0, Input<Floating>),
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PF1: (pf1, 1, Input<Floating>),
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PF11: (pf11, 11, Input<Floating>),
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]);
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#[cfg(feature = "stm32f070")]
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gpio!(GPIOF, gpiof, iopfen, PF, [
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PF0: (pf0, 0, Input<Floating>),
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PF1: (pf1, 1, Input<Floating>),
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]);
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#[cfg(any(feature = "stm32f071", feature = "stm32f072", feature = "stm32f091"))]
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#[cfg(any(
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feature = "stm32f071",
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feature = "stm32f072",
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feature = "stm32f078",
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feature = "stm32f091",
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feature = "stm32f098",
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))]
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gpio!(GPIOF, gpiof, iopfen, PF, [
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PF0: (pf0, 0, Input<Floating>),
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PF1: (pf1, 1, Input<Floating>),
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39
src/i2c.rs
39
src/i2c.rs
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@ -36,12 +36,17 @@ macro_rules! i2c_pins {
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#[cfg(any(
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feature = "stm32f030",
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feature = "stm32f031",
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feature = "stm32f038",
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feature = "stm32f042",
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feature = "stm32f048",
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feature = "stm32f051",
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feature = "stm32f058",
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feature = "stm32f070",
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feature = "stm32f071",
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feature = "stm32f072",
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feature = "stm32f078",
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feature = "stm32f091",
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feature = "stm32f098",
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))]
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i2c_pins! {
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I2C1 => {
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@ -54,7 +59,9 @@ i2c_pins! {
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feature = "stm32f030xc",
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feature = "stm32f031",
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feature = "stm32f042",
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feature = "stm32f048",
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feature = "stm32f091",
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feature = "stm32f098",
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))]
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i2c_pins! {
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I2C1 => {
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@ -62,25 +69,38 @@ i2c_pins! {
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sda => [gpioa::PA10<Alternate<AF4>>],
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}
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}
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#[cfg(any(feature = "stm32f030", feature = "stm32f042"))]
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#[cfg(any(feature = "stm32f030", feature = "stm32f042", feature = "stm32f048"))]
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i2c_pins! {
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I2C1 => {
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scl => [gpioa::PA11<Alternate<AF5>>],
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sda => [gpioa::PA12<Alternate<AF5>>],
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}
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}
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#[cfg(any(feature = "stm32f031", feature = "stm32f042", feature = "stm32f030x6"))]
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#[cfg(any(
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feature = "stm32f031",
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feature = "stm32f038",
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feature = "stm32f042",
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feature = "stm32f048",
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feature = "stm32f030x6",
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))]
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i2c_pins! {
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I2C1 => {
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scl => [gpiob::PB10<Alternate<AF1>>],
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sda => [gpiob::PB11<Alternate<AF1>>],
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}
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}
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#[cfg(any(feature = "stm32f042", feature = "stm32f030xc"))]
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#[cfg(any(feature = "stm32f030xc", feature = "stm32f042", feature = "stm32f048"))]
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i2c_pins! {
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I2C1 => {
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scl => [gpiob::PB13<Alternate<AF5>>, gpiof::PF1<Alternate<AF1>>],
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sda => [gpiob::PB14<Alternate<AF5>>, gpiof::PF0<Alternate<AF1>>],
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scl => [gpiob::PB13<Alternate<AF5>>],
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sda => [gpiob::PB14<Alternate<AF5>>],
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}
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}
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#[cfg(any(feature = "stm32f042", feature = "stm32f030xc", feature = "stm32f098"))]
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i2c_pins! {
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I2C1 => {
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scl => [gpiof::PF1<Alternate<AF1>>],
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sda => [gpiof::PF0<Alternate<AF1>>],
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}
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}
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#[cfg(feature = "stm32f070x6")]
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@ -98,7 +118,7 @@ i2c_pins! {
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}
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}
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#[cfg(any(feature = "stm32f030x8", feature = "stm32f051"))]
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#[cfg(any(feature = "stm32f030x8", feature = "stm32f051", feature = "stm32f058"))]
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i2c_pins! {
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I2C2 => {
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scl => [gpiob::PB10<Alternate<AF1>>],
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@ -110,7 +130,9 @@ i2c_pins! {
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feature = "stm32f070xb",
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feature = "stm32f071",
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feature = "stm32f072",
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feature = "stm32f078",
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feature = "stm32f091",
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feature = "stm32f098",
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))]
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i2c_pins! {
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I2C2 => {
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@ -118,7 +140,7 @@ i2c_pins! {
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sda => [gpiob::PB11<Alternate<AF1>>, gpiob::PB14<Alternate<AF5>>],
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}
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}
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#[cfg(feature = "stm32f091")]
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#[cfg(any(feature = "stm32f091", feature = "stm32f098"))]
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i2c_pins! {
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I2C2 => {
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scl => [gpioa::PA11<Alternate<AF5>>],
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@ -162,10 +184,13 @@ i2c! {
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#[cfg(any(
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feature = "stm32f030xc",
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feature = "stm32f051",
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feature = "stm32f058",
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feature = "stm32f070xb",
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feature = "stm32f071",
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feature = "stm32f072",
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feature = "stm32f078",
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feature = "stm32f091",
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feature = "stm32f098",
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))]
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i2c! {
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I2C2: (i2c2, i2c2en, i2c2rst, apb1enr, apb1rstr),
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@ -17,6 +17,15 @@ pub use stm32f0::stm32f0x1 as stm32;
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#[cfg(any(feature = "stm32f042", feature = "stm32f072"))]
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pub use stm32f0::stm32f0x2 as stm32;
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#[cfg(any(
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feature = "stm32f038",
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feature = "stm32f048",
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||||
feature = "stm32f058",
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feature = "stm32f078",
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feature = "stm32f098",
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))]
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pub use stm32f0::stm32f0x8 as stm32;
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||||
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#[cfg(feature = "device-selected")]
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||||
pub mod adc;
|
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#[cfg(feature = "device-selected")]
|
||||
|
|
|
|||
|
|
@ -116,28 +116,18 @@ macro_rules! usart_pins {
|
|||
|
||||
#[cfg(any(
|
||||
feature = "stm32f030",
|
||||
feature = "stm32f042",
|
||||
feature = "stm32f051",
|
||||
feature = "stm32f071",
|
||||
))]
|
||||
usart_pins! {
|
||||
USART1 => {
|
||||
tx => [gpioa::PA9<Alternate<AF1>>, gpiob::PB6<Alternate<AF0>>],
|
||||
rx => [gpioa::PA10<Alternate<AF1>>, gpiob::PB6<Alternate<AF0>>],
|
||||
}
|
||||
}
|
||||
#[cfg(any(feature = "stm32f031", feature = "stm32f030x6"))]
|
||||
usart_pins! {
|
||||
USART1 => {
|
||||
tx => [gpioa::PA2<Alternate<AF1>>, gpioa::PA14<Alternate<AF1>>],
|
||||
rx => [gpioa::PA3<Alternate<AF1>>, gpioa::PA15<Alternate<AF1>>],
|
||||
}
|
||||
}
|
||||
#[cfg(any(
|
||||
feature = "stm32f031",
|
||||
feature = "stm32f038",
|
||||
feature = "stm32f042",
|
||||
feature = "stm32f048",
|
||||
feature = "stm32f051",
|
||||
feature = "stm32f058",
|
||||
feature = "stm32f070",
|
||||
feature = "stm32f071",
|
||||
feature = "stm32f072",
|
||||
feature = "stm32f078",
|
||||
feature = "stm32f091",
|
||||
feature = "stm32f098",
|
||||
))]
|
||||
usart_pins! {
|
||||
USART1 => {
|
||||
|
|
@ -145,16 +135,27 @@ usart_pins! {
|
|||
rx => [gpioa::PA10<Alternate<AF1>>, gpiob::PB7<Alternate<AF0>>],
|
||||
}
|
||||
}
|
||||
#[cfg(any(feature = "stm32f030x6", feature = "stm32f031", feature = "stm32f038"))]
|
||||
usart_pins! {
|
||||
USART1 => {
|
||||
tx => [gpioa::PA2<Alternate<AF1>>, gpioa::PA14<Alternate<AF1>>],
|
||||
rx => [gpioa::PA3<Alternate<AF1>>, gpioa::PA15<Alternate<AF1>>],
|
||||
}
|
||||
}
|
||||
|
||||
#[cfg(any(
|
||||
feature = "stm32f030x8",
|
||||
feature = "stm32f030xc",
|
||||
feature = "stm32f042",
|
||||
feature = "stm32f048",
|
||||
feature = "stm32f051",
|
||||
feature = "stm32f058",
|
||||
feature = "stm32f070",
|
||||
feature = "stm32f071",
|
||||
feature = "stm32f072",
|
||||
feature = "stm32f078",
|
||||
feature = "stm32f091",
|
||||
feature = "stm32f098",
|
||||
))]
|
||||
usart_pins! {
|
||||
USART2 => {
|
||||
|
|
@ -162,7 +163,13 @@ usart_pins! {
|
|||
rx => [gpioa::PA3<Alternate<AF1>>, gpioa::PA15<Alternate<AF1>>],
|
||||
}
|
||||
}
|
||||
#[cfg(any(feature = "stm32f072", feature = "stm32f071", feature = "stm32f091"))]
|
||||
#[cfg(any(
|
||||
feature = "stm32f072",
|
||||
feature = "stm32f071",
|
||||
feature = "stm32f078",
|
||||
feature = "stm32f091",
|
||||
feature = "stm32f098",
|
||||
))]
|
||||
usart_pins! {
|
||||
USART2 => {
|
||||
tx => [gpiod::PD5<Alternate<AF0>>],
|
||||
|
|
@ -175,7 +182,9 @@ usart_pins! {
|
|||
feature = "stm32f070xb",
|
||||
feature = "stm32f071",
|
||||
feature = "stm32f072",
|
||||
feature = "stm32f078",
|
||||
feature = "stm32f091",
|
||||
feature = "stm32f098",
|
||||
))]
|
||||
usart_pins! {
|
||||
USART3 => {
|
||||
|
|
@ -188,7 +197,13 @@ usart_pins! {
|
|||
rx => [gpioa::PA1<Alternate<AF4>>, gpioc::PC11<Alternate<AF0>>],
|
||||
}
|
||||
}
|
||||
#[cfg(any(feature = "stm32f071", feature = "stm32f072", feature = "stm32f091"))]
|
||||
#[cfg(any(
|
||||
feature = "stm32f071",
|
||||
feature = "stm32f072",
|
||||
feature = "stm32f078",
|
||||
feature = "stm32f091",
|
||||
feature = "stm32f098",
|
||||
))]
|
||||
usart_pins! {
|
||||
USART3 => {
|
||||
tx => [gpiod::PD8<Alternate<AF0>>],
|
||||
|
|
@ -206,7 +221,7 @@ usart_pins! {
|
|||
// }
|
||||
// }
|
||||
|
||||
#[cfg(any(feature = "stm32f030xc", feature = "stm32f091"))]
|
||||
#[cfg(any(feature = "stm32f030xc", feature = "stm32f091", feature = "stm32f098"))]
|
||||
usart_pins! {
|
||||
USART5 => {
|
||||
tx => [gpiob::PB3<Alternate<AF4>>, gpioc::PC12<Alternate<AF2>>],
|
||||
|
|
@ -219,7 +234,7 @@ usart_pins! {
|
|||
}
|
||||
// TODO: The ST SVD files are missing the entire PE enable register.
|
||||
// Re-enable as soon as this gets fixed.
|
||||
#[cfg(feature = "stm32f091")]
|
||||
#[cfg(any(feature = "stm32f091", feature = "stm32f098"))]
|
||||
usart_pins! {
|
||||
// USART5 => {
|
||||
// tx => [gpioe::PE10<Alternate<AF1>>],
|
||||
|
|
@ -365,11 +380,15 @@ usart! {
|
|||
feature = "stm32f030x8",
|
||||
feature = "stm32f030xc",
|
||||
feature = "stm32f042",
|
||||
feature = "stm32f048",
|
||||
feature = "stm32f051",
|
||||
feature = "stm32f058",
|
||||
feature = "stm32f070",
|
||||
feature = "stm32f071",
|
||||
feature = "stm32f072",
|
||||
feature = "stm32f078",
|
||||
feature = "stm32f091",
|
||||
feature = "stm32f098",
|
||||
))]
|
||||
usart! {
|
||||
USART2: (usart2, usart2tx, usart2rx,usart2en, apb1enr),
|
||||
|
|
@ -379,13 +398,15 @@ usart! {
|
|||
feature = "stm32f070xb",
|
||||
feature = "stm32f071",
|
||||
feature = "stm32f072",
|
||||
feature = "stm32f078",
|
||||
feature = "stm32f091",
|
||||
feature = "stm32f098",
|
||||
))]
|
||||
usart! {
|
||||
USART3: (usart3, usart3tx, usart3rx,usart3en, apb1enr),
|
||||
USART4: (usart4, usart4tx, usart4rx,usart4en, apb1enr),
|
||||
}
|
||||
#[cfg(any(feature = "stm32f030xc", feature = "stm32f091"))]
|
||||
#[cfg(any(feature = "stm32f030xc", feature = "stm32f091", feature = "stm32f098"))]
|
||||
usart! {
|
||||
USART5: (usart5, usart5tx, usart5rx,usart5en, apb1enr),
|
||||
USART6: (usart6, usart6tx, usart6rx,usart6en, apb2enr),
|
||||
|
|
|
|||
32
src/spi.rs
32
src/spi.rs
|
|
@ -49,10 +49,14 @@ use crate::stm32::SPI1;
|
|||
#[cfg(any(
|
||||
feature = "stm32f030x8",
|
||||
feature = "stm32f030xc",
|
||||
feature = "stm32f048",
|
||||
feature = "stm32f051",
|
||||
feature = "stm32f058",
|
||||
feature = "stm32f070xb",
|
||||
feature = "stm32f071",
|
||||
feature = "stm32f078",
|
||||
feature = "stm32f091",
|
||||
feature = "stm32f098",
|
||||
))]
|
||||
use crate::stm32::SPI2;
|
||||
|
||||
|
|
@ -112,7 +116,7 @@ spi_pins! {
|
|||
mosi => [gpioa::PA7<Alternate<AF0>>, gpiob::PB5<Alternate<AF0>>],
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "stm32f030x6")]
|
||||
#[cfg(any(feature = "stm32f030x6", feature = "stm32f038"))]
|
||||
spi_pins! {
|
||||
SPI1 => {
|
||||
sck => [gpiob::PB13<Alternate<AF0>>],
|
||||
|
|
@ -123,7 +127,13 @@ spi_pins! {
|
|||
// TODO: The ST SVD files are missing the entire PE enable register.
|
||||
// So those pins do not exist in the register definitions.
|
||||
// Re-enable as soon as this gets fixed.
|
||||
// #[cfg(any(feature = "stm32f071", feature = "stm32f072", feature = "stm32f091"))]
|
||||
// #[cfg(any(
|
||||
// feature = "stm32f071",
|
||||
// feature = "stm32f072",
|
||||
// feature = "stm32f078",
|
||||
// feature = "stm32f091",
|
||||
// feature = "stm32f098",
|
||||
// ))]
|
||||
// spi_pins! {
|
||||
// SPI1 => {
|
||||
// sck => [gpioe::PE13<Alternate<AF1>>],
|
||||
|
|
@ -135,11 +145,15 @@ spi_pins! {
|
|||
#[cfg(any(
|
||||
feature = "stm32f030x8",
|
||||
feature = "stm32f030xc",
|
||||
feature = "stm32f048",
|
||||
feature = "stm32f051",
|
||||
feature = "stm32f058",
|
||||
feature = "stm32f070xb",
|
||||
feature = "stm32f071",
|
||||
feature = "stm32f072",
|
||||
feature = "stm32f078",
|
||||
feature = "stm32f091",
|
||||
feature = "stm32f098",
|
||||
))]
|
||||
spi_pins! {
|
||||
SPI2 => {
|
||||
|
|
@ -153,7 +167,9 @@ spi_pins! {
|
|||
feature = "stm32f070xb",
|
||||
feature = "stm32f071",
|
||||
feature = "stm32f072",
|
||||
feature = "stm32f078",
|
||||
feature = "stm32f091",
|
||||
feature = "stm32f098",
|
||||
))]
|
||||
spi_pins! {
|
||||
SPI2 => {
|
||||
|
|
@ -162,7 +178,13 @@ spi_pins! {
|
|||
mosi => [gpioc::PC3<Alternate<AF1>>],
|
||||
}
|
||||
}
|
||||
#[cfg(any(feature = "stm32f071", feature = "stm32f072", feature = "stm32f091"))]
|
||||
#[cfg(any(
|
||||
feature = "stm32f071",
|
||||
feature = "stm32f072",
|
||||
feature = "stm32f078",
|
||||
feature = "stm32f091",
|
||||
feature = "stm32f098",
|
||||
))]
|
||||
spi_pins! {
|
||||
SPI2 => {
|
||||
sck => [gpiod::PD1<Alternate<AF1>>],
|
||||
|
|
@ -209,10 +231,14 @@ spi! {
|
|||
#[cfg(any(
|
||||
feature = "stm32f030x8",
|
||||
feature = "stm32f030xc",
|
||||
feature = "stm32f048",
|
||||
feature = "stm32f051",
|
||||
feature = "stm32f058",
|
||||
feature = "stm32f070xb",
|
||||
feature = "stm32f071",
|
||||
feature = "stm32f078",
|
||||
feature = "stm32f091",
|
||||
feature = "stm32f098",
|
||||
))]
|
||||
spi! {
|
||||
SPI2: (spi2, spi2en, spi2rst, apb1enr, apb1rstr),
|
||||
|
|
|
|||
|
|
@ -224,11 +224,16 @@ timers! {
|
|||
|
||||
#[cfg(any(
|
||||
feature = "stm32f031",
|
||||
feature = "stm32f038",
|
||||
feature = "stm32f042",
|
||||
feature = "stm32f048",
|
||||
feature = "stm32f051",
|
||||
feature = "stm32f058",
|
||||
feature = "stm32f071",
|
||||
feature = "stm32f072",
|
||||
feature = "stm32f078",
|
||||
feature = "stm32f091",
|
||||
feature = "stm32f098",
|
||||
))]
|
||||
timers! {
|
||||
TIM2: (tim2, tim2en, tim2rst, apb1enr, apb1rstr),
|
||||
|
|
@ -238,10 +243,13 @@ timers! {
|
|||
feature = "stm32f030x8",
|
||||
feature = "stm32f030xc",
|
||||
feature = "stm32f051",
|
||||
feature = "stm32f058",
|
||||
feature = "stm32f070xb",
|
||||
feature = "stm32f071",
|
||||
feature = "stm32f072",
|
||||
feature = "stm32f078",
|
||||
feature = "stm32f091",
|
||||
feature = "stm32f098",
|
||||
))]
|
||||
timers! {
|
||||
TIM6: (tim6, tim6en, tim6rst, apb1enr, apb1rstr),
|
||||
|
|
@ -252,7 +260,9 @@ timers! {
|
|||
feature = "stm32f030xc",
|
||||
feature = "stm32f070xb",
|
||||
feature = "stm32f072",
|
||||
feature = "stm32f078",
|
||||
feature = "stm32f091",
|
||||
feature = "stm32f098",
|
||||
))]
|
||||
timers! {
|
||||
TIM7: (tim7, tim7en, tim7rst, apb1enr, apb1rstr),
|
||||
|
|
|
|||
Loading…
Reference in New Issue