diff --git a/CHANGELOG.md b/CHANGELOG.md
index 660286c..8be387f 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -7,6 +7,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+### Added
+
+- Support for stm32f0x8 line - @jessebraham
+
 ## [v0.12.0] - 2019-01-13
 
 ### Added
diff --git a/Cargo.toml b/Cargo.toml
index 6786b8f..b52ddad 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -50,19 +50,24 @@ panic-halt = "0.2.0"
 device-selected = []
 rt = ["stm32f0/rt"]
 stm32f030 = ["stm32f0/stm32f0x0", "device-selected"]
-stm32f030x4 = ["stm32f030x6"]
+stm32f030x4 = ["stm32f030"]
 stm32f030x6 = ["stm32f030"]
 stm32f030x8 = ["stm32f030"]
 stm32f030xc = ["stm32f030"]
 stm32f031 = ["stm32f0/stm32f0x1", "device-selected"]
+stm32f038 = ["stm32f0/stm32f0x8", "device-selected"]
 stm32f042 = ["stm32f0/stm32f0x2", "device-selected"]
+stm32f048 = ["stm32f0/stm32f0x8", "device-selected"]
 stm32f051 = ["stm32f0/stm32f0x1", "device-selected"]
+stm32f058 = ["stm32f0/stm32f0x8", "device-selected"]
 stm32f070 = ["stm32f0/stm32f0x0", "device-selected"]
 stm32f070x6 = ["stm32f070"]
 stm32f070xb = ["stm32f070"]
 stm32f071 = ["stm32f0/stm32f0x1", "device-selected"]
 stm32f072 = ["stm32f0/stm32f0x2", "device-selected"]
+stm32f078 = ["stm32f0/stm32f0x8", "device-selected"]
 stm32f091 = ["stm32f0/stm32f0x1", "device-selected"]
+stm32f098 = ["stm32f0/stm32f0x8", "device-selected"]
 
 [profile.dev]
 debug = true
diff --git a/README.md b/README.md
index eb30196..9b66cd8 100644
--- a/README.md
+++ b/README.md
@@ -7,7 +7,7 @@ stm32f0xx-hal
 
 [_stm32f0xx-hal_](https://github.com/stm32-rs/stm32f0xx-hal) contains a hardware abstraction on top of the peripheral access API for the STMicro STM32F0xx family of microcontrollers.
 
-This crate replaces the [stm32f042-hal](https://github.com/therealprof/stm32f042-hal) by a more ubiqitous version suitable for additional families. The idea behind this crate is to gloss over the slight differences in the various peripherals available on those MCUs so a HAL can be written for all chips in that same family without having to cut and paste crates for every single model.
+This crate replaces the [stm32f042-hal](https://github.com/therealprof/stm32f042-hal) by a more ubiquitous version suitable for additional families. The idea behind this crate is to gloss over the slight differences in the various peripherals available on those MCUs so a HAL can be written for all chips in that same family without having to cut and paste crates for every single model.
 
 This crate relies on Adam Greig's fantastic [stm32f0](https://crates.io/crates/stm32f0) crate to provide appropriate register definitions, and implements a partial set of the [embedded-hal](https://github.com/rust-embedded/embedded-hal) traits. Some of the implementation was shamelessly adapted from the [stm32f103xx-hal](https://github.com/japaric/stm32f103xx-hal) crate by Jorge Aparicio.
 
@@ -19,12 +19,17 @@ Supported Configurations
 
 * __stm32f030__ (stm32f030x4, stm32f030x6, stm32f030x8, stm32f030xc)  
 * __stm32f031__  
+* __stm32f038__  
 * __stm32f042__  
+* __stm32f048__  
 * __stm32f051__  
+* __stm32f058__  
 * __stm32f070__ (stm32f070x6, stm32f070xb)  
 * __stm32f071__  
 * __stm32f072__  
+* __stm32f078__  
 * __stm32f091__  
+* __stm32f098__  
 
 
 Getting Started
diff --git a/src/adc.rs b/src/adc.rs
index 63246e7..78f7176 100644
--- a/src/adc.rs
+++ b/src/adc.rs
@@ -207,10 +207,13 @@ adc_pins!(
 #[cfg(any(
     feature = "stm32f030",
     feature = "stm32f051",
+    feature = "stm32f058",
     feature = "stm32f070",
     feature = "stm32f071",
     feature = "stm32f072",
-    feature = "stm32f091"
+    feature = "stm32f078",
+    feature = "stm32f091",
+    feature = "stm32f098",
 ))]
 adc_pins!(
     gpioc::PC0<Analog> => 10_u8,
@@ -354,11 +357,16 @@ impl VRef {
 
 #[cfg(any(
     feature = "stm32f031",
+    feature = "stm32f038",
     feature = "stm32f042",
+    feature = "stm32f048",
     feature = "stm32f051",
+    feature = "stm32f058",
     feature = "stm32f071",
     feature = "stm32f072",
+    feature = "stm32f078",
     feature = "stm32f091",
+    feature = "stm32f098",
 ))]
 #[derive(Debug, Default)]
 /// Battery reference voltage (ADC Channel 18)
@@ -366,11 +374,16 @@ pub struct VBat;
 
 #[cfg(any(
     feature = "stm32f031",
+    feature = "stm32f038",
     feature = "stm32f042",
+    feature = "stm32f048",
     feature = "stm32f051",
+    feature = "stm32f058",
     feature = "stm32f071",
     feature = "stm32f072",
+    feature = "stm32f078",
     feature = "stm32f091",
+    feature = "stm32f098",
 ))]
 adc_pins!(
     VBat  => 18_u8,
@@ -378,11 +391,16 @@ adc_pins!(
 
 #[cfg(any(
     feature = "stm32f031",
+    feature = "stm32f038",
     feature = "stm32f042",
+    feature = "stm32f048",
     feature = "stm32f051",
+    feature = "stm32f058",
     feature = "stm32f071",
     feature = "stm32f072",
+    feature = "stm32f078",
     feature = "stm32f091",
+    feature = "stm32f098",
 ))]
 impl VBat {
     /// Init a new VBat
diff --git a/src/gpio.rs b/src/gpio.rs
index 6d7be1d..1efa46d 100644
--- a/src/gpio.rs
+++ b/src/gpio.rs
@@ -561,20 +561,22 @@ gpio!(GPIOB, gpiob, iopben, PB, [
     PB15: (pb15, 15, Input<Floating>),
 ]);
 
-#[cfg(feature = "stm32f042")]
+#[cfg(any(feature = "stm32f038", feature = "stm32f042", feature = "stm32f048"))]
 gpio!(GPIOC, gpioc, iopcen, PC, [
     PC13: (pc13, 13, Input<Floating>),
     PC14: (pc14, 14, Input<Floating>),
     PC15: (pc15, 15, Input<Floating>),
 ]);
-
 #[cfg(any(
     feature = "stm32f030",
     feature = "stm32f051",
+    feature = "stm32f058",
     feature = "stm32f070",
     feature = "stm32f071",
     feature = "stm32f072",
+    feature = "stm32f078",
     feature = "stm32f091",
+    feature = "stm32f098",
 ))]
 gpio!(GPIOC, gpioc, iopcen, PC, [
     PC0: (pc0, 0, Input<Floating>),
@@ -595,12 +597,22 @@ gpio!(GPIOC, gpioc, iopcen, PC, [
     PC15: (pc15, 15, Input<Floating>),
 ]);
 
-#[cfg(any(feature = "stm32f030", feature = "stm32f051", feature = "stm32f070"))]
+#[cfg(any(
+    feature = "stm32f030",
+    feature = "stm32f051",
+    feature = "stm32f058",
+    feature = "stm32f070",
+))]
 gpio!(GPIOD, gpiod, iopden, PD, [
     PD2: (pd2, 2, Input<Floating>),
 ]);
-
-#[cfg(any(feature = "stm32f071", feature = "stm32f072", feature = "stm32f091"))]
+#[cfg(any(
+    feature = "stm32f071",
+    feature = "stm32f072",
+    feature = "stm32f078",
+    feature = "stm32f091",
+    feature = "stm32f098",
+))]
 gpio!(GPIOD, gpiod, iopden, PD, [
     PD0: (pd0, 0, Input<Floating>),
     PD1: (pd1, 1, Input<Floating>),
@@ -623,7 +635,13 @@ gpio!(GPIOD, gpiod, iopden, PD, [
 // TODO: The ST SVD files are missing the entire PE enable register.
 //       Re-enable as soon as this gets fixed.
 
-// #[cfg(any(feature = "stm32f071", feature = "stm32f072", feature = "stm32f091"))]
+// #[cfg(any(
+//     feature = "stm32f071",
+//     feature = "stm32f072",
+//     feature = "stm32f078",
+//     feature = "stm32f091",
+//     feature = "stm32f098",
+// ))]
 // gpio!(GPIOE, gpioe, iopeen, PE, [
 //     PE0: (pe0, 0, Input<Floating>),
 //     PE1: (pe1, 1, Input<Floating>),
@@ -643,14 +661,7 @@ gpio!(GPIOD, gpiod, iopden, PD, [
 //     PE15: (pe15, 15, Input<Floating>),
 // ]);
 
-#[cfg(feature = "stm32f042")]
-gpio!(GPIOF, gpiof, iopfen, PF, [
-    PF0: (pf0, 0, Input<Floating>),
-    PF1: (pf1, 1, Input<Floating>),
-    PF11: (pf11, 11, Input<Floating>),
-]);
-
-#[cfg(any(feature = "stm32f030", feature = "stm32f051"))]
+#[cfg(any(feature = "stm32f030", feature = "stm32f051", feature = "stm32f058"))]
 gpio!(GPIOF, gpiof, iopfen, PF, [
     PF0: (pf0, 0, Input<Floating>),
     PF1: (pf1, 1, Input<Floating>),
@@ -666,13 +677,34 @@ gpio!(GPIOF, gpiof, iopfen, PF, [
     PF7: (pf7, 7, Input<Floating>),
 ]);
 
+#[cfg(feature = "stm32f038")]
+gpio!(GPIOF, gpiof, iopfen, PF, [
+    PF0: (pf0, 0, Input<Floating>),
+    PF1: (pf1, 1, Input<Floating>),
+    PF6: (pf6, 6, Input<Floating>),
+    PF7: (pf7, 7, Input<Floating>),
+]);
+
+#[cfg(any(feature = "stm32f042", feature = "stm32f048"))]
+gpio!(GPIOF, gpiof, iopfen, PF, [
+    PF0: (pf0, 0, Input<Floating>),
+    PF1: (pf1, 1, Input<Floating>),
+    PF11: (pf11, 11, Input<Floating>),
+]);
+
 #[cfg(feature = "stm32f070")]
 gpio!(GPIOF, gpiof, iopfen, PF, [
     PF0: (pf0, 0, Input<Floating>),
     PF1: (pf1, 1, Input<Floating>),
 ]);
 
-#[cfg(any(feature = "stm32f071", feature = "stm32f072", feature = "stm32f091"))]
+#[cfg(any(
+    feature = "stm32f071",
+    feature = "stm32f072",
+    feature = "stm32f078",
+    feature = "stm32f091",
+    feature = "stm32f098",
+))]
 gpio!(GPIOF, gpiof, iopfen, PF, [
     PF0: (pf0, 0, Input<Floating>),
     PF1: (pf1, 1, Input<Floating>),
diff --git a/src/i2c.rs b/src/i2c.rs
index a56fe97..a8708f5 100644
--- a/src/i2c.rs
+++ b/src/i2c.rs
@@ -36,12 +36,17 @@ macro_rules! i2c_pins {
 #[cfg(any(
     feature = "stm32f030",
     feature = "stm32f031",
+    feature = "stm32f038",
     feature = "stm32f042",
+    feature = "stm32f048",
     feature = "stm32f051",
+    feature = "stm32f058",
     feature = "stm32f070",
     feature = "stm32f071",
     feature = "stm32f072",
+    feature = "stm32f078",
     feature = "stm32f091",
+    feature = "stm32f098",
 ))]
 i2c_pins! {
     I2C1 => {
@@ -54,7 +59,9 @@ i2c_pins! {
     feature = "stm32f030xc",
     feature = "stm32f031",
     feature = "stm32f042",
+    feature = "stm32f048",
     feature = "stm32f091",
+    feature = "stm32f098",
 ))]
 i2c_pins! {
     I2C1 => {
@@ -62,25 +69,38 @@ i2c_pins! {
         sda => [gpioa::PA10<Alternate<AF4>>],
     }
 }
-#[cfg(any(feature = "stm32f030", feature = "stm32f042"))]
+#[cfg(any(feature = "stm32f030", feature = "stm32f042", feature = "stm32f048"))]
 i2c_pins! {
     I2C1 => {
         scl => [gpioa::PA11<Alternate<AF5>>],
         sda => [gpioa::PA12<Alternate<AF5>>],
     }
 }
-#[cfg(any(feature = "stm32f031", feature = "stm32f042", feature = "stm32f030x6"))]
+#[cfg(any(
+    feature = "stm32f031",
+    feature = "stm32f038",
+    feature = "stm32f042",
+    feature = "stm32f048",
+    feature = "stm32f030x6",
+))]
 i2c_pins! {
     I2C1 => {
         scl => [gpiob::PB10<Alternate<AF1>>],
         sda => [gpiob::PB11<Alternate<AF1>>],
     }
 }
-#[cfg(any(feature = "stm32f042", feature = "stm32f030xc"))]
+#[cfg(any(feature = "stm32f030xc", feature = "stm32f042", feature = "stm32f048"))]
+i2c_pins! {
+    I2C1 => {
+        scl => [gpiob::PB13<Alternate<AF5>>],
+        sda => [gpiob::PB14<Alternate<AF5>>],
+    }
+}
+#[cfg(any(feature = "stm32f042", feature = "stm32f030xc", feature = "stm32f098"))]
 i2c_pins! {
     I2C1 => {
-        scl => [gpiob::PB13<Alternate<AF5>>, gpiof::PF1<Alternate<AF1>>],
-        sda => [gpiob::PB14<Alternate<AF5>>, gpiof::PF0<Alternate<AF1>>],
+        scl => [gpiof::PF1<Alternate<AF1>>],
+        sda => [gpiof::PF0<Alternate<AF1>>],
     }
 }
 #[cfg(feature = "stm32f070x6")]
@@ -98,7 +118,7 @@ i2c_pins! {
     }
 }
 
-#[cfg(any(feature = "stm32f030x8", feature = "stm32f051"))]
+#[cfg(any(feature = "stm32f030x8", feature = "stm32f051", feature = "stm32f058"))]
 i2c_pins! {
     I2C2 => {
         scl => [gpiob::PB10<Alternate<AF1>>],
@@ -110,7 +130,9 @@ i2c_pins! {
     feature = "stm32f070xb",
     feature = "stm32f071",
     feature = "stm32f072",
+    feature = "stm32f078",
     feature = "stm32f091",
+    feature = "stm32f098",
 ))]
 i2c_pins! {
     I2C2 => {
@@ -118,7 +140,7 @@ i2c_pins! {
         sda => [gpiob::PB11<Alternate<AF1>>, gpiob::PB14<Alternate<AF5>>],
     }
 }
-#[cfg(feature = "stm32f091")]
+#[cfg(any(feature = "stm32f091", feature = "stm32f098"))]
 i2c_pins! {
     I2C2 => {
         scl => [gpioa::PA11<Alternate<AF5>>],
@@ -162,10 +184,13 @@ i2c! {
 #[cfg(any(
     feature = "stm32f030xc",
     feature = "stm32f051",
+    feature = "stm32f058",
     feature = "stm32f070xb",
     feature = "stm32f071",
     feature = "stm32f072",
+    feature = "stm32f078",
     feature = "stm32f091",
+    feature = "stm32f098",
 ))]
 i2c! {
     I2C2: (i2c2, i2c2en, i2c2rst, apb1enr, apb1rstr),
diff --git a/src/lib.rs b/src/lib.rs
index cf36be8..510e1b4 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -17,6 +17,15 @@ pub use stm32f0::stm32f0x1 as stm32;
 #[cfg(any(feature = "stm32f042", feature = "stm32f072"))]
 pub use stm32f0::stm32f0x2 as stm32;
 
+#[cfg(any(
+    feature = "stm32f038",
+    feature = "stm32f048",
+    feature = "stm32f058",
+    feature = "stm32f078",
+    feature = "stm32f098",
+))]
+pub use stm32f0::stm32f0x8 as stm32;
+
 #[cfg(feature = "device-selected")]
 pub mod adc;
 #[cfg(feature = "device-selected")]
diff --git a/src/serial.rs b/src/serial.rs
index 7c620e9..11d9253 100644
--- a/src/serial.rs
+++ b/src/serial.rs
@@ -116,45 +116,46 @@ macro_rules! usart_pins {
 
 #[cfg(any(
     feature = "stm32f030",
+    feature = "stm32f031",
+    feature = "stm32f038",
     feature = "stm32f042",
+    feature = "stm32f048",
     feature = "stm32f051",
+    feature = "stm32f058",
+    feature = "stm32f070",
     feature = "stm32f071",
+    feature = "stm32f072",
+    feature = "stm32f078",
+    feature = "stm32f091",
+    feature = "stm32f098",
 ))]
 usart_pins! {
-    USART1 =>  {
+    USART1 => {
         tx => [gpioa::PA9<Alternate<AF1>>, gpiob::PB6<Alternate<AF0>>],
-        rx => [gpioa::PA10<Alternate<AF1>>, gpiob::PB6<Alternate<AF0>>],
+        rx => [gpioa::PA10<Alternate<AF1>>, gpiob::PB7<Alternate<AF0>>],
     }
 }
-#[cfg(any(feature = "stm32f031", feature = "stm32f030x6"))]
+#[cfg(any(feature = "stm32f030x6", feature = "stm32f031", feature = "stm32f038"))]
 usart_pins! {
     USART1 => {
         tx => [gpioa::PA2<Alternate<AF1>>, gpioa::PA14<Alternate<AF1>>],
         rx => [gpioa::PA3<Alternate<AF1>>, gpioa::PA15<Alternate<AF1>>],
     }
 }
-#[cfg(any(
-    feature = "stm32f031",
-    feature = "stm32f070",
-    feature = "stm32f072",
-    feature = "stm32f091",
-))]
-usart_pins! {
-    USART1 => {
-        tx => [gpioa::PA9<Alternate<AF1>>, gpiob::PB6<Alternate<AF0>>],
-        rx => [gpioa::PA10<Alternate<AF1>>, gpiob::PB7<Alternate<AF0>>],
-    }
-}
 
 #[cfg(any(
     feature = "stm32f030x8",
     feature = "stm32f030xc",
     feature = "stm32f042",
+    feature = "stm32f048",
     feature = "stm32f051",
+    feature = "stm32f058",
     feature = "stm32f070",
     feature = "stm32f071",
     feature = "stm32f072",
+    feature = "stm32f078",
     feature = "stm32f091",
+    feature = "stm32f098",
 ))]
 usart_pins! {
     USART2 => {
@@ -162,7 +163,13 @@ usart_pins! {
         rx => [gpioa::PA3<Alternate<AF1>>, gpioa::PA15<Alternate<AF1>>],
     }
 }
-#[cfg(any(feature = "stm32f072", feature = "stm32f071", feature = "stm32f091"))]
+#[cfg(any(
+    feature = "stm32f072",
+    feature = "stm32f071",
+    feature = "stm32f078",
+    feature = "stm32f091",
+    feature = "stm32f098",
+))]
 usart_pins! {
     USART2 => {
         tx => [gpiod::PD5<Alternate<AF0>>],
@@ -175,7 +182,9 @@ usart_pins! {
     feature = "stm32f070xb",
     feature = "stm32f071",
     feature = "stm32f072",
+    feature = "stm32f078",
     feature = "stm32f091",
+    feature = "stm32f098",
 ))]
 usart_pins! {
     USART3 => {
@@ -188,7 +197,13 @@ usart_pins! {
         rx => [gpioa::PA1<Alternate<AF4>>, gpioc::PC11<Alternate<AF0>>],
     }
 }
-#[cfg(any(feature = "stm32f071", feature = "stm32f072", feature = "stm32f091"))]
+#[cfg(any(
+    feature = "stm32f071",
+    feature = "stm32f072",
+    feature = "stm32f078",
+    feature = "stm32f091",
+    feature = "stm32f098",
+))]
 usart_pins! {
     USART3 => {
         tx => [gpiod::PD8<Alternate<AF0>>],
@@ -206,7 +221,7 @@ usart_pins! {
 //     }
 // }
 
-#[cfg(any(feature = "stm32f030xc", feature = "stm32f091"))]
+#[cfg(any(feature = "stm32f030xc", feature = "stm32f091", feature = "stm32f098"))]
 usart_pins! {
     USART5 => {
         tx => [gpiob::PB3<Alternate<AF4>>, gpioc::PC12<Alternate<AF2>>],
@@ -219,7 +234,7 @@ usart_pins! {
 }
 // TODO: The ST SVD files are missing the entire PE enable register.
 //       Re-enable as soon as this gets fixed.
-#[cfg(feature = "stm32f091")]
+#[cfg(any(feature = "stm32f091", feature = "stm32f098"))]
 usart_pins! {
     // USART5 => {
     //     tx => [gpioe::PE10<Alternate<AF1>>],
@@ -365,11 +380,15 @@ usart! {
     feature = "stm32f030x8",
     feature = "stm32f030xc",
     feature = "stm32f042",
+    feature = "stm32f048",
     feature = "stm32f051",
+    feature = "stm32f058",
     feature = "stm32f070",
     feature = "stm32f071",
     feature = "stm32f072",
+    feature = "stm32f078",
     feature = "stm32f091",
+    feature = "stm32f098",
 ))]
 usart! {
     USART2: (usart2, usart2tx, usart2rx,usart2en, apb1enr),
@@ -379,13 +398,15 @@ usart! {
     feature = "stm32f070xb",
     feature = "stm32f071",
     feature = "stm32f072",
+    feature = "stm32f078",
     feature = "stm32f091",
+    feature = "stm32f098",
 ))]
 usart! {
     USART3: (usart3, usart3tx, usart3rx,usart3en, apb1enr),
     USART4: (usart4, usart4tx, usart4rx,usart4en, apb1enr),
 }
-#[cfg(any(feature = "stm32f030xc", feature = "stm32f091"))]
+#[cfg(any(feature = "stm32f030xc", feature = "stm32f091", feature = "stm32f098"))]
 usart! {
     USART5: (usart5, usart5tx, usart5rx,usart5en, apb1enr),
     USART6: (usart6, usart6tx, usart6rx,usart6en, apb2enr),
diff --git a/src/spi.rs b/src/spi.rs
index 7818871..12ddeb9 100644
--- a/src/spi.rs
+++ b/src/spi.rs
@@ -49,10 +49,14 @@ use crate::stm32::SPI1;
 #[cfg(any(
     feature = "stm32f030x8",
     feature = "stm32f030xc",
+    feature = "stm32f048",
     feature = "stm32f051",
+    feature = "stm32f058",
     feature = "stm32f070xb",
     feature = "stm32f071",
+    feature = "stm32f078",
     feature = "stm32f091",
+    feature = "stm32f098",
 ))]
 use crate::stm32::SPI2;
 
@@ -112,7 +116,7 @@ spi_pins! {
         mosi => [gpioa::PA7<Alternate<AF0>>, gpiob::PB5<Alternate<AF0>>],
     }
 }
-#[cfg(feature = "stm32f030x6")]
+#[cfg(any(feature = "stm32f030x6", feature = "stm32f038"))]
 spi_pins! {
     SPI1 => {
         sck => [gpiob::PB13<Alternate<AF0>>],
@@ -123,7 +127,13 @@ spi_pins! {
 // TODO: The ST SVD files are missing the entire PE enable register.
 //       So those pins do not exist in the register definitions.
 //       Re-enable as soon as this gets fixed.
-// #[cfg(any(feature = "stm32f071", feature = "stm32f072", feature = "stm32f091"))]
+// #[cfg(any(
+//     feature = "stm32f071",
+//     feature = "stm32f072",
+//     feature = "stm32f078",
+//     feature = "stm32f091",
+//     feature = "stm32f098",
+// ))]
 // spi_pins! {
 //     SPI1 => {
 //         sck => [gpioe::PE13<Alternate<AF1>>],
@@ -135,11 +145,15 @@ spi_pins! {
 #[cfg(any(
     feature = "stm32f030x8",
     feature = "stm32f030xc",
+    feature = "stm32f048",
     feature = "stm32f051",
+    feature = "stm32f058",
     feature = "stm32f070xb",
     feature = "stm32f071",
     feature = "stm32f072",
+    feature = "stm32f078",
     feature = "stm32f091",
+    feature = "stm32f098",
 ))]
 spi_pins! {
     SPI2 => {
@@ -153,7 +167,9 @@ spi_pins! {
     feature = "stm32f070xb",
     feature = "stm32f071",
     feature = "stm32f072",
+    feature = "stm32f078",
     feature = "stm32f091",
+    feature = "stm32f098",
 ))]
 spi_pins! {
     SPI2 => {
@@ -162,7 +178,13 @@ spi_pins! {
         mosi => [gpioc::PC3<Alternate<AF1>>],
     }
 }
-#[cfg(any(feature = "stm32f071", feature = "stm32f072", feature = "stm32f091"))]
+#[cfg(any(
+    feature = "stm32f071",
+    feature = "stm32f072",
+    feature = "stm32f078",
+    feature = "stm32f091",
+    feature = "stm32f098",
+))]
 spi_pins! {
     SPI2 => {
         sck => [gpiod::PD1<Alternate<AF1>>],
@@ -209,10 +231,14 @@ spi! {
 #[cfg(any(
     feature = "stm32f030x8",
     feature = "stm32f030xc",
+    feature = "stm32f048",
     feature = "stm32f051",
+    feature = "stm32f058",
     feature = "stm32f070xb",
     feature = "stm32f071",
+    feature = "stm32f078",
     feature = "stm32f091",
+    feature = "stm32f098",
 ))]
 spi! {
     SPI2: (spi2, spi2en, spi2rst, apb1enr, apb1rstr),
diff --git a/src/timers.rs b/src/timers.rs
index 08e8018..f33ad69 100644
--- a/src/timers.rs
+++ b/src/timers.rs
@@ -224,11 +224,16 @@ timers! {
 
 #[cfg(any(
     feature = "stm32f031",
+    feature = "stm32f038",
     feature = "stm32f042",
+    feature = "stm32f048",
     feature = "stm32f051",
+    feature = "stm32f058",
     feature = "stm32f071",
     feature = "stm32f072",
+    feature = "stm32f078",
     feature = "stm32f091",
+    feature = "stm32f098",
 ))]
 timers! {
     TIM2: (tim2, tim2en, tim2rst, apb1enr, apb1rstr),
@@ -238,10 +243,13 @@ timers! {
     feature = "stm32f030x8",
     feature = "stm32f030xc",
     feature = "stm32f051",
+    feature = "stm32f058",
     feature = "stm32f070xb",
     feature = "stm32f071",
     feature = "stm32f072",
+    feature = "stm32f078",
     feature = "stm32f091",
+    feature = "stm32f098",
 ))]
 timers! {
     TIM6: (tim6, tim6en, tim6rst, apb1enr, apb1rstr),
@@ -252,7 +260,9 @@ timers! {
     feature = "stm32f030xc",
     feature = "stm32f070xb",
     feature = "stm32f072",
+    feature = "stm32f078",
     feature = "stm32f091",
+    feature = "stm32f098",
 ))]
 timers! {
     TIM7: (tim7, tim7en, tim7rst, apb1enr, apb1rstr),