Merge pull request #43 from jessebraham/stm32f0x1
Add support for stm32f031, stm32f051, stm32f071
This commit is contained in:
Daniel Egger
GitHub
commit
ac4c91b95f
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@ -9,7 +9,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
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### Added
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- Support for STM32F091 - @jessebraham
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- Support for stm32f0x1 line - @jessebraham
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- Support for HSE as a system clocksource (#25 - breaking change) - @zklapow
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### Changed
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@ -66,7 +66,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
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- Reworked GPIOs and added fully erased pins
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- Timer support
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- Support for STM32F070
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- Support for STM32F070 - @jessebraham
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- Additional peripheral support for STM32F030
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- Watchdog support
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@ -46,15 +46,18 @@ panic-halt = "0.2.0"
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[features]
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device-selected = []
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rt = ["stm32f0/rt"]
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stm32f042 = ["stm32f0/stm32f0x2", "device-selected"]
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stm32f030 = ["stm32f0/stm32f0x0", "device-selected"]
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stm32f030x4 = ["stm32f030x6"]
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stm32f030x6 = ["stm32f030"]
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stm32f030x8 = ["stm32f030"]
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stm32f030xc = ["stm32f030"]
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stm32f031 = ["stm32f0/stm32f0x1", "device-selected"]
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stm32f042 = ["stm32f0/stm32f0x2", "device-selected"]
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stm32f051 = ["stm32f0/stm32f0x1", "device-selected"]
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stm32f070 = ["stm32f0/stm32f0x0", "device-selected"]
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stm32f070x6 = ["stm32f070"]
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stm32f070xb = ["stm32f070"]
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stm32f071 = ["stm32f0/stm32f0x1", "device-selected"]
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stm32f072 = ["stm32f0/stm32f0x2", "device-selected"]
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stm32f091 = ["stm32f0/stm32f0x1", "device-selected"]
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@ -18,8 +18,11 @@ Supported Configurations
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------------------------
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* __stm32f030__ (stm32f030x4, stm32f030x6, stm32f030x8, stm32f030xc)
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* __stm32f031__
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* __stm32f042__
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* __stm32f051__
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* __stm32f070__ (stm32f070x6, stm32f070xb)
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* __stm32f071__
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* __stm32f072__
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* __stm32f091__
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29
src/adc.rs
29
src/adc.rs
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@ -206,7 +206,9 @@ adc_pins!(
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#[cfg(any(
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feature = "stm32f030",
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feature = "stm32f051",
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feature = "stm32f070",
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feature = "stm32f071",
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feature = "stm32f072",
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feature = "stm32f091"
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))]
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@ -350,17 +352,38 @@ impl VRef {
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}
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}
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#[cfg(any(feature = "stm32f042", feature = "stm32f072", feature = "stm32f091"))]
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#[cfg(any(
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feature = "stm32f031",
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feature = "stm32f042",
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feature = "stm32f051",
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feature = "stm32f071",
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feature = "stm32f072",
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feature = "stm32f091",
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))]
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#[derive(Debug, Default)]
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/// Battery reference voltage (ADC Channel 18)
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pub struct VBat;
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#[cfg(any(feature = "stm32f042", feature = "stm32f072", feature = "stm32f091"))]
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#[cfg(any(
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feature = "stm32f031",
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feature = "stm32f042",
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feature = "stm32f051",
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feature = "stm32f071",
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feature = "stm32f072",
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feature = "stm32f091",
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))]
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adc_pins!(
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VBat => 18_u8,
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);
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#[cfg(any(feature = "stm32f042", feature = "stm32f072", feature = "stm32f091"))]
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#[cfg(any(
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feature = "stm32f031",
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feature = "stm32f042",
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feature = "stm32f051",
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feature = "stm32f071",
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feature = "stm32f072",
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feature = "stm32f091",
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))]
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impl VBat {
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/// Init a new VBat
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pub fn new() -> Self {
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22
src/gpio.rs
22
src/gpio.rs
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@ -570,7 +570,9 @@ gpio!(GPIOC, gpioc, iopcen, PC, [
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#[cfg(any(
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feature = "stm32f030",
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feature = "stm32f051",
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feature = "stm32f070",
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feature = "stm32f071",
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feature = "stm32f072",
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feature = "stm32f091",
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))]
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@ -593,12 +595,12 @@ gpio!(GPIOC, gpioc, iopcen, PC, [
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PC15: (pc15, 15, Input<Floating>),
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]);
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#[cfg(any(feature = "stm32f030", feature = "stm32f070"))]
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#[cfg(any(feature = "stm32f030", feature = "stm32f051", feature = "stm32f070"))]
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gpio!(GPIOD, gpiod, iopden, PD, [
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PD2: (pd2, 2, Input<Floating>),
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]);
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#[cfg(any(feature = "stm32f072", feature = "stm32f091"))]
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#[cfg(any(feature = "stm32f071", feature = "stm32f072", feature = "stm32f091"))]
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gpio!(GPIOD, gpiod, iopden, PD, [
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PD0: (pd0, 0, Input<Floating>),
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PD1: (pd1, 1, Input<Floating>),
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@ -621,7 +623,7 @@ gpio!(GPIOD, gpiod, iopden, PD, [
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// TODO: The ST SVD files are missing the entire PE enable register.
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// Re-enable as soon as this gets fixed.
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// #[cfg(any(feature = "stm32f072", feature = "stm32f091"))]
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// #[cfg(any(feature = "stm32f071", feature = "stm32f072", feature = "stm32f091"))]
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// gpio!(GPIOE, gpioe, iopeen, PE, [
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// PE0: (pe0, 0, Input<Floating>),
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// PE1: (pe1, 1, Input<Floating>),
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@ -648,14 +650,20 @@ gpio!(GPIOF, gpiof, iopfen, PF, [
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PF11: (pf11, 11, Input<Floating>),
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]);
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#[cfg(feature = "stm32f030")]
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#[cfg(any(feature = "stm32f030", feature = "stm32f051"))]
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gpio!(GPIOF, gpiof, iopfen, PF, [
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PF0: (pf0, 0, Input<Floating>),
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PF1: (pf1, 1, Input<Floating>),
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PF4: (pf4, 4, Input<Floating>),
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PF5: (pf5, 5, Input<Floating>),
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PF6: (pf6, 5, Input<Floating>),
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PF7: (pf7, 5, Input<Floating>),
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PF6: (pf6, 6, Input<Floating>),
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PF7: (pf7, 7, Input<Floating>),
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]);
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#[cfg(feature = "stm32f031")]
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gpio!(GPIOF, gpiof, iopfen, PF, [
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PF6: (pf6, 6, Input<Floating>),
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PF7: (pf7, 7, Input<Floating>),
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]);
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#[cfg(feature = "stm32f070")]
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@ -664,7 +672,7 @@ gpio!(GPIOF, gpiof, iopfen, PF, [
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PF1: (pf1, 1, Input<Floating>),
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]);
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#[cfg(any(feature = "stm32f072", feature = "stm32f091"))]
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#[cfg(any(feature = "stm32f071", feature = "stm32f072", feature = "stm32f091"))]
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gpio!(GPIOF, gpiof, iopfen, PF, [
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PF0: (pf0, 0, Input<Floating>),
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PF1: (pf1, 1, Input<Floating>),
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39
src/i2c.rs
39
src/i2c.rs
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@ -33,16 +33,26 @@ macro_rules! i2c_pins {
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}
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}
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#[cfg(any(feature = "stm32f030", feature = "stm32f042"))]
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#[cfg(any(
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feature = "stm32f030",
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feature = "stm32f031",
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feature = "stm32f042",
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feature = "stm32f051",
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feature = "stm32f070",
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feature = "stm32f071",
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feature = "stm32f072",
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feature = "stm32f091",
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))]
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i2c_pins! {
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I2C1 => {
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scl => [gpioa::PA11<Alternate<AF5>>, gpiob::PB6<Alternate<AF1>>, gpiob::PB8<Alternate<AF1>>],
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sda => [gpioa::PA12<Alternate<AF5>>, gpiob::PB7<Alternate<AF1>>, gpiob::PB9<Alternate<AF1>>],
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scl => [gpiob::PB6<Alternate<AF1>>, gpiob::PB8<Alternate<AF1>>],
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sda => [gpiob::PB7<Alternate<AF1>>, gpiob::PB9<Alternate<AF1>>],
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}
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}
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#[cfg(any(
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feature = "stm32f030x6",
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feature = "stm32f030xc",
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feature = "stm32f031",
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feature = "stm32f042",
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feature = "stm32f091",
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))]
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@ -52,7 +62,14 @@ i2c_pins! {
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sda => [gpioa::PA10<Alternate<AF4>>],
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}
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}
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#[cfg(any(feature = "stm32f042", feature = "stm32f030x6"))]
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#[cfg(any(feature = "stm32f030", feature = "stm32f042"))]
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i2c_pins! {
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I2C1 => {
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scl => [gpioa::PA11<Alternate<AF5>>],
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sda => [gpioa::PA12<Alternate<AF5>>],
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}
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}
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#[cfg(any(feature = "stm32f031", feature = "stm32f042", feature = "stm32f030x6"))]
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i2c_pins! {
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I2C1 => {
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scl => [gpiob::PB10<Alternate<AF1>>],
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@ -66,13 +83,6 @@ i2c_pins! {
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sda => [gpiob::PB14<Alternate<AF5>>, gpiof::PF0<Alternate<AF1>>],
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}
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}
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#[cfg(any(feature = "stm32f070", feature = "stm32f072", feature = "stm32f091"))]
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i2c_pins! {
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I2C1 => {
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scl => [gpiob::PB6<Alternate<AF1>>, gpiob::PB8<Alternate<AF1>>],
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sda => [gpiob::PB7<Alternate<AF1>>, gpiob::PB9<Alternate<AF1>>],
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}
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}
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#[cfg(feature = "stm32f070x6")]
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i2c_pins! {
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I2C1 => {
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@ -88,7 +98,7 @@ i2c_pins! {
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}
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}
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#[cfg(any(feature = "stm32f030x8"))]
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#[cfg(any(feature = "stm32f030x8", feature = "stm32f051"))]
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i2c_pins! {
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I2C2 => {
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scl => [gpiob::PB10<Alternate<AF1>>],
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@ -98,6 +108,7 @@ i2c_pins! {
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#[cfg(any(
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feature = "stm32f030xc",
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feature = "stm32f070xb",
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feature = "stm32f071",
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feature = "stm32f072",
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feature = "stm32f091",
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))]
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@ -150,9 +161,9 @@ i2c! {
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#[cfg(any(
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feature = "stm32f030xc",
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// XXX: This can't be right
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feature = "stm32f030xc",
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feature = "stm32f051",
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feature = "stm32f070xb",
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feature = "stm32f071",
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feature = "stm32f072",
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feature = "stm32f091",
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))]
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@ -6,7 +6,12 @@ pub use stm32f0;
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#[cfg(any(feature = "stm32f030", feature = "stm32f070"))]
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pub use stm32f0::stm32f0x0 as stm32;
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#[cfg(feature = "stm32f091")]
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#[cfg(any(
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feature = "stm32f031",
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feature = "stm32f051",
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feature = "stm32f071",
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feature = "stm32f091",
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))]
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pub use stm32f0::stm32f0x1 as stm32;
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#[cfg(any(feature = "stm32f042", feature = "stm32f072"))]
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@ -85,32 +85,45 @@ macro_rules! usart_pins {
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}
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}
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#[cfg(any(feature = "stm32f030", feature = "stm32f042"))]
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#[cfg(any(
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feature = "stm32f030",
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feature = "stm32f042",
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feature = "stm32f051",
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feature = "stm32f071",
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))]
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usart_pins! {
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USART1 => {
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tx => [gpioa::PA9<Alternate<AF1>>, gpiob::PB6<Alternate<AF0>>],
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rx => [gpioa::PA10<Alternate<AF1>>, gpiob::PB6<Alternate<AF0>>],
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}
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}
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#[cfg(feature = "stm32f030x6")]
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#[cfg(any(feature = "stm32f031", feature = "stm32f030x6"))]
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usart_pins! {
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USART1 => {
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tx => [gpioa::PA2<Alternate<AF1>>, gpioa::PA14<Alternate<AF1>>],
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rx => [gpioa::PA3<Alternate<AF1>>, gpioa::PA15<Alternate<AF1>>],
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}
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}
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#[cfg(any(feature = "stm32f070", feature = "stm32f072", feature = "stm32f091"))]
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#[cfg(any(
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feature = "stm32f031",
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feature = "stm32f070",
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feature = "stm32f072",
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feature = "stm32f091",
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))]
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usart_pins! {
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USART1 => {
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tx => [gpioa::PA9<Alternate<AF1>>, gpiob::PB6<Alternate<AF0>>],
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rx => [gpioa::PA10<Alternate<AF1>>, gpiob::PB7<Alternate<AF0>>],
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}
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}
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#[cfg(any(
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feature = "stm32f030x8",
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feature = "stm32f030xc",
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feature = "stm32f042",
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feature = "stm32f051",
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feature = "stm32f070",
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feature = "stm32f071",
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feature = "stm32f072",
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feature = "stm32f091",
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))]
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@ -120,16 +133,18 @@ usart_pins! {
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rx => [gpioa::PA3<Alternate<AF1>>, gpioa::PA15<Alternate<AF1>>],
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}
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}
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#[cfg(any(feature = "stm32f072", feature = "stm32f091"))]
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#[cfg(any(feature = "stm32f072", feature = "stm32f071", feature = "stm32f091"))]
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usart_pins! {
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USART2 => {
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tx => [gpiod::PD5<Alternate<AF0>>],
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rx => [gpiod::PD6<Alternate<AF0>>],
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}
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}
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#[cfg(any(
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feature = "stm32f030xc",
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feature = "stm32f070xb",
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feature = "stm32f071",
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feature = "stm32f072",
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feature = "stm32f091",
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))]
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@ -144,13 +159,14 @@ usart_pins! {
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rx => [gpioa::PA1<Alternate<AF4>>, gpioc::PC11<Alternate<AF0>>],
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}
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}
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#[cfg(any(feature = "stm32f072", feature = "stm32f091"))]
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#[cfg(any(feature = "stm32f071", feature = "stm32f072", feature = "stm32f091"))]
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usart_pins! {
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USART3 => {
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tx => [gpiod::PD8<Alternate<AF0>>],
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rx => [gpiod::PD9<Alternate<AF0>>],
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}
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}
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// TODO: The ST SVD files are missing the entire PE enable register.
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// Re-enable as soon as this gets fixed.
|
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// #[cfg(feature = "stm32f091")]
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@ -160,6 +176,7 @@ usart_pins! {
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// rx => [gpioe::PE9<Alternate<AF1>>],
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// }
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// }
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#[cfg(any(feature = "stm32f030xc", feature = "stm32f091"))]
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usart_pins! {
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USART5 => {
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@ -278,7 +295,9 @@ usart! {
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feature = "stm32f030x8",
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feature = "stm32f030xc",
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feature = "stm32f042",
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feature = "stm32f051",
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feature = "stm32f070",
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feature = "stm32f071",
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feature = "stm32f072",
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feature = "stm32f091",
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))]
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@ -288,6 +307,7 @@ usart! {
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#[cfg(any(
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feature = "stm32f030xc",
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feature = "stm32f070xb",
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feature = "stm32f071",
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feature = "stm32f072",
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feature = "stm32f091",
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))]
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|
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11
src/spi.rs
11
src/spi.rs
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|
@ -49,7 +49,9 @@ use crate::stm32::SPI1;
|
|||
#[cfg(any(
|
||||
feature = "stm32f030x8",
|
||||
feature = "stm32f030xc",
|
||||
feature = "stm32f051",
|
||||
feature = "stm32f070xb",
|
||||
feature = "stm32f071",
|
||||
feature = "stm32f091",
|
||||
))]
|
||||
use crate::stm32::SPI2;
|
||||
|
|
@ -121,7 +123,7 @@ spi_pins! {
|
|||
// TODO: The ST SVD files are missing the entire PE enable register.
|
||||
// So those pins do not exist in the register definitions.
|
||||
// Re-enable as soon as this gets fixed.
|
||||
// #[cfg(any(feature = "stm32f072", feature = "stm32f091"))]
|
||||
// #[cfg(any(feature = "stm32f071", feature = "stm32f072", feature = "stm32f091"))]
|
||||
// spi_pins! {
|
||||
// SPI1 => {
|
||||
// sck => [gpioe::PE13<Alternate<AF1>>],
|
||||
|
|
@ -133,7 +135,9 @@ spi_pins! {
|
|||
#[cfg(any(
|
||||
feature = "stm32f030x8",
|
||||
feature = "stm32f030xc",
|
||||
feature = "stm32f051",
|
||||
feature = "stm32f070xb",
|
||||
feature = "stm32f071",
|
||||
feature = "stm32f072",
|
||||
feature = "stm32f091",
|
||||
))]
|
||||
|
|
@ -147,6 +151,7 @@ spi_pins! {
|
|||
#[cfg(any(
|
||||
feature = "stm32f030xc",
|
||||
feature = "stm32f070xb",
|
||||
feature = "stm32f071",
|
||||
feature = "stm32f072",
|
||||
feature = "stm32f091",
|
||||
))]
|
||||
|
|
@ -157,7 +162,7 @@ spi_pins! {
|
|||
mosi => [gpioc::PC3<Alternate<AF1>>],
|
||||
}
|
||||
}
|
||||
#[cfg(any(feature = "stm32f072", feature = "stm32f091"))]
|
||||
#[cfg(any(feature = "stm32f071", feature = "stm32f072", feature = "stm32f091"))]
|
||||
spi_pins! {
|
||||
SPI2 => {
|
||||
sck => [gpiod::PD1<Alternate<AF1>>],
|
||||
|
|
@ -204,7 +209,9 @@ spi! {
|
|||
#[cfg(any(
|
||||
feature = "stm32f030x8",
|
||||
feature = "stm32f030xc",
|
||||
feature = "stm32f051",
|
||||
feature = "stm32f070xb",
|
||||
feature = "stm32f071",
|
||||
feature = "stm32f091",
|
||||
))]
|
||||
spi! {
|
||||
|
|
|
|||
|
|
@ -222,10 +222,24 @@ timers! {
|
|||
TIM17: (tim17, tim17en, tim17rst, apb2enr, apb2rstr),
|
||||
}
|
||||
|
||||
#[cfg(any(
|
||||
feature = "stm32f031",
|
||||
feature = "stm32f042",
|
||||
feature = "stm32f051",
|
||||
feature = "stm32f071",
|
||||
feature = "stm32f072",
|
||||
feature = "stm32f091",
|
||||
))]
|
||||
timers! {
|
||||
TIM2: (tim2, tim2en, tim2rst, apb1enr, apb1rstr),
|
||||
}
|
||||
|
||||
#[cfg(any(
|
||||
feature = "stm32f030x8",
|
||||
feature = "stm32f030xc",
|
||||
feature = "stm32f051",
|
||||
feature = "stm32f070xb",
|
||||
feature = "stm32f071",
|
||||
feature = "stm32f072",
|
||||
feature = "stm32f091",
|
||||
))]
|
||||
|
|
@ -243,8 +257,3 @@ timers! {
|
|||
timers! {
|
||||
TIM7: (tim7, tim7en, tim7rst, apb1enr, apb1rstr),
|
||||
}
|
||||
|
||||
#[cfg(any(feature = "stm32f042", feature = "stm32f072", feature = "stm32f091"))]
|
||||
timers! {
|
||||
TIM2: (tim2, tim2en, tim2rst, apb1enr, apb1rstr),
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue