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Merge pull request #43 from jessebraham/stm32f0x1

Add support for stm32f031, stm32f051, stm32f071
trying.tmp
Daniel Egger 4 years ago committed by GitHub
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  1. 4
      CHANGELOG.md
  2. 5
      Cargo.toml
  3. 3
      README.md
  4. 29
      src/adc.rs
  5. 22
      src/gpio.rs
  6. 39
      src/i2c.rs
  7. 7
      src/lib.rs
  8. 30
      src/serial.rs
  9. 11
      src/spi.rs
  10. 19
      src/timers.rs

4
CHANGELOG.md

@ -9,7 +9,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
### Added
- Support for STM32F091 - @jessebraham
- Support for stm32f0x1 line - @jessebraham
- Support for HSE as a system clocksource (#25 - breaking change) - @zklapow
### Changed
@ -66,7 +66,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
- Reworked GPIOs and added fully erased pins
- Timer support
- Support for STM32F070
- Support for STM32F070 - @jessebraham
- Additional peripheral support for STM32F030
- Watchdog support

5
Cargo.toml

@ -46,15 +46,18 @@ panic-halt = "0.2.0"
[features]
device-selected = []
rt = ["stm32f0/rt"]
stm32f042 = ["stm32f0/stm32f0x2", "device-selected"]
stm32f030 = ["stm32f0/stm32f0x0", "device-selected"]
stm32f030x4 = ["stm32f030x6"]
stm32f030x6 = ["stm32f030"]
stm32f030x8 = ["stm32f030"]
stm32f030xc = ["stm32f030"]
stm32f031 = ["stm32f0/stm32f0x1", "device-selected"]
stm32f042 = ["stm32f0/stm32f0x2", "device-selected"]
stm32f051 = ["stm32f0/stm32f0x1", "device-selected"]
stm32f070 = ["stm32f0/stm32f0x0", "device-selected"]
stm32f070x6 = ["stm32f070"]
stm32f070xb = ["stm32f070"]
stm32f071 = ["stm32f0/stm32f0x1", "device-selected"]
stm32f072 = ["stm32f0/stm32f0x2", "device-selected"]
stm32f091 = ["stm32f0/stm32f0x1", "device-selected"]

3
README.md

@ -18,8 +18,11 @@ Supported Configurations
------------------------
* __stm32f030__ (stm32f030x4, stm32f030x6, stm32f030x8, stm32f030xc)
* __stm32f031__
* __stm32f042__
* __stm32f051__
* __stm32f070__ (stm32f070x6, stm32f070xb)
* __stm32f071__
* __stm32f072__
* __stm32f091__

29
src/adc.rs

@ -206,7 +206,9 @@ adc_pins!(
#[cfg(any(
feature = "stm32f030",
feature = "stm32f051",
feature = "stm32f070",
feature = "stm32f071",
feature = "stm32f072",
feature = "stm32f091"
))]
@ -350,17 +352,38 @@ impl VRef {
}
}
#[cfg(any(feature = "stm32f042", feature = "stm32f072", feature = "stm32f091"))]
#[cfg(any(
feature = "stm32f031",
feature = "stm32f042",
feature = "stm32f051",
feature = "stm32f071",
feature = "stm32f072",
feature = "stm32f091",
))]
#[derive(Debug, Default)]
/// Battery reference voltage (ADC Channel 18)
pub struct VBat;
#[cfg(any(feature = "stm32f042", feature = "stm32f072", feature = "stm32f091"))]
#[cfg(any(
feature = "stm32f031",
feature = "stm32f042",
feature = "stm32f051",
feature = "stm32f071",
feature = "stm32f072",
feature = "stm32f091",
))]
adc_pins!(
VBat => 18_u8,
);
#[cfg(any(feature = "stm32f042", feature = "stm32f072", feature = "stm32f091"))]
#[cfg(any(
feature = "stm32f031",
feature = "stm32f042",
feature = "stm32f051",
feature = "stm32f071",
feature = "stm32f072",
feature = "stm32f091",
))]
impl VBat {
/// Init a new VBat
pub fn new() -> Self {

22
src/gpio.rs

@ -570,7 +570,9 @@ gpio!(GPIOC, gpioc, iopcen, PC, [
#[cfg(any(
feature = "stm32f030",
feature = "stm32f051",
feature = "stm32f070",
feature = "stm32f071",
feature = "stm32f072",
feature = "stm32f091",
))]
@ -593,12 +595,12 @@ gpio!(GPIOC, gpioc, iopcen, PC, [
PC15: (pc15, 15, Input<Floating>),
]);
#[cfg(any(feature = "stm32f030", feature = "stm32f070"))]
#[cfg(any(feature = "stm32f030", feature = "stm32f051", feature = "stm32f070"))]
gpio!(GPIOD, gpiod, iopden, PD, [
PD2: (pd2, 2, Input<Floating>),
]);
#[cfg(any(feature = "stm32f072", feature = "stm32f091"))]
#[cfg(any(feature = "stm32f071", feature = "stm32f072", feature = "stm32f091"))]
gpio!(GPIOD, gpiod, iopden, PD, [
PD0: (pd0, 0, Input<Floating>),
PD1: (pd1, 1, Input<Floating>),
@ -621,7 +623,7 @@ gpio!(GPIOD, gpiod, iopden, PD, [
// TODO: The ST SVD files are missing the entire PE enable register.
// Re-enable as soon as this gets fixed.
// #[cfg(any(feature = "stm32f072", feature = "stm32f091"))]
// #[cfg(any(feature = "stm32f071", feature = "stm32f072", feature = "stm32f091"))]
// gpio!(GPIOE, gpioe, iopeen, PE, [
// PE0: (pe0, 0, Input<Floating>),
// PE1: (pe1, 1, Input<Floating>),
@ -648,14 +650,20 @@ gpio!(GPIOF, gpiof, iopfen, PF, [
PF11: (pf11, 11, Input<Floating>),
]);
#[cfg(feature = "stm32f030")]
#[cfg(any(feature = "stm32f030", feature = "stm32f051"))]
gpio!(GPIOF, gpiof, iopfen, PF, [
PF0: (pf0, 0, Input<Floating>),
PF1: (pf1, 1, Input<Floating>),
PF4: (pf4, 4, Input<Floating>),
PF5: (pf5, 5, Input<Floating>),
PF6: (pf6, 5, Input<Floating>),
PF7: (pf7, 5, Input<Floating>),
PF6: (pf6, 6, Input<Floating>),
PF7: (pf7, 7, Input<Floating>),
]);
#[cfg(feature = "stm32f031")]
gpio!(GPIOF, gpiof, iopfen, PF, [
PF6: (pf6, 6, Input<Floating>),
PF7: (pf7, 7, Input<Floating>),
]);
#[cfg(feature = "stm32f070")]
@ -664,7 +672,7 @@ gpio!(GPIOF, gpiof, iopfen, PF, [
PF1: (pf1, 1, Input<Floating>),
]);
#[cfg(any(feature = "stm32f072", feature = "stm32f091"))]
#[cfg(any(feature = "stm32f071", feature = "stm32f072", feature = "stm32f091"))]
gpio!(GPIOF, gpiof, iopfen, PF, [
PF0: (pf0, 0, Input<Floating>),
PF1: (pf1, 1, Input<Floating>),

39
src/i2c.rs

@ -33,16 +33,26 @@ macro_rules! i2c_pins {
}
}
#[cfg(any(feature = "stm32f030", feature = "stm32f042"))]
#[cfg(any(
feature = "stm32f030",
feature = "stm32f031",
feature = "stm32f042",
feature = "stm32f051",
feature = "stm32f070",
feature = "stm32f071",
feature = "stm32f072",
feature = "stm32f091",
))]
i2c_pins! {
I2C1 => {
scl => [gpioa::PA11<Alternate<AF5>>, gpiob::PB6<Alternate<AF1>>, gpiob::PB8<Alternate<AF1>>],
sda => [gpioa::PA12<Alternate<AF5>>, gpiob::PB7<Alternate<AF1>>, gpiob::PB9<Alternate<AF1>>],
scl => [gpiob::PB6<Alternate<AF1>>, gpiob::PB8<Alternate<AF1>>],
sda => [gpiob::PB7<Alternate<AF1>>, gpiob::PB9<Alternate<AF1>>],
}
}
#[cfg(any(
feature = "stm32f030x6",
feature = "stm32f030xc",
feature = "stm32f031",
feature = "stm32f042",
feature = "stm32f091",
))]
@ -52,7 +62,14 @@ i2c_pins! {
sda => [gpioa::PA10<Alternate<AF4>>],
}
}
#[cfg(any(feature = "stm32f042", feature = "stm32f030x6"))]
#[cfg(any(feature = "stm32f030", feature = "stm32f042"))]
i2c_pins! {
I2C1 => {
scl => [gpioa::PA11<Alternate<AF5>>],
sda => [gpioa::PA12<Alternate<AF5>>],
}
}
#[cfg(any(feature = "stm32f031", feature = "stm32f042", feature = "stm32f030x6"))]
i2c_pins! {
I2C1 => {
scl => [gpiob::PB10<Alternate<AF1>>],
@ -66,13 +83,6 @@ i2c_pins! {
sda => [gpiob::PB14<Alternate<AF5>>, gpiof::PF0<Alternate<AF1>>],
}
}
#[cfg(any(feature = "stm32f070", feature = "stm32f072", feature = "stm32f091"))]
i2c_pins! {
I2C1 => {
scl => [gpiob::PB6<Alternate<AF1>>, gpiob::PB8<Alternate<AF1>>],
sda => [gpiob::PB7<Alternate<AF1>>, gpiob::PB9<Alternate<AF1>>],
}
}
#[cfg(feature = "stm32f070x6")]
i2c_pins! {
I2C1 => {
@ -88,7 +98,7 @@ i2c_pins! {
}
}
#[cfg(any(feature = "stm32f030x8"))]
#[cfg(any(feature = "stm32f030x8", feature = "stm32f051"))]
i2c_pins! {
I2C2 => {
scl => [gpiob::PB10<Alternate<AF1>>],
@ -98,6 +108,7 @@ i2c_pins! {
#[cfg(any(
feature = "stm32f030xc",
feature = "stm32f070xb",
feature = "stm32f071",
feature = "stm32f072",
feature = "stm32f091",
))]
@ -150,9 +161,9 @@ i2c! {
#[cfg(any(
feature = "stm32f030xc",
// XXX: This can't be right
feature = "stm32f030xc",
feature = "stm32f051",
feature = "stm32f070xb",
feature = "stm32f071",
feature = "stm32f072",
feature = "stm32f091",
))]

7
src/lib.rs

@ -6,7 +6,12 @@ pub use stm32f0;
#[cfg(any(feature = "stm32f030", feature = "stm32f070"))]
pub use stm32f0::stm32f0x0 as stm32;
#[cfg(feature = "stm32f091")]
#[cfg(any(
feature = "stm32f031",
feature = "stm32f051",
feature = "stm32f071",
feature = "stm32f091",
))]
pub use stm32f0::stm32f0x1 as stm32;
#[cfg(any(feature = "stm32f042", feature = "stm32f072"))]

30
src/serial.rs

@ -85,32 +85,45 @@ macro_rules! usart_pins {
}
}
#[cfg(any(feature = "stm32f030", feature = "stm32f042"))]
#[cfg(any(
feature = "stm32f030",
feature = "stm32f042",
feature = "stm32f051",
feature = "stm32f071",
))]
usart_pins! {
USART1 => {
tx => [gpioa::PA9<Alternate<AF1>>, gpiob::PB6<Alternate<AF0>>],
rx => [gpioa::PA10<Alternate<AF1>>, gpiob::PB6<Alternate<AF0>>],
}
}
#[cfg(feature = "stm32f030x6")]
#[cfg(any(feature = "stm32f031", feature = "stm32f030x6"))]
usart_pins! {
USART1 => {
tx => [gpioa::PA2<Alternate<AF1>>, gpioa::PA14<Alternate<AF1>>],
rx => [gpioa::PA3<Alternate<AF1>>, gpioa::PA15<Alternate<AF1>>],
}
}
#[cfg(any(feature = "stm32f070", feature = "stm32f072", feature = "stm32f091"))]
#[cfg(any(
feature = "stm32f031",
feature = "stm32f070",
feature = "stm32f072",
feature = "stm32f091",
))]
usart_pins! {
USART1 => {
tx => [gpioa::PA9<Alternate<AF1>>, gpiob::PB6<Alternate<AF0>>],
rx => [gpioa::PA10<Alternate<AF1>>, gpiob::PB7<Alternate<AF0>>],
}
}
#[cfg(any(
feature = "stm32f030x8",
feature = "stm32f030xc",
feature = "stm32f042",
feature = "stm32f051",
feature = "stm32f070",
feature = "stm32f071",
feature = "stm32f072",
feature = "stm32f091",
))]
@ -120,16 +133,18 @@ usart_pins! {
rx => [gpioa::PA3<Alternate<AF1>>, gpioa::PA15<Alternate<AF1>>],
}
}
#[cfg(any(feature = "stm32f072", feature = "stm32f091"))]
#[cfg(any(feature = "stm32f072", feature = "stm32f071", feature = "stm32f091"))]
usart_pins! {
USART2 => {
tx => [gpiod::PD5<Alternate<AF0>>],
rx => [gpiod::PD6<Alternate<AF0>>],
}
}
#[cfg(any(
feature = "stm32f030xc",
feature = "stm32f070xb",
feature = "stm32f071",
feature = "stm32f072",
feature = "stm32f091",
))]
@ -144,13 +159,14 @@ usart_pins! {
rx => [gpioa::PA1<Alternate<AF4>>, gpioc::PC11<Alternate<AF0>>],
}
}
#[cfg(any(feature = "stm32f072", feature = "stm32f091"))]
#[cfg(any(feature = "stm32f071", feature = "stm32f072", feature = "stm32f091"))]
usart_pins! {
USART3 => {
tx => [gpiod::PD8<Alternate<AF0>>],
rx => [gpiod::PD9<Alternate<AF0>>],
}
}
// TODO: The ST SVD files are missing the entire PE enable register.
// Re-enable as soon as this gets fixed.
// #[cfg(feature = "stm32f091")]
@ -160,6 +176,7 @@ usart_pins! {
// rx => [gpioe::PE9<Alternate<AF1>>],
// }
// }
#[cfg(any(feature = "stm32f030xc", feature = "stm32f091"))]
usart_pins! {
USART5 => {
@ -278,7 +295,9 @@ usart! {
feature = "stm32f030x8",
feature = "stm32f030xc",
feature = "stm32f042",
feature = "stm32f051",
feature = "stm32f070",
feature = "stm32f071",
feature = "stm32f072",
feature = "stm32f091",
))]
@ -288,6 +307,7 @@ usart! {
#[cfg(any(
feature = "stm32f030xc",
feature = "stm32f070xb",
feature = "stm32f071",
feature = "stm32f072",
feature = "stm32f091",
))]

11
src/spi.rs

@ -49,7 +49,9 @@ use crate::stm32::SPI1;
#[cfg(any(
feature = "stm32f030x8",
feature = "stm32f030xc",
feature = "stm32f051",
feature = "stm32f070xb",
feature = "stm32f071",
feature = "stm32f091",
))]
use crate::stm32::SPI2;
@ -121,7 +123,7 @@ spi_pins! {
// TODO: The ST SVD files are missing the entire PE enable register.
// So those pins do not exist in the register definitions.
// Re-enable as soon as this gets fixed.
// #[cfg(any(feature = "stm32f072", feature = "stm32f091"))]
// #[cfg(any(feature = "stm32f071", feature = "stm32f072", feature = "stm32f091"))]
// spi_pins! {
// SPI1 => {
// sck => [gpioe::PE13<Alternate<AF1>>],
@ -133,7 +135,9 @@ spi_pins! {
#[cfg(any(
feature = "stm32f030x8",
feature = "stm32f030xc",
feature = "stm32f051",
feature = "stm32f070xb",
feature = "stm32f071",
feature = "stm32f072",
feature = "stm32f091",
))]
@ -147,6 +151,7 @@ spi_pins! {
#[cfg(any(
feature = "stm32f030xc",
feature = "stm32f070xb",
feature = "stm32f071",
feature = "stm32f072",
feature = "stm32f091",
))]
@ -157,7 +162,7 @@ spi_pins! {
mosi => [gpioc::PC3<Alternate<AF1>>],
}
}
#[cfg(any(feature = "stm32f072", feature = "stm32f091"))]
#[cfg(any(feature = "stm32f071", feature = "stm32f072", feature = "stm32f091"))]
spi_pins! {
SPI2 => {
sck => [gpiod::PD1<Alternate<AF1>>],
@ -204,7 +209,9 @@ spi! {
#[cfg(any(
feature = "stm32f030x8",
feature = "stm32f030xc",
feature = "stm32f051",
feature = "stm32f070xb",
feature = "stm32f071",
feature = "stm32f091",
))]
spi! {

19
src/timers.rs

@ -222,10 +222,24 @@ timers! {
TIM17: (tim17, tim17en, tim17rst, apb2enr, apb2rstr),
}
#[cfg(any(
feature = "stm32f031",
feature = "stm32f042",
feature = "stm32f051",
feature = "stm32f071",
feature = "stm32f072",
feature = "stm32f091",
))]
timers! {
TIM2: (tim2, tim2en, tim2rst, apb1enr, apb1rstr),
}
#[cfg(any(
feature = "stm32f030x8",
feature = "stm32f030xc",
feature = "stm32f051",
feature = "stm32f070xb",
feature = "stm32f071",
feature = "stm32f072",
feature = "stm32f091",
))]
@ -243,8 +257,3 @@ timers! {
timers! {
TIM7: (tim7, tim7en, tim7rst, apb1enr, apb1rstr),
}
#[cfg(any(feature = "stm32f042", feature = "stm32f072", feature = "stm32f091"))]
timers! {
TIM2: (tim2, tim2en, tim2rst, apb1enr, apb1rstr),
}

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