Merge pull request #16 from jessebraham/stm32f070-peripherals

Add SPI and I2C support for STM32F070 devices

src/i2c.rs

@@ -64,14 +64,32 @@ i2c_pins! {
         sda => [gpiob::PB14<Alternate<AF5>>, gpiof::PF0<Alternate<AF1>>],
     }
 }
-#[cfg(any(feature = "stm32f030x8", feature = "stm32f030xc"))]
+#[cfg(feature = "stm32f070")]
+i2c_pins! {
+    I2C1 => {
+        scl => [gpiob::PB6<Alternate<AF1>>, gpiob::PB8<Alternate<AF1>>],
+        sda => [gpiob::PB7<Alternate<AF1>>, gpiob::PB9<Alternate<AF1>>],
+    }
+}
+#[cfg(feature = "stm32f070x6")]
+i2c_pins! {
+    I2C1 => {
+        scl => [gpioa::PA9<Alternate<AF4>>, gpiof::PF0<Alternate<AF1>>],
+        sda => [gpioa::PA10<Alternate<AF4>>, gpiof::PF1<Alternate<AF1>>],
+    }
+}
+#[cfg(any(
+    feature = "stm32f030x8",
+    feature = "stm32f030xc",
+    feature = "stm32f070xb"
+))]
 i2c_pins! {
     I2C2 => {
         scl => [gpiob::PB10<Alternate<AF1>>],
         sda => [gpiob::PB11<Alternate<AF1>>],
     }
 }
-#[cfg(feature = "stm32f030xc")]
+#[cfg(any(feature = "stm32f030xc", feature = "stm32f070xb"))]
 i2c_pins! {
     I2C2 => {
         scl => [gpiob::PB13<Alternate<AF5>>],
@@ -110,11 +128,15 @@ macro_rules! i2c {
         )+
     }
 }
-#[cfg(any(feature = "stm32f042", feature = "stm32f030"))]
+#[cfg(any(feature = "stm32f042", feature = "stm32f030", feature = "stm32f070"))]
 i2c! {
     I2C1: (i2c1, i2c1en, i2c1rst, apb1enr, apb1rstr),
 }
-#[cfg(any(feature = "stm32f030xc", feature = "stm32f030xc"))]
+#[cfg(any(
+    feature = "stm32f030xc",
+    feature = "stm32f030xc",
+    feature = "stm32f070xb"
+))]
 i2c! {
     I2C2: (i2c2, i2c2en, i2c2rst, apb1enr, apb1rstr),
 }

src/spi.rs

@@ -8,9 +8,13 @@ pub use embedded_hal::spi::{Mode, Phase, Polarity};
 use crate::stm32;
 // TODO Put this inside the macro
 // Currently that causes a compiler panic
-#[cfg(any(feature = "stm32f042", feature = "stm32f030"))]
+#[cfg(any(feature = "stm32f042", feature = "stm32f030", feature = "stm32f070"))]
 use crate::stm32::SPI1;
-#[cfg(any(feature = "stm32f030x8", feature = "stm32f030xc"))]
+#[cfg(any(
+    feature = "stm32f030x8",
+    feature = "stm32f030xc",
+    feature = "stm32f070xb"
+))]
 use crate::stm32::SPI2;
 
 use crate::gpio::*;
@@ -60,7 +64,7 @@ macro_rules! spi_pins {
     }
 }
 
-#[cfg(any(feature = "stm32f042", feature = "stm32f030"))]
+#[cfg(any(feature = "stm32f042", feature = "stm32f030", feature = "stm32f070"))]
 spi_pins! {
     SPI1 => {
         sck => [gpioa::PA5<Alternate<AF0>>, gpiob::PB3<Alternate<AF0>>],
@@ -76,7 +80,11 @@ spi_pins! {
         mosi => [gpiob::PB15<Alternate<AF0>>],
     }
 }
-#[cfg(any(feature = "stm32f030x8", feature = "stm32f030xc"))]
+#[cfg(any(
+    feature = "stm32f030x8",
+    feature = "stm32f030xc",
+    feature = "stm32f070xb"
+))]
 spi_pins! {
     SPI2 => {
         sck => [gpiob::PB13<Alternate<AF0>>],
@@ -84,7 +92,7 @@ spi_pins! {
         mosi => [gpiob::PB15<Alternate<AF0>>],
     }
 }
-#[cfg(feature = "stm32f030xc")]
+#[cfg(any(feature = "stm32f030xc", feature = "stm32f070xb"))]
 spi_pins! {
     SPI2 => {
         sck => [gpiob::PB10<Alternate<AF5>>],
@@ -126,11 +134,15 @@ macro_rules! spi {
     }
 }
 
-#[cfg(any(feature = "stm32f042", feature = "stm32f030"))]
+#[cfg(any(feature = "stm32f042", feature = "stm32f030", feature = "stm32f070"))]
 spi! {
     SPI1: (spi1, spi1en, spi1rst, apb2enr, apb2rstr),
 }
-#[cfg(any(feature = "stm32f030x8", feature = "stm32f030xc"))]
+#[cfg(any(
+    feature = "stm32f030x8",
+    feature = "stm32f030xc",
+    feature = "stm32f070xb"
+))]
 spi! {
     SPI2: (spi2, spi2en, spi2rst, apb1enr, apb1rstr),
 }