Add support for stm32f071
This commit is contained in:
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@ -57,6 +57,7 @@ stm32f051 = ["stm32f0/stm32f0x1", "device-selected"]
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stm32f070 = ["stm32f0/stm32f0x0", "device-selected"]
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stm32f070x6 = ["stm32f070"]
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stm32f070xb = ["stm32f070"]
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stm32f071 = ["stm32f0/stm32f0x1", "device-selected"]
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stm32f072 = ["stm32f0/stm32f0x2", "device-selected"]
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stm32f091 = ["stm32f0/stm32f0x1", "device-selected"]
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@ -208,6 +208,7 @@ adc_pins!(
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feature = "stm32f030",
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feature = "stm32f051",
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feature = "stm32f070",
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feature = "stm32f071",
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feature = "stm32f072",
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feature = "stm32f091"
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))]
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@ -355,6 +356,7 @@ impl VRef {
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feature = "stm32f031",
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feature = "stm32f042",
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feature = "stm32f051",
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feature = "stm32f071",
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feature = "stm32f072",
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feature = "stm32f091",
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))]
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@ -366,6 +368,7 @@ pub struct VBat;
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feature = "stm32f031",
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feature = "stm32f042",
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feature = "stm32f051",
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feature = "stm32f071",
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feature = "stm32f072",
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feature = "stm32f091",
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))]
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@ -377,6 +380,7 @@ adc_pins!(
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feature = "stm32f031",
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feature = "stm32f042",
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feature = "stm32f051",
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feature = "stm32f071",
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feature = "stm32f072",
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feature = "stm32f091",
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))]
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@ -572,6 +572,7 @@ gpio!(GPIOC, gpioc, iopcen, PC, [
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feature = "stm32f030",
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feature = "stm32f051",
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feature = "stm32f070",
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feature = "stm32f071",
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feature = "stm32f072",
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feature = "stm32f091",
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))]
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@ -599,7 +600,7 @@ gpio!(GPIOD, gpiod, iopden, PD, [
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PD2: (pd2, 2, Input<Floating>),
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]);
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#[cfg(any(feature = "stm32f072", feature = "stm32f091"))]
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#[cfg(any(feature = "stm32f071", feature = "stm32f072", feature = "stm32f091"))]
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gpio!(GPIOD, gpiod, iopden, PD, [
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PD0: (pd0, 0, Input<Floating>),
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PD1: (pd1, 1, Input<Floating>),
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@ -622,7 +623,7 @@ gpio!(GPIOD, gpiod, iopden, PD, [
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// TODO: The ST SVD files are missing the entire PE enable register.
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// Re-enable as soon as this gets fixed.
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// #[cfg(any(feature = "stm32f072", feature = "stm32f091"))]
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// #[cfg(any(feature = "stm32f071", feature = "stm32f072", feature = "stm32f091"))]
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// gpio!(GPIOE, gpioe, iopeen, PE, [
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// PE0: (pe0, 0, Input<Floating>),
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// PE1: (pe1, 1, Input<Floating>),
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@ -671,7 +672,7 @@ gpio!(GPIOF, gpiof, iopfen, PF, [
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PF1: (pf1, 1, Input<Floating>),
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]);
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#[cfg(any(feature = "stm32f072", feature = "stm32f091"))]
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#[cfg(any(feature = "stm32f071", feature = "stm32f072", feature = "stm32f091"))]
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gpio!(GPIOF, gpiof, iopfen, PF, [
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PF0: (pf0, 0, Input<Floating>),
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PF1: (pf1, 1, Input<Floating>),
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37
src/i2c.rs
37
src/i2c.rs
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@ -33,11 +33,20 @@ macro_rules! i2c_pins {
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}
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}
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#[cfg(any(feature = "stm32f030", feature = "stm32f042"))]
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#[cfg(any(
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feature = "stm32f030",
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feature = "stm32f031",
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feature = "stm32f042",
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feature = "stm32f051",
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feature = "stm32f070",
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feature = "stm32f071",
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feature = "stm32f072",
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feature = "stm32f091",
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))]
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i2c_pins! {
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I2C1 => {
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scl => [gpioa::PA11<Alternate<AF5>>, gpiob::PB6<Alternate<AF1>>, gpiob::PB8<Alternate<AF1>>],
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sda => [gpioa::PA12<Alternate<AF5>>, gpiob::PB7<Alternate<AF1>>, gpiob::PB9<Alternate<AF1>>],
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scl => [gpiob::PB6<Alternate<AF1>>, gpiob::PB8<Alternate<AF1>>],
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sda => [gpiob::PB7<Alternate<AF1>>, gpiob::PB9<Alternate<AF1>>],
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}
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}
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#[cfg(any(
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@ -53,6 +62,13 @@ i2c_pins! {
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sda => [gpioa::PA10<Alternate<AF4>>],
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}
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}
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#[cfg(any(feature = "stm32f030", feature = "stm32f042"))]
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i2c_pins! {
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I2C1 => {
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scl => [gpioa::PA11<Alternate<AF5>>],
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sda => [gpioa::PA12<Alternate<AF5>>],
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}
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}
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#[cfg(any(feature = "stm32f031", feature = "stm32f042", feature = "stm32f030x6"))]
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i2c_pins! {
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I2C1 => {
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@ -67,19 +83,6 @@ i2c_pins! {
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sda => [gpiob::PB14<Alternate<AF5>>, gpiof::PF0<Alternate<AF1>>],
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}
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}
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#[cfg(any(
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feature = "stm32f031",
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feature = "stm32f051",
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feature = "stm32f070",
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feature = "stm32f072",
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feature = "stm32f091",
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))]
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i2c_pins! {
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I2C1 => {
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scl => [gpiob::PB6<Alternate<AF1>>, gpiob::PB8<Alternate<AF1>>],
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sda => [gpiob::PB7<Alternate<AF1>>, gpiob::PB9<Alternate<AF1>>],
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}
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}
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#[cfg(feature = "stm32f070x6")]
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i2c_pins! {
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I2C1 => {
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@ -105,6 +108,7 @@ i2c_pins! {
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#[cfg(any(
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feature = "stm32f030xc",
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feature = "stm32f070xb",
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feature = "stm32f071",
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feature = "stm32f072",
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feature = "stm32f091",
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))]
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@ -159,6 +163,7 @@ i2c! {
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feature = "stm32f030xc",
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feature = "stm32f051",
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feature = "stm32f070xb",
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feature = "stm32f071",
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feature = "stm32f072",
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feature = "stm32f091",
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))]
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@ -6,7 +6,12 @@ pub use stm32f0;
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#[cfg(any(feature = "stm32f030", feature = "stm32f070"))]
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pub use stm32f0::stm32f0x0 as stm32;
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#[cfg(any(feature = "stm32f031", feature = "stm32f051", feature = "stm32f091"))]
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#[cfg(any(
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feature = "stm32f031",
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feature = "stm32f051",
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feature = "stm32f071",
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feature = "stm32f091",
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))]
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pub use stm32f0::stm32f0x1 as stm32;
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#[cfg(any(feature = "stm32f042", feature = "stm32f072"))]
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@ -85,7 +85,12 @@ macro_rules! usart_pins {
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}
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}
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#[cfg(any(feature = "stm32f030", feature = "stm32f042", feature = "stm32f051"))]
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#[cfg(any(
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feature = "stm32f030",
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feature = "stm32f042",
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feature = "stm32f051",
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feature = "stm32f071",
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))]
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usart_pins! {
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USART1 => {
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tx => [gpioa::PA9<Alternate<AF1>>, gpiob::PB6<Alternate<AF0>>],
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@ -118,6 +123,7 @@ usart_pins! {
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feature = "stm32f042",
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feature = "stm32f051",
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feature = "stm32f070",
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feature = "stm32f071",
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feature = "stm32f072",
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feature = "stm32f091",
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))]
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@ -127,16 +133,18 @@ usart_pins! {
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rx => [gpioa::PA3<Alternate<AF1>>, gpioa::PA15<Alternate<AF1>>],
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}
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}
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#[cfg(any(feature = "stm32f072", feature = "stm32f091"))]
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#[cfg(any(feature = "stm32f072", feature = "stm32f071", feature = "stm32f091"))]
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usart_pins! {
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USART2 => {
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tx => [gpiod::PD5<Alternate<AF0>>],
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rx => [gpiod::PD6<Alternate<AF0>>],
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}
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}
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#[cfg(any(
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feature = "stm32f030xc",
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feature = "stm32f070xb",
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feature = "stm32f071",
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feature = "stm32f072",
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feature = "stm32f091",
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))]
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@ -151,13 +159,14 @@ usart_pins! {
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rx => [gpioa::PA1<Alternate<AF4>>, gpioc::PC11<Alternate<AF0>>],
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}
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}
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#[cfg(any(feature = "stm32f072", feature = "stm32f091"))]
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#[cfg(any(feature = "stm32f071", feature = "stm32f072", feature = "stm32f091"))]
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usart_pins! {
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USART3 => {
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tx => [gpiod::PD8<Alternate<AF0>>],
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rx => [gpiod::PD9<Alternate<AF0>>],
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}
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}
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// TODO: The ST SVD files are missing the entire PE enable register.
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// Re-enable as soon as this gets fixed.
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// #[cfg(feature = "stm32f091")]
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@ -167,6 +176,7 @@ usart_pins! {
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// rx => [gpioe::PE9<Alternate<AF1>>],
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// }
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// }
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#[cfg(any(feature = "stm32f030xc", feature = "stm32f091"))]
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usart_pins! {
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USART5 => {
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@ -287,6 +297,7 @@ usart! {
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feature = "stm32f042",
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feature = "stm32f051",
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feature = "stm32f070",
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feature = "stm32f071",
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feature = "stm32f072",
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feature = "stm32f091",
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))]
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@ -296,6 +307,7 @@ usart! {
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#[cfg(any(
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feature = "stm32f030xc",
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feature = "stm32f070xb",
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feature = "stm32f071",
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feature = "stm32f072",
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feature = "stm32f091",
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))]
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@ -50,6 +50,7 @@ use crate::stm32::SPI1;
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feature = "stm32f030x8",
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feature = "stm32f030xc",
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feature = "stm32f070xb",
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feature = "stm32f071",
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feature = "stm32f091",
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))]
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use crate::stm32::SPI2;
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@ -121,7 +122,7 @@ spi_pins! {
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// TODO: The ST SVD files are missing the entire PE enable register.
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// So those pins do not exist in the register definitions.
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// Re-enable as soon as this gets fixed.
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// #[cfg(any(feature = "stm32f072", feature = "stm32f091"))]
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// #[cfg(any(feature = "stm32f071", feature = "stm32f072", feature = "stm32f091"))]
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// spi_pins! {
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// SPI1 => {
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// sck => [gpioe::PE13<Alternate<AF1>>],
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@ -135,6 +136,7 @@ spi_pins! {
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feature = "stm32f030xc",
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feature = "stm32f051",
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feature = "stm32f070xb",
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feature = "stm32f071",
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feature = "stm32f072",
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feature = "stm32f091",
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))]
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@ -148,6 +150,7 @@ spi_pins! {
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#[cfg(any(
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feature = "stm32f030xc",
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feature = "stm32f070xb",
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feature = "stm32f071",
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feature = "stm32f072",
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feature = "stm32f091",
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))]
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@ -158,7 +161,7 @@ spi_pins! {
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mosi => [gpioc::PC3<Alternate<AF1>>],
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}
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}
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#[cfg(any(feature = "stm32f072", feature = "stm32f091"))]
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#[cfg(any(feature = "stm32f071", feature = "stm32f072", feature = "stm32f091"))]
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spi_pins! {
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SPI2 => {
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sck => [gpiod::PD1<Alternate<AF1>>],
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@ -207,6 +210,7 @@ spi! {
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feature = "stm32f030xc",
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feature = "stm32f051",
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feature = "stm32f070xb",
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feature = "stm32f071",
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feature = "stm32f091",
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))]
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spi! {
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@ -222,11 +222,24 @@ timers! {
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TIM17: (tim17, tim17en, tim17rst, apb2enr, apb2rstr),
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}
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#[cfg(any(
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feature = "stm32f031",
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feature = "stm32f042",
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feature = "stm32f051",
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feature = "stm32f071",
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feature = "stm32f072",
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feature = "stm32f091",
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))]
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timers! {
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TIM2: (tim2, tim2en, tim2rst, apb1enr, apb1rstr),
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}
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#[cfg(any(
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feature = "stm32f030x8",
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feature = "stm32f030xc",
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feature = "stm32f051",
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feature = "stm32f070xb",
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feature = "stm32f071",
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feature = "stm32f072",
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feature = "stm32f091",
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))]
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timers! {
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TIM7: (tim7, tim7en, tim7rst, apb1enr, apb1rstr),
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}
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#[cfg(any(
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feature = "stm32f031",
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feature = "stm32f042",
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feature = "stm32f051",
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feature = "stm32f072",
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feature = "stm32f091",
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))]
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timers! {
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TIM2: (tim2, tim2en, tim2rst, apb1enr, apb1rstr),
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}
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