Ran rustfmt on the code
Signed-off-by: Daniel Egger <daniel@eggers-club.de>
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4c81088ce5
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@ -63,10 +63,7 @@ fn main() -> ! {
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// Move all components under Mutex supervision
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cortex_m::interrupt::free(move |cs| {
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*SHARED.borrow(cs).borrow_mut() = Some(Shared {
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adc,
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tx,
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});
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*SHARED.borrow(cs).borrow_mut() = Some(Shared { adc, tx });
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});
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}
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@ -85,7 +82,7 @@ fn SysTick() -> ! {
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if let Some(ref mut shared) = SHARED.borrow(cs).borrow_mut().deref_mut() {
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// Read temperature data from internal sensor using ADC
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let t = hal::adc::VTemp::read(&mut shared.adc, None);
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writeln!(shared.tx, "Temperature {}.{}C\r", t/100, t%100).ok();
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writeln!(shared.tx, "Temperature {}.{}C\r", t / 100, t % 100).ok();
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// Read volatage reference data from internal sensor using ADC
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let t = hal::adc::VRef::read_vdda(&mut shared.adc);
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67
src/rcc.rs
67
src/rcc.rs
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@ -1,4 +1,3 @@
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use core::cmp;
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use crate::time::Hertz;
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/// Extension trait that constrains the `RCC` peripheral
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@ -112,7 +111,7 @@ impl CFGR {
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} else {
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src_clk_freq = HSI; // If no clock source is selected use HSI.
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}
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// Pll check
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if sysclk == src_clk_freq {
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// Bypass pll if src clk and requested sysclk are the same, to save power.
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@ -121,8 +120,9 @@ impl CFGR {
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pllmul_bits = None;
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r_sysclk = src_clk_freq;
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} else {
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let pllmul = (4 * self.sysclk.unwrap_or(src_clk_freq) + src_clk_freq) / src_clk_freq / 2;
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let pllmul = cmp::min(cmp::max(pllmul, 2), 16);
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let pllmul =
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(4 * self.sysclk.unwrap_or(src_clk_freq) + src_clk_freq) / src_clk_freq / 2;
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let pllmul = core::cmp::min(core::cmp::max(pllmul, 2), 16);
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r_sysclk = pllmul * src_clk_freq / 2;
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pllmul_bits = if pllmul == 2 {
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@ -182,17 +182,17 @@ impl CFGR {
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let rcc = unsafe { &*crate::stm32::RCC::ptr() };
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// Set up rcc based on above calculated configuration.
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// Enable requested clock sources
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// HSI
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if self.enable_hsi {
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rcc.cr.write(|w| w.hsion().set_bit());
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while rcc.cr.read().hsirdy().bit_is_clear() { }
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while rcc.cr.read().hsirdy().bit_is_clear() {}
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}
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// HSI48
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if self.enable_hsi48 {
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rcc.cr2.modify(|_, w| w.hsi48on().set_bit());
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while rcc.cr2.read().hsi48rdy().bit_is_clear() { }
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while rcc.cr2.read().hsi48rdy().bit_is_clear() {}
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}
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// Enable PLL
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@ -201,15 +201,18 @@ impl CFGR {
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// Set PLL source based on configuration.
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if self.enable_hsi48 {
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rcc.cfgr.modify(|_, w| w.pllsrc().bits(PllSource::HSI48 as u8));
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rcc.cfgr
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.modify(|_, w| w.pllsrc().bits(PllSource::HSI48 as u8));
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} else if self.enable_hsi {
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rcc.cfgr.modify(|_, w| w.pllsrc().bits(PllSource::HSI_DIV2 as u8));
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rcc.cfgr
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.modify(|_, w| w.pllsrc().bits(PllSource::HSI_DIV2 as u8));
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} else {
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rcc.cfgr.modify(|_, w| w.pllsrc().bits(PllSource::HSI_DIV2 as u8));
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rcc.cfgr
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.modify(|_, w| w.pllsrc().bits(PllSource::HSI_DIV2 as u8));
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}
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rcc.cr.write(|w| w.pllon().set_bit());
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while rcc.cr.read().pllrdy().bit_is_clear() { }
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while rcc.cr.read().pllrdy().bit_is_clear() {}
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rcc.cfgr.modify(|_, w| unsafe {
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w.ppre()
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@ -219,30 +222,40 @@ impl CFGR {
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.sw()
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.bits(SysClkSource::PLL as u8)
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});
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} else { // No PLL required.
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} else {
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// No PLL required.
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// Setup requested clocks.
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if self.enable_hsi48 {
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rcc.cfgr.modify(|_, w| unsafe {
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w.ppre().bits(ppre_bits)
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.hpre().bits(hpre_bits)
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.sw().bits(SysClkSource::HSI48 as u8)
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rcc.cfgr.modify(|_, w| unsafe {
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w.ppre()
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.bits(ppre_bits)
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.hpre()
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.bits(hpre_bits)
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.sw()
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.bits(SysClkSource::HSI48 as u8)
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});
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} else if self.enable_hsi {
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rcc.cfgr.modify(|_, w| unsafe {
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w.ppre().bits(ppre_bits)
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.hpre().bits(hpre_bits)
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.sw().bits(SysClkSource::HSI as u8)
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});
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} else { // Default to HSI
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rcc.cfgr.modify(|_, w| unsafe {
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w.ppre().bits(ppre_bits)
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.hpre().bits(hpre_bits)
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.sw().bits(SysClkSource::HSI as u8)
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w.ppre()
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.bits(ppre_bits)
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.hpre()
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.bits(hpre_bits)
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.sw()
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.bits(SysClkSource::HSI as u8)
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});
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} else {
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// Default to HSI
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rcc.cfgr.modify(|_, w| unsafe {
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w.ppre()
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.bits(ppre_bits)
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.hpre()
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.bits(hpre_bits)
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.sw()
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.bits(SysClkSource::HSI as u8)
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});
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}
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}
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Clocks {
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hclk: Hertz(hclk),
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pclk: Hertz(pclk),
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@ -36,7 +36,6 @@ use embedded_hal::prelude::*;
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#[allow(unused)]
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use crate::{gpio::*, rcc::Clocks, time::Bps};
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/// Serial error
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#[derive(Debug)]
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pub enum Error {
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@ -281,11 +281,13 @@ impl<SPI, SCKPIN, MISOPIN, MOSIPIN> ::embedded_hal::blocking::spi::transfer::Def
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for Spi<SPI, SCKPIN, MISOPIN, MOSIPIN>
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where
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SPI: Deref<Target = SpiRegisterBlock>,
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{}
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{
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}
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#[cfg(feature = "device-selected")]
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impl<SPI, SCKPIN, MISOPIN, MOSIPIN> ::embedded_hal::blocking::spi::write::Default<u8>
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for Spi<SPI, SCKPIN, MISOPIN, MOSIPIN>
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where
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SPI: Deref<Target = SpiRegisterBlock>,
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{}
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{
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}
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