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Author SHA1 Message Date
Marc Poulhiès 34d2ee36e2 Implement FullDuplex for SPI and add check_errors method 2 years ago
Daniel Egger 2bb8bb9637
Merge pull request #126 from matoushybl/update-dependencies 2 years ago
Matous Hybl 5f656df6dc Update dependency versions. 2 years ago
Daniel Egger e679ab190f Bump version to 0.17.1 and release it 2 years ago
Daniel Egger 48d1b9a161
Merge pull request #120 from evils/complete_TscPin 2 years ago
  1. 10
      CHANGELOG.md
  2. 14
      Cargo.toml
  3. 97
      src/spi.rs

10
CHANGELOG.md

@ -7,7 +7,14 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
## [Unreleased]
## [v0.17.1] - 2020-08-30
### Changed
- Simplify USB PA11/12 remapping for STM32F042x via `usb_bus.usb_remap()` function.
### Added
- Complete the `TscPin` trait implementation for all touch pins in the f0 family
## [v0.17.0] - 2020-06-27
@ -207,7 +214,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
- Updated stm32f0 dependency to v0.5.0.
- Interrupt handler to new #[interrupt] attribute
[Unreleased]: https://github.com/stm32-rs/stm32f0xx-hal/compare/v0.17.0...HEAD
[Unreleased]: https://github.com/stm32-rs/stm32f0xx-hal/compare/v0.17.1...HEAD
[v0.17.1]: https://github.com/stm32-rs/stm32f0xx-hal/compare/v0.17.0...v0.17.1
[v0.17.0]: https://github.com/stm32-rs/stm32f0xx-hal/compare/v0.16.0...v0.17.0
[v0.16.0]: https://github.com/stm32-rs/stm32f0xx-hal/compare/v0.15.2...v0.16.0
[v0.15.2]: https://github.com/stm32-rs/stm32f0xx-hal/compare/v0.15.1...v0.15.2

14
Cargo.toml

@ -23,27 +23,27 @@ license = "0BSD"
name = "stm32f0xx-hal"
readme = "README.md"
repository = "https://github.com/stm32-rs/stm32f0xx-hal"
version = "0.17.0"
version = "0.17.1"
[package.metadata.docs.rs]
features = ["stm32f042", "rt", "stm32-usbd"]
targets = ["thumbv6m-none-eabi"]
[dependencies]
bare-metal = { version = "0.2", features = ["const-fn"] }
bare-metal = { version = "1.0.0" }
cast = { version = "0.2", default-features = false }
cortex-m = "0.6"
embedded-hal = { version = "0.2", features = ["unproven"] }
stm32f0 = "0.11"
nb = "0.1"
stm32f0 = "0.12.1"
nb = "1.0"
void = { version = "1.0", default-features = false }
stm32-usbd = { version = "0.5.0", features = ["ram_access_2x16"], optional = true }
stm32-usbd = { version = "0.5.1", features = ["ram_access_2x16"], optional = true }
[dev-dependencies]
cortex-m-rt = "0.6"
panic-halt = "0.2"
usb-device = "0.2.3"
usbd-serial = "0.1.0"
usb-device = "0.2.7"
usbd-serial = "0.1.1"
[features]
device-selected = []

97
src/spi.rs

@ -365,17 +365,27 @@ where
fn check_read(&mut self) -> nb::Result<(), Error> {
let sr = self.spi.sr.read();
Err(if sr.ovr().bit_is_set() {
nb::Error::Other(Error::Overrun)
self.check_errors()?;
if !sr.rxne().bit_is_set() {
Err(nb::Error::WouldBlock)
} else {
Ok(())
}
}
fn check_errors(&mut self) -> Result<(), Error> {
let sr = self.spi.sr.read();
if sr.ovr().bit_is_set() {
Err(Error::Overrun)
} else if sr.modf().bit_is_set() {
nb::Error::Other(Error::ModeFault)
Err(Error::ModeFault)
} else if sr.crcerr().bit_is_set() {
nb::Error::Other(Error::Crc)
} else if sr.rxne().bit_is_set() {
return Ok(());
Err(Error::Crc)
} else {
nb::Error::WouldBlock
})
Ok(())
}
}
fn send_buffer_size(&mut self) -> u8 {
@ -394,17 +404,13 @@ where
fn check_send(&mut self) -> nb::Result<(), Error> {
let sr = self.spi.sr.read();
Err(if sr.ovr().bit_is_set() {
nb::Error::Other(Error::Overrun)
} else if sr.modf().bit_is_set() {
nb::Error::Other(Error::ModeFault)
} else if sr.crcerr().bit_is_set() {
nb::Error::Other(Error::Crc)
} else if sr.txe().bit_is_set() {
return Ok(());
self.check_errors()?;
if !sr.txe().bit_is_set() {
Err(nb::Error::WouldBlock)
} else {
nb::Error::WouldBlock
})
Ok(())
}
}
fn read_u8(&mut self) -> u8 {
@ -454,6 +460,29 @@ where
}
}
impl<SPI, SCKPIN, MISOPIN, MOSIPIN> ::embedded_hal::spi::FullDuplex<u8>
for Spi<SPI, SCKPIN, MISOPIN, MOSIPIN, EightBit>
where
SPI: Deref<Target = SpiRegisterBlock>,
{
type Error = Error;
fn read(&mut self) -> nb::Result<u8, Error> {
self.check_read()?;
Ok(self.read_u8())
}
fn send(&mut self, byte: u8) -> nb::Result<(), Error> {
// We want to transfer bidirectionally, make sure we're in the correct mode
self.set_bidi();
self.check_send()?;
self.send_u8(byte);
self.check_errors().map_err(|e| nb::Error::Other(e))
}
}
impl<SPI, SCKPIN, MISOPIN, MOSIPIN> ::embedded_hal::blocking::spi::Write<u8>
for Spi<SPI, SCKPIN, MISOPIN, MOSIPIN, EightBit>
where
@ -482,8 +511,33 @@ where
}
// Do one last status register check before continuing
self.check_send().ok();
Ok(())
self.check_errors()
}
}
impl<SPI, SCKPIN, MISOPIN, MOSIPIN> ::embedded_hal::spi::FullDuplex<u16>
for Spi<SPI, SCKPIN, MISOPIN, MOSIPIN, SixteenBit>
where
SPI: Deref<Target = SpiRegisterBlock>,
{
type Error = Error;
fn read(&mut self) -> nb::Result<u16, Error> {
self.check_read()?;
Ok(self.read_u16())
}
fn send(&mut self, byte: u16) -> nb::Result<(), Error> {
// We want to transfer bidirectionally, make sure we're in the correct mode
self.set_bidi();
self.check_send()?;
self.send_u16(byte);
match self.check_errors() {
Ok(_) => Ok(()),
Err(e) => Err(nb::Error::Other(e)),
}
}
}
@ -526,7 +580,6 @@ where
}
// Do one last status register check before continuing
self.check_send().ok();
Ok(())
self.check_errors()
}
}

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