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361 lines
9.7 KiB
Rust
361 lines
9.7 KiB
Rust
#[allow(unused)]
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use core::ops::Deref;
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#[allow(unused)]
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use embedded_hal::blocking::i2c::{Write, WriteRead};
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#[allow(unused)]
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use crate::{
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gpio::*,
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time::{KiloHertz, U32Ext},
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};
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/// I2C abstraction
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#[allow(unused)]
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pub struct I2c<I2C, SCLPIN, SDAPIN> {
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i2c: I2C,
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pins: (SCLPIN, SDAPIN),
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}
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pub trait SclPin<I2C> {}
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pub trait SdaPin<I2C> {}
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#[allow(unused)]
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macro_rules! i2c_pins {
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($($I2C:ident => {
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scl => [$($scl:ty),+ $(,)*],
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sda => [$($sda:ty),+ $(,)*],
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})+) => {
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$(
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$(
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impl SclPin<crate::stm32::$I2C> for $scl {}
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)+
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$(
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impl SdaPin<crate::stm32::$I2C> for $sda {}
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)+
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)+
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}
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}
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#[cfg(any(feature = "stm32f030", feature = "stm32f042"))]
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i2c_pins! {
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I2C1 => {
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scl => [gpioa::PA11<Alternate<AF5>>, gpiob::PB6<Alternate<AF1>>, gpiob::PB8<Alternate<AF1>>],
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sda => [gpioa::PA12<Alternate<AF5>>, gpiob::PB7<Alternate<AF1>>, gpiob::PB9<Alternate<AF1>>],
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}
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}
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#[cfg(any(
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feature = "stm32f030x6",
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feature = "stm32f030xc",
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feature = "stm32f042",
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))]
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i2c_pins! {
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I2C1 => {
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scl => [gpioa::PA9<Alternate<AF4>>],
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sda => [gpioa::PA10<Alternate<AF4>>],
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}
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}
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#[cfg(any(feature = "stm32f042", feature = "stm32f030x6"))]
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i2c_pins! {
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I2C1 => {
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scl => [gpiob::PB10<Alternate<AF1>>],
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sda => [gpiob::PB11<Alternate<AF1>>],
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}
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}
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#[cfg(any(feature = "stm32f042", feature = "stm32f030xc"))]
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i2c_pins! {
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I2C1 => {
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scl => [gpiob::PB13<Alternate<AF5>>, gpiof::PF1<Alternate<AF1>>],
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sda => [gpiob::PB14<Alternate<AF5>>, gpiof::PF0<Alternate<AF1>>],
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}
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}
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#[cfg(feature = "stm32f070")]
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i2c_pins! {
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I2C1 => {
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scl => [gpiob::PB6<Alternate<AF1>>, gpiob::PB8<Alternate<AF1>>],
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sda => [gpiob::PB7<Alternate<AF1>>, gpiob::PB9<Alternate<AF1>>],
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}
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}
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#[cfg(feature = "stm32f070x6")]
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i2c_pins! {
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I2C1 => {
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scl => [gpioa::PA9<Alternate<AF4>>, gpiof::PF0<Alternate<AF1>>],
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sda => [gpioa::PA10<Alternate<AF4>>, gpiof::PF1<Alternate<AF1>>],
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}
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}
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#[cfg(any(
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feature = "stm32f030x8",
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feature = "stm32f030xc",
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feature = "stm32f070xb"
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))]
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i2c_pins! {
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I2C2 => {
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scl => [gpiob::PB10<Alternate<AF1>>],
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sda => [gpiob::PB11<Alternate<AF1>>],
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}
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}
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#[cfg(any(feature = "stm32f030xc", feature = "stm32f070xb"))]
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i2c_pins! {
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I2C2 => {
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scl => [gpiob::PB13<Alternate<AF5>>],
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sda => [gpiob::PB14<Alternate<AF5>>],
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}
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}
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#[derive(Debug)]
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pub enum Error {
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OVERRUN,
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NACK,
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}
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#[allow(unused)]
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macro_rules! i2c {
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($($I2C:ident: ($i2c:ident, $i2cXen:ident, $i2cXrst:ident, $apbenr:ident, $apbrstr:ident),)+) => {
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$(
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use crate::stm32::$I2C;
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impl<SCLPIN, SDAPIN> I2c<$I2C, SCLPIN, SDAPIN> {
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pub fn $i2c(i2c: $I2C, pins: (SCLPIN, SDAPIN), speed: KiloHertz) -> Self
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where
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SCLPIN: SclPin<$I2C>,
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SDAPIN: SdaPin<$I2C>,
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{
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// NOTE(unsafe) This executes only during initialisation
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let rcc = unsafe { &(*crate::stm32::RCC::ptr()) };
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// Enable clock for I2C
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rcc.$apbenr.modify(|_, w| w.$i2cXen().set_bit());
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// Reset I2C
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rcc.$apbrstr.modify(|_, w| w.$i2cXrst().set_bit());
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rcc.$apbrstr.modify(|_, w| w.$i2cXrst().clear_bit());
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I2c { i2c, pins }.i2c_init(speed)
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}
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}
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)+
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}
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}
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#[cfg(feature = "device-selected")]
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i2c! {
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I2C1: (i2c1, i2c1en, i2c1rst, apb1enr, apb1rstr),
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}
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#[cfg(any(
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feature = "stm32f030xc",
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// XXX: This can't be right
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feature = "stm32f030xc",
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feature = "stm32f070xb"
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))]
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i2c! {
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I2C2: (i2c2, i2c2en, i2c2rst, apb1enr, apb1rstr),
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}
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#[cfg(feature = "device-selected")]
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// It's s needed for the impls, but rustc doesn't recognize that
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#[allow(dead_code)]
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type I2cRegisterBlock = crate::stm32::i2c1::RegisterBlock;
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#[cfg(feature = "device-selected")]
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impl<I2C, SCLPIN, SDAPIN> I2c<I2C, SCLPIN, SDAPIN>
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where
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I2C: Deref<Target = I2cRegisterBlock>,
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{
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fn i2c_init(self: Self, speed: KiloHertz) -> Self {
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use core::cmp;
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// Make sure the I2C unit is disabled so we can configure it
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self.i2c.cr1.modify(|_, w| w.pe().clear_bit());
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// Calculate settings for I2C speed modes
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let presc;
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let scldel;
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let sdadel;
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let sclh;
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let scll;
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// We're using HSI here which runs at a fixed 8MHz
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const FREQ: u32 = 8_000_000;
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// Normal I2C speeds use a different scaling than fast mode below
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if speed <= 100_u32.khz() {
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presc = 1;
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scll = cmp::max((((FREQ >> presc) >> 1) / speed.0) - 1, 255) as u8;
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sclh = scll - 4;
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sdadel = 2;
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scldel = 4;
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} else {
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presc = 0;
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scll = cmp::max((((FREQ >> presc) >> 1) / speed.0) - 1, 255) as u8;
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sclh = scll - 6;
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sdadel = 1;
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scldel = 3;
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}
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// Enable I2C signal generator, and configure I2C for 400KHz full speed
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self.i2c.timingr.write(|w| {
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w.presc()
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.bits(presc)
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.scldel()
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.bits(scldel)
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.sdadel()
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.bits(sdadel)
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.sclh()
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.bits(sclh)
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.scll()
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.bits(scll)
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});
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// Enable the I2C processing
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self.i2c.cr1.modify(|_, w| w.pe().set_bit());
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self
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}
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pub fn release(self) -> (I2C, (SCLPIN, SDAPIN)) {
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(self.i2c, self.pins)
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}
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fn check_and_clear_error_flags(&self, isr: &crate::stm32::i2c1::isr::R) -> Result<(), Error> {
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// If we received a NACK, then this is an error
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if isr.nackf().bit_is_set() {
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self.i2c
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.icr
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.write(|w| w.stopcf().set_bit().nackcf().set_bit());
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return Err(Error::NACK);
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}
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Ok(())
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}
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fn send_byte(&self, byte: u8) -> Result<(), Error> {
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// Wait until we're ready for sending
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while {
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let isr = self.i2c.isr.read();
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self.check_and_clear_error_flags(&isr)?;
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isr.txis().bit_is_clear()
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} {}
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// Push out a byte of data
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self.i2c.txdr.write(|w| unsafe { w.bits(u32::from(byte)) });
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self.check_and_clear_error_flags(&self.i2c.isr.read())?;
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Ok(())
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}
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fn recv_byte(&self) -> Result<u8, Error> {
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while {
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let isr = self.i2c.isr.read();
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self.check_and_clear_error_flags(&isr)?;
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isr.rxne().bit_is_clear()
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} {}
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let value = self.i2c.rxdr.read().bits() as u8;
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Ok(value)
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}
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}
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#[cfg(feature = "device-selected")]
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impl<I2C, SCLPIN, SDAPIN> WriteRead for I2c<I2C, SCLPIN, SDAPIN>
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where
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I2C: Deref<Target = I2cRegisterBlock>,
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{
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type Error = Error;
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fn write_read(&mut self, addr: u8, bytes: &[u8], buffer: &mut [u8]) -> Result<(), Error> {
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// Set up current slave address for writing and disable autoending
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self.i2c.cr2.modify(|_, w| {
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w.sadd()
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.bits(u16::from(addr) << 1)
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.nbytes()
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.bits(bytes.len() as u8)
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.rd_wrn()
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.clear_bit()
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.autoend()
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.clear_bit()
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});
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// Send a START condition
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self.i2c.cr2.modify(|_, w| w.start().set_bit());
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// Wait until the transmit buffer is empty and there hasn't been any error condition
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while {
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let isr = self.i2c.isr.read();
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self.check_and_clear_error_flags(&isr)?;
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isr.txis().bit_is_clear() && isr.tc().bit_is_clear()
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} {}
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// Send out all individual bytes
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for c in bytes {
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self.send_byte(*c)?;
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}
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// Wait until data was sent
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while {
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let isr = self.i2c.isr.read();
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self.check_and_clear_error_flags(&isr)?;
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isr.tc().bit_is_clear()
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} {}
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// Set up current address for reading
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self.i2c.cr2.modify(|_, w| {
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w.sadd()
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.bits(u16::from(addr) << 1)
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.nbytes()
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.bits(buffer.len() as u8)
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.rd_wrn()
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.set_bit()
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});
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// Send another START condition
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self.i2c.cr2.modify(|_, w| w.start().set_bit());
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// Send the autoend after setting the start to get a restart
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self.i2c.cr2.modify(|_, w| w.autoend().set_bit());
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// Now read in all bytes
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for c in buffer.iter_mut() {
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*c = self.recv_byte()?;
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}
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// Check and clear flags if they somehow ended up set
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self.check_and_clear_error_flags(&self.i2c.isr.read())?;
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Ok(())
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}
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}
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#[cfg(feature = "device-selected")]
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impl<I2C, SCLPIN, SDAPIN> Write for I2c<I2C, SCLPIN, SDAPIN>
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where
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I2C: Deref<Target = I2cRegisterBlock>,
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{
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type Error = Error;
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fn write(&mut self, addr: u8, bytes: &[u8]) -> Result<(), Error> {
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// Set up current slave address for writing and enable autoending
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self.i2c.cr2.modify(|_, w| {
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w.sadd()
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.bits(u16::from(addr) << 1)
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.nbytes()
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.bits(bytes.len() as u8)
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.rd_wrn()
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.clear_bit()
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.autoend()
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.set_bit()
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});
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// Send a START condition
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self.i2c.cr2.modify(|_, w| w.start().set_bit());
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// Send out all individual bytes
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for c in bytes {
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self.send_byte(*c)?;
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}
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// Check and clear flags if they somehow ended up set
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self.check_and_clear_error_flags(&self.i2c.isr.read())?;
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Ok(())
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}
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}
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