Browse Source

create driverlib module, create project spec module

start porting UART init
pulled some more driverlib definitions
master
Marc Poulhiès 5 years ago
parent
commit
389d2f2de9
  1. 93
      layout.ld
  2. 210
      src/driverlib/gpio.rs
  3. 146
      src/driverlib/memmap.rs
  4. 4
      src/driverlib/mod.rs
  5. 224
      src/driverlib/pinmap.rs
  6. 22
      src/driverlib/sysctl.rs
  7. 180
      src/main.rs
  8. 66
      src/tiva_gpio.rs
  9. 53
      src/tiva_uart.rs

93
layout.ld

@ -1,36 +1,3 @@
/*
* Copyright (c) 2012, Mauro Scomparin
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Mauro Scomparin nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY Mauro Scomparin ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Mauro Scomparin BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* File: LM4F.ld.
* Author: Mauro Scomparin <http://scompoprojects.worpress.com>.
* Version: 1.0.0.
* Description: Linker description file for LM4FXXX microcontrollers.
*/
/*
* Memory definition:
* FLASH: start point 0x00, lenght 0x40000.
@ -44,19 +11,8 @@ MEMORY
STACK (rwx) : ORIGIN = 0x20007FFF , LENGTH = 0x00000000
}
/*
* Sections definitions:
*
* .text - machine instructions.
* .data - initialized data defined in the program.
* .bss - un-initialized global and static variables (to be initialized to 0 before starting main).
* .stack - just contains the pointer to the stack end at the right place.
*/
SECTIONS
{
/* This section it's the code, containing the NVIC Vector table that must start at 0x0
* Look at the LM4F120H5QR datasheet for details. (Table 2-8. Exception Types)
*/
.vectors 0x0 :
{
KEEP(*(.vectors))
@ -65,47 +21,32 @@ SECTIONS
.text 0x400 :
{
/*_start_text = .; /* This is an index to the beginning of .text segment. */
*(.text.*) /* This contains the code after the ISR table. */
*(.rodata.*) /* Read only data. */
_end_text = .; /* This is an index to the end of .text segment. */
_text_start = .;
*(.text.*)
*(.rodata.*)
_end_text = .;
}>FLASH
/*
* .data segment must be placed in RAM but it's originally stored in FLASH
* So I set the data segment in ram, but I specify the load address with the AT
* keyword to set that right after the .text section.
* (Look at the LD documentation. (Optional Section Attributes))
* Thanks https://github.com/utzig for the hints!
*/
.data :
{
_data_start = .; /* An index to the beginning of .data segment. */
*(.data.*) /* I should put there all my initialized data of my program. */
*(vtable) /* vtable it's generated by stellarisware to store the NVIC table in ram*/
_data_end = .; /* And another index to the end of .data segment. */
_data_start = .;
*(.data.*)
*(vtable)
_data_end = .;
}>RAM AT >FLASH
_data_load = LOADADDR(.data);
/*
* .bss contains the unitialized variables and must be set as 0x0 during runtime.
* It should be loaded in RAM and particula care should be taken initializing them in the startup file.
*/
.bss :
{
_bss_start = .; /* This is an index to the beginning of .bss segment. */
*(.bss.*) /* The un-initialized data should go there. */
*(COMMON) /* All the other stuff should be put there */
_bss_end = .; /* End index for .bss segment */
_bss_start = .;
*(.bss.*)
*(COMMON)
_bss_end = .;
}>RAM
/*
* .stack contains nothing, but I use it to set the first vector item (SP R13).
*/
.stack :
{
_stack_top = .; /* An index to the end of the stack */
}>STACK
_data_load = LOADADDR(.data);
.stack :
{
_stack_top = .;
}>STACK
}

210
src/driverlib/gpio.rs

@ -0,0 +1,210 @@
//*****************************************************************************
//
// hw_gpio.h - Defines and Macros for GPIO hardware.
//
// Copyright (c) 2005-2014 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
//
//*****************************************************************************
//*****************************************************************************
//
// The following are defines for the GPIO register offsets.
//
//*****************************************************************************
pub const GPIO_O_DATA :u32 = 0x00000000; // GPIO Data
pub const GPIO_O_DIR :u32 = 0x00000400; // GPIO Direction
pub const GPIO_O_IS :u32 = 0x00000404; // GPIO Interrupt Sense
pub const GPIO_O_IBE :u32 = 0x00000408; // GPIO Interrupt Both Edges
pub const GPIO_O_IEV :u32 = 0x0000040C; // GPIO Interrupt Event
pub const GPIO_O_IM :u32 = 0x00000410; // GPIO Interrupt Mask
pub const GPIO_O_RIS :u32 = 0x00000414; // GPIO Raw Interrupt Status
pub const GPIO_O_MIS :u32 = 0x00000418; // GPIO Masked Interrupt Status
pub const GPIO_O_ICR :u32 = 0x0000041C; // GPIO Interrupt Clear
pub const GPIO_O_AFSEL :u32 = 0x00000420; // GPIO Alternate Function Select
pub const GPIO_O_DR2R :u32 = 0x00000500; // GPIO 2-mA Drive Select
pub const GPIO_O_DR4R :u32 = 0x00000504; // GPIO 4-mA Drive Select
pub const GPIO_O_DR8R :u32 = 0x00000508; // GPIO 8-mA Drive Select
pub const GPIO_O_ODR :u32 = 0x0000050C; // GPIO Open Drain Select
pub const GPIO_O_PUR :u32 = 0x00000510; // GPIO Pull-Up Select
pub const GPIO_O_PDR :u32 = 0x00000514; // GPIO Pull-Down Select
pub const GPIO_O_SLR :u32 = 0x00000518; // GPIO Slew Rate Control Select
pub const GPIO_O_DEN :u32 = 0x0000051C; // GPIO Digital Enable
pub const GPIO_O_LOCK :u32 = 0x00000520; // GPIO Lock
pub const GPIO_O_CR :u32 = 0x00000524; // GPIO Commit
pub const GPIO_O_AMSEL :u32 = 0x00000528; // GPIO Analog Mode Select
pub const GPIO_O_PCTL :u32 = 0x0000052C; // GPIO Port Control
pub const GPIO_O_ADCCTL :u32 = 0x00000530; // GPIO ADC Control
pub const GPIO_O_DMACTL :u32 = 0x00000534; // GPIO DMA Control
pub const GPIO_O_SI :u32 = 0x00000538; // GPIO Select Interrupt
pub const GPIO_O_DR12R :u32 = 0x0000053C; // GPIO 12-mA Drive Select
pub const GPIO_O_WAKEPEN :u32 = 0x00000540; // GPIO Wake Pin Enable
pub const GPIO_O_WAKELVL :u32 = 0x00000544; // GPIO Wake Level
pub const GPIO_O_WAKESTAT :u32 = 0x00000548; // GPIO Wake Status
pub const GPIO_O_PP :u32 = 0x00000FC0; // GPIO Peripheral Property
pub const GPIO_O_PC :u32 = 0x00000FC4; // GPIO Peripheral Configuration
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_O_IM register.
//
//*****************************************************************************
pub const GPIO_IM_DMAIME :u32 = 0x00000100; // GPIO uDMA Done Interrupt Mask
// Enable
pub const GPIO_IM_GPIO_M :u32 = 0x000000FF; // GPIO Interrupt Mask Enable
pub const GPIO_IM_GPIO_S :u32 = 0;
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_O_RIS register.
//
//*****************************************************************************
pub const GPIO_RIS_DMARIS :u32 = 0x00000100; // GPIO uDMA Done Interrupt Raw
// Status
pub const GPIO_RIS_GPIO_M :u32 = 0x000000FF; // GPIO Interrupt Raw Status
pub const GPIO_RIS_GPIO_S :u32 = 0;
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_O_MIS register.
//
//*****************************************************************************
pub const GPIO_MIS_DMAMIS :u32 = 0x00000100; // GPIO uDMA Done Masked Interrupt
// Status
pub const GPIO_MIS_GPIO_M :u32 = 0x000000FF; // GPIO Masked Interrupt Status
pub const GPIO_MIS_GPIO_S :u32 = 0;
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_O_ICR register.
//
//*****************************************************************************
pub const GPIO_ICR_DMAIC :u32 = 0x00000100; // GPIO uDMA Interrupt Clear
pub const GPIO_ICR_GPIO_M :u32 = 0x000000FF; // GPIO Interrupt Clear
pub const GPIO_ICR_GPIO_S :u32 = 0;
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_O_LOCK register.
//
//*****************************************************************************
pub const GPIO_LOCK_M :u32 = 0xFFFFFFFF; // GPIO Lock
pub const GPIO_LOCK_UNLOCKED :u32 = 0x00000000; // The GPIOCR register is unlocked
// and may be modified
pub const GPIO_LOCK_LOCKED :u32 = 0x00000001; // The GPIOCR register is locked
// and may not be modified
pub const GPIO_LOCK_KEY :u32 = 0x4C4F434B; // Unlocks the GPIO_CR register
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_O_SI register.
//
//*****************************************************************************
pub const GPIO_SI_SUM :u32 = 0x00000001; // Summary Interrupt
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_O_DR12R register.
//
//*****************************************************************************
pub const GPIO_DR12R_DRV12_M :u32 = 0x000000FF; // Output Pad 12-mA Drive Enable
pub const GPIO_DR12R_DRV12_12MA :u32 = 0x00000001; // The corresponding GPIO pin has
// 12-mA drive. This encoding is
// only valid if the GPIOPP EDE bit
// is set and the appropriate
// GPIOPC EDM bit field is
// programmed to 0x3
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_O_WAKEPEN register.
//
//*****************************************************************************
pub const GPIO_WAKEPEN_WAKEP4 :u32 = 0x00000010; // P[4] Wake Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_O_WAKELVL register.
//
//*****************************************************************************
pub const GPIO_WAKELVL_WAKELVL4 :u32 = 0x00000010; // P[4] Wake Level
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_O_WAKESTAT
// register.
//
//*****************************************************************************
pub const GPIO_WAKESTAT_STAT4 :u32 = 0x00000010; // P[4] Wake Status
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_O_PP register.
//
//*****************************************************************************
pub const GPIO_PP_EDE :u32 = 0x00000001; // Extended Drive Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_O_PC register.
//
//*****************************************************************************
pub const GPIO_PC_EDM7_M :u32 = 0x0000C000; // Extended Drive Mode Bit 7
pub const GPIO_PC_EDM6_M :u32 = 0x00003000; // Extended Drive Mode Bit 6
pub const GPIO_PC_EDM5_M :u32 = 0x00000C00; // Extended Drive Mode Bit 5
pub const GPIO_PC_EDM4_M :u32 = 0x00000300; // Extended Drive Mode Bit 4
pub const GPIO_PC_EDM3_M :u32 = 0x000000C0; // Extended Drive Mode Bit 3
pub const GPIO_PC_EDM2_M :u32 = 0x00000030; // Extended Drive Mode Bit 2
pub const GPIO_PC_EDM1_M :u32 = 0x0000000C; // Extended Drive Mode Bit 1
pub const GPIO_PC_EDM0_M :u32 = 0x00000003; // Extended Drive Mode Bit 0
pub const GPIO_PC_EDM0_DISABLE :u32 = 0x00000000; // Drive values of 2, 4 and 8 mA
// are maintained. GPIO n Drive
// Select (GPIODRnR) registers
// function as normal
pub const GPIO_PC_EDM0_6MA :u32 = 0x00000001; // An additional 6 mA option is
// provided
pub const GPIO_PC_EDM0_PLUS2MA :u32 = 0x00000003; // A 2 mA driver is always enabled;
// setting the corresponding
// GPIODR4R register bit adds 2 mA
// and setting the corresponding
// GPIODR8R of GPIODR12R register
// bit adds an additional 4 mA
pub const GPIO_PC_EDM7_S :u32 = 14;
pub const GPIO_PC_EDM6_S :u32 = 12;
pub const GPIO_PC_EDM5_S :u32 = 10;
pub const GPIO_PC_EDM4_S :u32 = 8;
pub const GPIO_PC_EDM3_S :u32 = 6;
pub const GPIO_PC_EDM2_S :u32 = 4;
pub const GPIO_PC_EDM1_S :u32 = 2;

146
src/driverlib/memmap.rs

@ -0,0 +1,146 @@
//*****************************************************************************
//
// hw_memmap.h - Macros defining the memory map of the device.
//
// Copyright (c) 2005-2014 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
//
//*****************************************************************************
//*****************************************************************************
//
// The following are defines for the base address of the memories and
// peripherals.
//
//*****************************************************************************
pub const FLASH_BASE :u32 = 0x00000000; // FLASH memory
pub const SRAM_BASE :u32 = 0x20000000; // SRAM memory
pub const WATCHDOG0_BASE :u32 = 0x40000000; // Watchdog0
pub const WATCHDOG1_BASE :u32 = 0x40001000; // Watchdog1
pub const GPIO_PORTA_BASE :u32 = 0x40004000; // GPIO Port A
pub const GPIO_PORTB_BASE :u32 = 0x40005000; // GPIO Port B
pub const GPIO_PORTC_BASE :u32 = 0x40006000; // GPIO Port C
pub const GPIO_PORTD_BASE :u32 = 0x40007000; // GPIO Port D
pub const SSI0_BASE :u32 = 0x40008000; // SSI0
pub const SSI1_BASE :u32 = 0x40009000; // SSI1
pub const SSI2_BASE :u32 = 0x4000A000; // SSI2
pub const SSI3_BASE :u32 = 0x4000B000; // SSI3
pub const UART0_BASE :u32 = 0x4000C000; // UART0
pub const UART1_BASE :u32 = 0x4000D000; // UART1
pub const UART2_BASE :u32 = 0x4000E000; // UART2
pub const UART3_BASE :u32 = 0x4000F000; // UART3
pub const UART4_BASE :u32 = 0x40010000; // UART4
pub const UART5_BASE :u32 = 0x40011000; // UART5
pub const UART6_BASE :u32 = 0x40012000; // UART6
pub const UART7_BASE :u32 = 0x40013000; // UART7
pub const I2C0_BASE :u32 = 0x40020000; // I2C0
pub const I2C1_BASE :u32 = 0x40021000; // I2C1
pub const I2C2_BASE :u32 = 0x40022000; // I2C2
pub const I2C3_BASE :u32 = 0x40023000; // I2C3
pub const GPIO_PORTE_BASE :u32 = 0x40024000; // GPIO Port E
pub const GPIO_PORTF_BASE :u32 = 0x40025000; // GPIO Port F
pub const GPIO_PORTG_BASE :u32 = 0x40026000; // GPIO Port G
pub const GPIO_PORTH_BASE :u32 = 0x40027000; // GPIO Port H
pub const PWM0_BASE :u32 = 0x40028000; // Pulse Width Modulator (PWM)
pub const PWM1_BASE :u32 = 0x40029000; // Pulse Width Modulator (PWM)
pub const QEI0_BASE :u32 = 0x4002C000; // QEI0
pub const QEI1_BASE :u32 = 0x4002D000; // QEI1
pub const TIMER0_BASE :u32 = 0x40030000; // Timer0
pub const TIMER1_BASE :u32 = 0x40031000; // Timer1
pub const TIMER2_BASE :u32 = 0x40032000; // Timer2
pub const TIMER3_BASE :u32 = 0x40033000; // Timer3
pub const TIMER4_BASE :u32 = 0x40034000; // Timer4
pub const TIMER5_BASE :u32 = 0x40035000; // Timer5
pub const WTIMER0_BASE :u32 = 0x40036000; // Wide Timer0
pub const WTIMER1_BASE :u32 = 0x40037000; // Wide Timer1
pub const ADC0_BASE :u32 = 0x40038000; // ADC0
pub const ADC1_BASE :u32 = 0x40039000; // ADC1
pub const COMP_BASE :u32 = 0x4003C000; // Analog comparators
pub const GPIO_PORTJ_BASE :u32 = 0x4003D000; // GPIO Port J
pub const CAN0_BASE :u32 = 0x40040000; // CAN0
pub const CAN1_BASE :u32 = 0x40041000; // CAN1
pub const WTIMER2_BASE :u32 = 0x4004C000; // Wide Timer2
pub const WTIMER3_BASE :u32 = 0x4004D000; // Wide Timer3
pub const WTIMER4_BASE :u32 = 0x4004E000; // Wide Timer4
pub const WTIMER5_BASE :u32 = 0x4004F000; // Wide Timer5
pub const USB0_BASE :u32 = 0x40050000; // USB 0 Controller
pub const GPIO_PORTA_AHB_BASE :u32 = 0x40058000; // GPIO Port A (high speed)
pub const GPIO_PORTB_AHB_BASE :u32 = 0x40059000; // GPIO Port B (high speed)
pub const GPIO_PORTC_AHB_BASE :u32 = 0x4005A000; // GPIO Port C (high speed)
pub const GPIO_PORTD_AHB_BASE :u32 = 0x4005B000; // GPIO Port D (high speed)
pub const GPIO_PORTE_AHB_BASE :u32 = 0x4005C000; // GPIO Port E (high speed)
pub const GPIO_PORTF_AHB_BASE :u32 = 0x4005D000; // GPIO Port F (high speed)
pub const GPIO_PORTG_AHB_BASE :u32 = 0x4005E000; // GPIO Port G (high speed)
pub const GPIO_PORTH_AHB_BASE :u32 = 0x4005F000; // GPIO Port H (high speed)
pub const GPIO_PORTJ_AHB_BASE :u32 = 0x40060000; // GPIO Port J (high speed)
pub const GPIO_PORTK_BASE :u32 = 0x40061000; // GPIO Port K
pub const GPIO_PORTL_BASE :u32 = 0x40062000; // GPIO Port L
pub const GPIO_PORTM_BASE :u32 = 0x40063000; // GPIO Port M
pub const GPIO_PORTN_BASE :u32 = 0x40064000; // GPIO Port N
pub const GPIO_PORTP_BASE :u32 = 0x40065000; // GPIO Port P
pub const GPIO_PORTQ_BASE :u32 = 0x40066000; // GPIO Port Q
pub const GPIO_PORTR_BASE :u32 = 0x40067000; // General-Purpose Input/Outputs
// (GPIOs)
pub const GPIO_PORTS_BASE :u32 = 0x40068000; // General-Purpose Input/Outputs
// (GPIOs)
pub const GPIO_PORTT_BASE :u32 = 0x40069000; // General-Purpose Input/Outputs
// (GPIOs)
pub const EEPROM_BASE :u32 = 0x400AF000; // EEPROM memory
pub const ONEWIRE0_BASE :u32 = 0x400B6000; // 1-Wire Master Module
pub const I2C8_BASE :u32 = 0x400B8000; // I2C8
pub const I2C9_BASE :u32 = 0x400B9000; // I2C9
pub const I2C4_BASE :u32 = 0x400C0000; // I2C4
pub const I2C5_BASE :u32 = 0x400C1000; // I2C5
pub const I2C6_BASE :u32 = 0x400C2000; // I2C6
pub const I2C7_BASE :u32 = 0x400C3000; // I2C7
pub const EPI0_BASE :u32 = 0x400D0000; // EPI0
pub const TIMER6_BASE :u32 = 0x400E0000; // General-Purpose Timers
pub const TIMER7_BASE :u32 = 0x400E1000; // General-Purpose Timers
pub const EMAC0_BASE :u32 = 0x400EC000; // Ethernet Controller
pub const SYSEXC_BASE :u32 = 0x400F9000; // System Exception Module
pub const HIB_BASE :u32 = 0x400FC000; // Hibernation Module
pub const FLASH_CTRL_BASE :u32 = 0x400FD000; // FLASH Controller
pub const SYSCTL_BASE :u32 = 0x400FE000; // System Control
pub const UDMA_BASE :u32 = 0x400FF000; // uDMA Controller
pub const CCM0_BASE :u32 = 0x44030000; // Cyclical Redundancy Check (CRC)
pub const SHAMD5_BASE :u32 = 0x44034000; // SHA/MD5 Accelerator
pub const AES_BASE :u32 = 0x44036000; // Advance Encryption
// Hardware-Accelerated Module
pub const DES_BASE :u32 = 0x44038000; // Data Encryption Standard
// Accelerator (DES)
pub const LCD0_BASE :u32 = 0x44050000; // LCD Controller
pub const ITM_BASE :u32 = 0xE0000000; // Instrumentation Trace Macrocell
pub const DWT_BASE :u32 = 0xE0001000; // Data Watchpoint and Trace
pub const FPB_BASE :u32 = 0xE0002000; // FLASH Patch and Breakpoint
pub const NVIC_BASE :u32 = 0xE000E000; // Nested Vectored Interrupt Ctrl
pub const TPIU_BASE :u32 = 0xE0040000; // Trace Port Interface Unit

4
src/driverlib/mod.rs

@ -0,0 +1,4 @@
pub mod sysctl;
pub mod pinmap;
pub mod memmap;
pub mod gpio;

224
src/driverlib/pinmap.rs

@ -0,0 +1,224 @@
//*****************************************************************************
//
// pin_map.h - Mapping of peripherals to pins for all parts.
//
// Copyright (c) 2007-2014 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
//
//*****************************************************************************
//*****************************************************************************
//
// TM4C123GH6PM Port/Pin Mapping Definitions
//
//*****************************************************************************
pub const GPIO_PA0_U0RX :u32 = 0x00000001;
pub const GPIO_PA0_CAN1RX :u32 = 0x00000008;
pub const GPIO_PA1_U0TX :u32 = 0x00000401;
pub const GPIO_PA1_CAN1TX :u32 = 0x00000408;
pub const GPIO_PA2_SSI0CLK :u32 = 0x00000802;
pub const GPIO_PA3_SSI0FSS :u32 = 0x00000C02;
pub const GPIO_PA4_SSI0RX :u32 = 0x00001002;
pub const GPIO_PA5_SSI0TX :u32 = 0x00001402;
pub const GPIO_PA6_I2C1SCL :u32 = 0x00001803;
pub const GPIO_PA6_M1PWM2 :u32 = 0x00001805;
pub const GPIO_PA7_I2C1SDA :u32 = 0x00001C03;
pub const GPIO_PA7_M1PWM3 :u32 = 0x00001C05;
pub const GPIO_PB0_U1RX :u32 = 0x00010001;
pub const GPIO_PB0_T2CCP0 :u32 = 0x00010007;
pub const GPIO_PB1_U1TX :u32 = 0x00010401;
pub const GPIO_PB1_T2CCP1 :u32 = 0x00010407;
pub const GPIO_PB2_I2C0SCL :u32 = 0x00010803;
pub const GPIO_PB2_T3CCP0 :u32 = 0x00010807;
pub const GPIO_PB3_I2C0SDA :u32 = 0x00010C03;
pub const GPIO_PB3_T3CCP1 :u32 = 0x00010C07;
pub const GPIO_PB4_SSI2CLK :u32 = 0x00011002;
pub const GPIO_PB4_M0PWM2 :u32 = 0x00011004;
pub const GPIO_PB4_T1CCP0 :u32 = 0x00011007;
pub const GPIO_PB4_CAN0RX :u32 = 0x00011008;
pub const GPIO_PB5_SSI2FSS :u32 = 0x00011402;
pub const GPIO_PB5_M0PWM3 :u32 = 0x00011404;
pub const GPIO_PB5_T1CCP1 :u32 = 0x00011407;
pub const GPIO_PB5_CAN0TX :u32 = 0x00011408;
pub const GPIO_PB6_SSI2RX :u32 = 0x00011802;
pub const GPIO_PB6_M0PWM0 :u32 = 0x00011804;
pub const GPIO_PB6_T0CCP0 :u32 = 0x00011807;
pub const GPIO_PB7_SSI2TX :u32 = 0x00011C02;
pub const GPIO_PB7_M0PWM1 :u32 = 0x00011C04;
pub const GPIO_PB7_T0CCP1 :u32 = 0x00011C07;
pub const GPIO_PC0_TCK :u32 = 0x00020001;
pub const GPIO_PC0_SWCLK :u32 = 0x00020001;
pub const GPIO_PC0_T4CCP0 :u32 = 0x00020007;
pub const GPIO_PC1_TMS :u32 = 0x00020401;
pub const GPIO_PC1_SWDIO :u32 = 0x00020401;
pub const GPIO_PC1_T4CCP1 :u32 = 0x00020407;
pub const GPIO_PC2_TDI :u32 = 0x00020801;
pub const GPIO_PC2_T5CCP0 :u32 = 0x00020807;
pub const GPIO_PC3_SWO :u32 = 0x00020C01;
pub const GPIO_PC3_TDO :u32 = 0x00020C01;
pub const GPIO_PC3_T5CCP1 :u32 = 0x00020C07;
pub const GPIO_PC4_U4RX :u32 = 0x00021001;
pub const GPIO_PC4_U1RX :u32 = 0x00021002;
pub const GPIO_PC4_M0PWM6 :u32 = 0x00021004;
pub const GPIO_PC4_IDX1 :u32 = 0x00021006;
pub const GPIO_PC4_WT0CCP0 :u32 = 0x00021007;
pub const GPIO_PC4_U1RTS :u32 = 0x00021008;
pub const GPIO_PC5_U4TX :u32 = 0x00021401;
pub const GPIO_PC5_U1TX :u32 = 0x00021402;
pub const GPIO_PC5_M0PWM7 :u32 = 0x00021404;
pub const GPIO_PC5_PHA1 :u32 = 0x00021406;
pub const GPIO_PC5_WT0CCP1 :u32 = 0x00021407;
pub const GPIO_PC5_U1CTS :u32 = 0x00021408;
pub const GPIO_PC6_U3RX :u32 = 0x00021801;
pub const GPIO_PC6_PHB1 :u32 = 0x00021806;
pub const GPIO_PC6_WT1CCP0 :u32 = 0x00021807;
pub const GPIO_PC6_USB0EPEN :u32 = 0x00021808;
pub const GPIO_PC7_U3TX :u32 = 0x00021C01;
pub const GPIO_PC7_WT1CCP1 :u32 = 0x00021C07;
pub const GPIO_PC7_USB0PFLT :u32 = 0x00021C08;
pub const GPIO_PD0_SSI3CLK :u32 = 0x00030001;
pub const GPIO_PD0_SSI1CLK :u32 = 0x00030002;
pub const GPIO_PD0_I2C3SCL :u32 = 0x00030003;
pub const GPIO_PD0_M0PWM6 :u32 = 0x00030004;
pub const GPIO_PD0_M1PWM0 :u32 = 0x00030005;
pub const GPIO_PD0_WT2CCP0 :u32 = 0x00030007;
pub const GPIO_PD1_SSI3FSS :u32 = 0x00030401;
pub const GPIO_PD1_SSI1FSS :u32 = 0x00030402;
pub const GPIO_PD1_I2C3SDA :u32 = 0x00030403;
pub const GPIO_PD1_M0PWM7 :u32 = 0x00030404;
pub const GPIO_PD1_M1PWM1 :u32 = 0x00030405;
pub const GPIO_PD1_WT2CCP1 :u32 = 0x00030407;
pub const GPIO_PD2_SSI3RX :u32 = 0x00030801;
pub const GPIO_PD2_SSI1RX :u32 = 0x00030802;
pub const GPIO_PD2_M0FAULT0 :u32 = 0x00030804;
pub const GPIO_PD2_WT3CCP0 :u32 = 0x00030807;
pub const GPIO_PD2_USB0EPEN :u32 = 0x00030808;
pub const GPIO_PD3_SSI3TX :u32 = 0x00030C01;
pub const GPIO_PD3_SSI1TX :u32 = 0x00030C02;
pub const GPIO_PD3_IDX0 :u32 = 0x00030C06;
pub const GPIO_PD3_WT3CCP1 :u32 = 0x00030C07;
pub const GPIO_PD3_USB0PFLT :u32 = 0x00030C08;
pub const GPIO_PD4_U6RX :u32 = 0x00031001;
pub const GPIO_PD4_WT4CCP0 :u32 = 0x00031007;
pub const GPIO_PD5_U6TX :u32 = 0x00031401;
pub const GPIO_PD5_WT4CCP1 :u32 = 0x00031407;
pub const GPIO_PD6_U2RX :u32 = 0x00031801;
pub const GPIO_PD6_M0FAULT0 :u32 = 0x00031804;
pub const GPIO_PD6_PHA0 :u32 = 0x00031806;
pub const GPIO_PD6_WT5CCP0 :u32 = 0x00031807;
pub const GPIO_PD7_U2TX :u32 = 0x00031C01;
pub const GPIO_PD7_PHB0 :u32 = 0x00031C06;
pub const GPIO_PD7_WT5CCP1 :u32 = 0x00031C07;
pub const GPIO_PD7_NMI :u32 = 0x00031C08;
pub const GPIO_PE0_U7RX :u32 = 0x00040001;
pub const GPIO_PE1_U7TX :u32 = 0x00040401;
pub const GPIO_PE4_U5RX :u32 = 0x00041001;
pub const GPIO_PE4_I2C2SCL :u32 = 0x00041003;
pub const GPIO_PE4_M0PWM4 :u32 = 0x00041004;
pub const GPIO_PE4_M1PWM2 :u32 = 0x00041005;
pub const GPIO_PE4_CAN0RX :u32 = 0x00041008;
pub const GPIO_PE5_U5TX :u32 = 0x00041401;
pub const GPIO_PE5_I2C2SDA :u32 = 0x00041403;
pub const GPIO_PE5_M0PWM5 :u32 = 0x00041404;
pub const GPIO_PE5_M1PWM3 :u32 = 0x00041405;
pub const GPIO_PE5_CAN0TX :u32 = 0x00041408;
pub const GPIO_PF0_U1RTS :u32 = 0x00050001;
pub const GPIO_PF0_SSI1RX :u32 = 0x00050002;
pub const GPIO_PF0_CAN0RX :u32 = 0x00050003;
pub const GPIO_PF0_M1PWM4 :u32 = 0x00050005;
pub const GPIO_PF0_PHA0 :u32 = 0x00050006;
pub const GPIO_PF0_T0CCP0 :u32 = 0x00050007;
pub const GPIO_PF0_NMI :u32 = 0x00050008;
pub const GPIO_PF0_C0O :u32 = 0x00050009;
pub const GPIO_PF1_U1CTS :u32 = 0x00050401;
pub const GPIO_PF1_SSI1TX :u32 = 0x00050402;
pub const GPIO_PF1_M1PWM5 :u32 = 0x00050405;
pub const GPIO_PF1_PHB0 :u32 = 0x00050406;
pub const GPIO_PF1_T0CCP1 :u32 = 0x00050407;
pub const GPIO_PF1_C1O :u32 = 0x00050409;
pub const GPIO_PF1_TRD1 :u32 = 0x0005040E;
pub const GPIO_PF2_SSI1CLK :u32 = 0x00050802;
pub const GPIO_PF2_M0FAULT0 :u32 = 0x00050804;
pub const GPIO_PF2_M1PWM6 :u32 = 0x00050805;
pub const GPIO_PF2_T1CCP0 :u32 = 0x00050807;
pub const GPIO_PF2_TRD0 :u32 = 0x0005080E;
pub const GPIO_PF3_SSI1FSS :u32 = 0x00050C02;
pub const GPIO_PF3_CAN0TX :u32 = 0x00050C03;
pub const GPIO_PF3_M1PWM7 :u32 = 0x00050C05;
pub const GPIO_PF3_T1CCP1 :u32 = 0x00050C07;
pub const GPIO_PF3_TRCLK :u32 = 0x00050C0E;
pub const GPIO_PF4_M1FAULT0 :u32 = 0x00051005;
pub const GPIO_PF4_IDX0 :u32 = 0x00051006;
pub const GPIO_PF4_T2CCP0 :u32 = 0x00051007;
pub const GPIO_PF4_USB0EPEN :u32 = 0x00051008;

22
src/tiva_sysctl.rs → src/driverlib/sysctl.rs

@ -4111,6 +4111,22 @@ pub const SYSCTL_ALTCLK_LFIOSC : u32 = 0x00000004;
//
//*****************************************************************************
//*****************************************************************************
//
// The base addresses of the various peripheral control registers.
//
//*****************************************************************************
pub const SYSCTL_PPBASE :u32 = 0x400fe300;
pub const SYSCTL_SRBASE :u32 = 0x400fe500;
pub const SYSCTL_RCGCBASE :u32 = 0x400fe600;
pub const SYSCTL_SCGCBASE :u32 = 0x400fe700;
pub const SYSCTL_DCGCBASE :u32 = 0x400fe800;
pub const SYSCTL_PCBASE :u32 = 0x400fe900;
pub const SYSCTL_PRBASE :u32 = 0x400fea00;
pub unsafe fn cpu_clock_init(clock: u32) {
let mut ui32Delay;
let ui32Config : u32 = match(clock) {
@ -4189,8 +4205,6 @@ pub unsafe fn cpu_clock_init(clock: u32) {
return;
}
}
//
// Set the new crystal value and oscillator source. Because the OSCSRC2
@ -4292,3 +4306,7 @@ pub unsafe fn cpu_clock_init(clock: u32) {
//
// SysCtlDelay(16);
}
pub unsafe fn sys_ctl_peripheral_enable(periph_id : u32) {
write_bitband!((SYSCTL_RCGCBASE + ((periph_id & 0xff00) >> 8)),(periph_id & 0xff),1);
}

180
src/main.rs

@ -38,54 +38,28 @@ mod lowlevel {
}
}
mod tiva_sysctl;
const SYSCTL_BASE: u32 = 0x400F_E000;
const SYSCTL_RCGCGPIO_BASE: u32 = SYSCTL_BASE + 0x608;
const SYSCTL_GPIOHBCTL_BASE: u32 = SYSCTL_BASE + 0x06c;
const SYSCTL_RCC: u32 = SYSCTL_BASE + 0x60;
const SYSCTL_RCC2: u32 = SYSCTL_BASE + 0x70;
const SYSCTL_RCGBASE: u32 = 0x400fe600;
const SYSCTL_PERIPH_GPIOF: u32 = 0xf0000805;
const GPIO_LOCK_KEY: u32 = 0x4C4F434B;
const GPIO_LOCK_R_OFF: u32 = 0x520;
const GPIO_CR_R_OFF: u32 = 0x524;
const GPIO_DEN_R_OFF: u32 = 0x51c;
const GPIO_DIR_R_OFF: u32 = 0x400;
const GPIO_DATA_R_OFF: u32 = 0x000;
const GPIO_O_DR2R_OFF: u32 = 0x500;
const GPIO_O_DR4R_OFF: u32 = 0x504;
const GPIO_O_DR8R_OFF: u32 = 0x508;
const GPIO_O_SLR_OFF: u32 = 0x518;
// const GPIO_PORTF_BASE: u32 = 0x40025000; // GPIO Port F APB (old)
const GPIO_PORTF_BASE: u32 = 0x4005D000; // GPIO Port F AHB
enum TivaSysCtlSysDiv {
SysDiv1 = 0x0,
SysDiv2 = 0x1,
SysDiv3 = 0x2,
SysDiv4 = 0x3,
SysDiv5 = 0x4,
SysDiv6 = 0x5,
SysDiv7 = 0x6,
SysDiv8 = 0x7,
SysDiv9 = 0x8,
SysDiv10 = 0x9,
SysDiv11 = 0xA,
SysDiv12 = 0xB,
SysDiv13 = 0xC,
SysDiv14 = 0xD,
SysDiv15 = 0xE,
SysDiv16 = 0xF,
}
mod driverlib;
mod tiva_uart;
mod tiva_gpio;
// enum TivaSysCtlSysDiv {
// SysDiv1 = 0x0,
// SysDiv2 = 0x1,
// SysDiv3 = 0x2,
// SysDiv4 = 0x3,
// SysDiv5 = 0x4,
// SysDiv6 = 0x5,
// SysDiv7 = 0x6,
// SysDiv8 = 0x7,
// SysDiv9 = 0x8,
// SysDiv10 = 0x9,
// SysDiv11 = 0xA,
// SysDiv12 = 0xB,
// SysDiv13 = 0xC,
// SysDiv14 = 0xD,
// SysDiv15 = 0xE,
// SysDiv16 = 0xF,
// }
// const SYSCTL_RCC_BYPASS: u32 = 0x0000_0800; // PLL Bypass
// const SYSCTL_RCC2_BYPASS2: u32 = 0x0000_0800; // PLL Bypass 2
@ -99,80 +73,12 @@ enum TivaSysCtlSysDiv {
// const SYSCTL_RIS: u32 = 0x400FE050; // Raw Interrupt Status
pub unsafe fn sys_ctl_peripheral_enable(periph_id : u32) {
write_bitband!((SYSCTL_RCGBASE + ((periph_id & 0xff00) >> 8)),(periph_id & 0xff),1);
}
#[no_mangle]
pub unsafe fn __aeabi_unwind_cpp_pr0() -> ()
{
loop {}
}
struct TivaGpio {
sysctl_idx : u32,
base_addr : u32,
use_hpb : bool,
}
enum TivaGpioMode {
GpioIn,
GpioInPd,
GpioInPu,
GpioOut,
GpioOD,
GpioODPu,
}
impl TivaGpio {
unsafe fn init(&self) {
// bit-band access
write_bitband!(SYSCTL_RCGCGPIO_BASE, self.sysctl_idx, 1);
// Use HPB instead of APB
write_bitband!(SYSCTL_GPIOHBCTL_BASE, self.sysctl_idx, 1);
}
unsafe fn init_pin(&self, pin:u8, mode : TivaGpioMode){
match mode {
GpioOut => {
write_bitband!(GPIO_PORTF_BASE + GPIO_DEN_R_OFF, pin, 1);
write_bitband!(GPIO_PORTF_BASE + GPIO_DIR_R_OFF, pin, 1);
},
_ => {
},
}
}
unsafe fn write_pin(&self, pin:u8, val:u8){
hwreg!(self.base_addr + GPIO_DATA_R_OFF | (1<<(pin + 2)),
u32,
if val != 0 {1<<pin} else {0}
);
}
unsafe fn write_pins(&self, pin_mask:u8, val:u8){
hwreg!(self.base_addr + GPIO_DATA_R_OFF | ((pin_mask as u32)<<2),
u32,
val as u32
);
}
unsafe fn read_pin(&self, pin:u8) -> u8 {
return hwreg!(self.base_addr + GPIO_DATA_R_OFF | (1<<(pin + 2)),
u32
) as u8;
}
unsafe fn read_pins(&self, pin_mask:u8)-> u8 {
return hwreg!(self.base_addr + GPIO_DATA_R_OFF | ((pin_mask as u32)<<2),
u32
) as u8;
}
}
extern {
static mut _data_start : u32;
static mut _data_end : u32;
@ -181,14 +87,12 @@ extern {
static mut _bss_end : u32;
}
static mut SOME_STATIC_DATA: u32 = 0xdeadbeef;
static SOME_STATIC_STRING: &'static str = "A static string";
pub unsafe fn relocate(){
let mut load_addr : *mut u32 = &mut _data_load;
let mut dest_addr : *mut u32 = &mut _data_start;
let mut dest_addr_end : *mut u32 = &mut _data_end;
let dest_addr_end : *mut u32 = &mut _data_end;
while dest_addr < dest_addr_end {
*dest_addr = *load_addr;
@ -206,53 +110,31 @@ pub unsafe fn relocate(){
#[no_mangle]
pub extern fn main() {
// const RCGCGPIO: *mut u32 = (0x400FE000 + 0x608) as *mut u32;
// const RCGCGPIO_PORTA: u32 = 0x1;
// const RCGCGPIO_PORTB: u32 = 0x1<<1;
// const RCGCGPIO_PORTC: u32 = 0x1<<2;
// const RCGCGPIO_PORTD: u32 = 0x1<<3;
// const RCGCGPIO_PORTE: u32 = 0x1<<4;
// const RCGCGPIO_PORTF: u32 = 0x1<<5;
// const GPIO_PORT_A: *mut u32 = (0x40058000) as *mut u32;
// const GPIO_PORT_B: *mut u32 = (0x40059000) as *mut u32;
// const GPIO_PORT_C: *mut u32 = (0x4005A000) as *mut u32;
// const GPIO_PORT_D: *mut u32 = (0x4005B000) as *mut u32;
// const GPIO_PORT_E: *mut u32 = (0x4005C000) as *mut u32;
// const GPIO_PORT_F: u32 = 0x4005D000;
// const GPIO_PORT_F_GPIODATA: *mut u32 = (GPIO_PORT_F) as *mut u32;
// const GPIO_PORT_F_GPIODIR: *mut u32 = (GPIO_PORT_F + 0x400) as *mut u32;
// const GPIO_PORT_F_GPIOIS: *mut u32 = (GPIO_PORT_F + 0x404) as *mut u32;
// const GPIO_PORT_F_GPIODEN: *mut u32 = (GPIO_PORT_F + 0x51C) as *mut u32;
unsafe {
tiva_sysctl::cpu_clock_init(80);
driverlib::sysctl::cpu_clock_init(80);
SOME_STATIC_DATA = 0xbeefdead;
relocate();
let gpio_f = TivaGpio {
let gpio_f = tiva_gpio::TivaGpio {
sysctl_idx:5,
base_addr:GPIO_PORTF_BASE,
base_addr: driverlib::memmap::GPIO_PORTF_AHB_BASE,
use_hpb:true
};
gpio_f.init();
gpio_f.init_pin(1, TivaGpioMode::GpioOut);
gpio_f.init_pin(2, TivaGpioMode::GpioOut);
gpio_f.init_pin(3, TivaGpioMode::GpioOut);
gpio_f.init_pin(1, tiva_gpio::TivaGpioMode::GpioOut);
gpio_f.init_pin(2, tiva_gpio::TivaGpioMode::GpioOut);
gpio_f.init_pin(3, tiva_gpio::TivaGpioMode::GpioOut);
// gpio_f.write_pin(1,1);
// gpio_f.write_pin(2,1);
// gpio_f.write_pin(3,1);
gpio_f.write_pins(0xC,0xC);
gpio_f.write_pins(0xC, 0xC);
loop{};

66
src/tiva_gpio.rs

@ -0,0 +1,66 @@
use driverlib::sysctl;
use driverlib::gpio;
use driverlib::memmap;
use core::ptr;
pub struct TivaGpio {
pub sysctl_idx : u32,
pub base_addr : u32,
pub use_hpb : bool,
}
pub enum TivaGpioMode {
GpioIn,
GpioInPd,
GpioInPu,
GpioOut,
GpioOD,
GpioODPu,
}
impl TivaGpio {
pub unsafe fn init(&self) {
// bit-band access
write_bitband!(sysctl::SYSCTL_RCGCGPIO, self.sysctl_idx, 1);
// Use HPB instead of APB
write_bitband!(sysctl::SYSCTL_GPIOHBCTL, self.sysctl_idx, 1);
}
pub unsafe fn init_pin(&self, pin:u8, mode : TivaGpioMode){
match mode {
GpioOut => {
write_bitband!(memmap::GPIO_PORTF_AHB_BASE + gpio::GPIO_O_DEN, pin, 1);
write_bitband!(memmap::GPIO_PORTF_AHB_BASE + gpio::GPIO_O_DIR, pin, 1);
},
_ => {
},
}
}
pub unsafe fn write_pin(&self, pin:u8, val:u8){
hwreg!(self.base_addr + gpio::GPIO_O_DATA | (1<<(pin + 2)),
u32,
if val != 0 {1<<pin} else {0}
);
}
pub unsafe fn write_pins(&self, pin_mask:u8, val:u8){
hwreg!(self.base_addr + gpio::GPIO_O_DATA | ((pin_mask as u32)<<2),
u32,
val as u32
);
}
pub unsafe fn read_pin(&self, pin:u8) -> u8 {
return hwreg!(self.base_addr + gpio::GPIO_O_DATA | (1<<(pin + 2)),
u32
) as u8;
}
pub unsafe fn read_pins(&self, pin_mask:u8)-> u8 {
return hwreg!(self.base_addr + gpio::GPIO_O_DATA | ((pin_mask as u32)<<2),
u32
) as u8;
}
}

53
src/tiva_uart.rs

@ -0,0 +1,53 @@
use driverlib::sysctl;
use driverlib::pinmap;
use driverlib::memmap;
use driverlib::gpio;
use core::ptr;
struct TivaUartConf {
sysctl_periph_uart : u32,
sysctl_periph_gpio : u32,
gpio_base_addr_ahb : u32,
gpio_rx_pin : u32,
gpio_tx_pin: u32,
uart_base: u32,
}
const Uart0 : TivaUartConf = TivaUartConf {
sysctl_periph_uart : sysctl::SYSCTL_PERIPH_UART0,
sysctl_periph_gpio : sysctl::SYSCTL_PERIPH_GPIOA,
gpio_base_addr_ahb : memmap::GPIO_PORTA_AHB_BASE,
gpio_rx_pin : pinmap::GPIO_PA0_U0RX,
gpio_tx_pin : pinmap::GPIO_PA1_U0TX,
uart_base : memmap::UART0_BASE
};
macro_rules! config_gpio_pins {
($ahb_addr:expr, $pin :expr) => {
let pmc_index_shift : u32 = ($pin >> 8) & 0xff;
let pmc_pin_mask : u32 = $pin & 0xf;
hwreg!($ahb_addr + gpio::GPIO_O_PCTL, u32,
((hwreg!($ahb_addr + gpio::GPIO_O_PCTL, u32) &
!(0xf << pmc_index_shift)) |
(pmc_pin_mask << pmc_index_shift)));
}
}
pub unsafe fn uart_init(uart: u8, baudrate: u32) {
let uart_conf : TivaUartConf = match (uart) {
0 => Uart0,
_ => Uart0
};
sysctl::sys_ctl_peripheral_enable(uart_conf.sysctl_periph_uart);
sysctl::sys_ctl_peripheral_enable(uart_conf.sysctl_periph_gpio);
config_gpio_pins!(uart_conf.gpio_base_addr_ahb, uart_conf.gpio_rx_pin);
config_gpio_pins!(uart_conf.gpio_base_addr_ahb, uart_conf.gpio_tx_pin);
}
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