Marc Poulhiès
6 years ago
9 changed files with 771 additions and 227 deletions
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//*****************************************************************************
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//
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// hw_gpio.h - Defines and Macros for GPIO hardware.
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//
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// Copyright (c) 2005-2014 Texas Instruments Incorporated. All rights reserved.
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// Software License Agreement
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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||||
// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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// The following are defines for the GPIO register offsets.
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//
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//*****************************************************************************
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pub const GPIO_O_DATA :u32 = 0x00000000; // GPIO Data
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pub const GPIO_O_DIR :u32 = 0x00000400; // GPIO Direction
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pub const GPIO_O_IS :u32 = 0x00000404; // GPIO Interrupt Sense
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pub const GPIO_O_IBE :u32 = 0x00000408; // GPIO Interrupt Both Edges
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pub const GPIO_O_IEV :u32 = 0x0000040C; // GPIO Interrupt Event
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pub const GPIO_O_IM :u32 = 0x00000410; // GPIO Interrupt Mask
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pub const GPIO_O_RIS :u32 = 0x00000414; // GPIO Raw Interrupt Status
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pub const GPIO_O_MIS :u32 = 0x00000418; // GPIO Masked Interrupt Status
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pub const GPIO_O_ICR :u32 = 0x0000041C; // GPIO Interrupt Clear
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pub const GPIO_O_AFSEL :u32 = 0x00000420; // GPIO Alternate Function Select
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pub const GPIO_O_DR2R :u32 = 0x00000500; // GPIO 2-mA Drive Select
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pub const GPIO_O_DR4R :u32 = 0x00000504; // GPIO 4-mA Drive Select
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pub const GPIO_O_DR8R :u32 = 0x00000508; // GPIO 8-mA Drive Select
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pub const GPIO_O_ODR :u32 = 0x0000050C; // GPIO Open Drain Select
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pub const GPIO_O_PUR :u32 = 0x00000510; // GPIO Pull-Up Select
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pub const GPIO_O_PDR :u32 = 0x00000514; // GPIO Pull-Down Select
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pub const GPIO_O_SLR :u32 = 0x00000518; // GPIO Slew Rate Control Select
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pub const GPIO_O_DEN :u32 = 0x0000051C; // GPIO Digital Enable
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pub const GPIO_O_LOCK :u32 = 0x00000520; // GPIO Lock
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pub const GPIO_O_CR :u32 = 0x00000524; // GPIO Commit
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pub const GPIO_O_AMSEL :u32 = 0x00000528; // GPIO Analog Mode Select
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pub const GPIO_O_PCTL :u32 = 0x0000052C; // GPIO Port Control
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pub const GPIO_O_ADCCTL :u32 = 0x00000530; // GPIO ADC Control
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pub const GPIO_O_DMACTL :u32 = 0x00000534; // GPIO DMA Control
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pub const GPIO_O_SI :u32 = 0x00000538; // GPIO Select Interrupt
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pub const GPIO_O_DR12R :u32 = 0x0000053C; // GPIO 12-mA Drive Select
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pub const GPIO_O_WAKEPEN :u32 = 0x00000540; // GPIO Wake Pin Enable
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pub const GPIO_O_WAKELVL :u32 = 0x00000544; // GPIO Wake Level
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pub const GPIO_O_WAKESTAT :u32 = 0x00000548; // GPIO Wake Status
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pub const GPIO_O_PP :u32 = 0x00000FC0; // GPIO Peripheral Property
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pub const GPIO_O_PC :u32 = 0x00000FC4; // GPIO Peripheral Configuration
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the GPIO_O_IM register.
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//
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//*****************************************************************************
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pub const GPIO_IM_DMAIME :u32 = 0x00000100; // GPIO uDMA Done Interrupt Mask
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// Enable
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pub const GPIO_IM_GPIO_M :u32 = 0x000000FF; // GPIO Interrupt Mask Enable
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pub const GPIO_IM_GPIO_S :u32 = 0; |
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the GPIO_O_RIS register.
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//
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//*****************************************************************************
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pub const GPIO_RIS_DMARIS :u32 = 0x00000100; // GPIO uDMA Done Interrupt Raw
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// Status
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pub const GPIO_RIS_GPIO_M :u32 = 0x000000FF; // GPIO Interrupt Raw Status
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pub const GPIO_RIS_GPIO_S :u32 = 0; |
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the GPIO_O_MIS register.
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//
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//*****************************************************************************
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pub const GPIO_MIS_DMAMIS :u32 = 0x00000100; // GPIO uDMA Done Masked Interrupt
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// Status
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pub const GPIO_MIS_GPIO_M :u32 = 0x000000FF; // GPIO Masked Interrupt Status
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pub const GPIO_MIS_GPIO_S :u32 = 0; |
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the GPIO_O_ICR register.
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//
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//*****************************************************************************
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pub const GPIO_ICR_DMAIC :u32 = 0x00000100; // GPIO uDMA Interrupt Clear
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pub const GPIO_ICR_GPIO_M :u32 = 0x000000FF; // GPIO Interrupt Clear
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pub const GPIO_ICR_GPIO_S :u32 = 0; |
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the GPIO_O_LOCK register.
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//
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//*****************************************************************************
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pub const GPIO_LOCK_M :u32 = 0xFFFFFFFF; // GPIO Lock
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pub const GPIO_LOCK_UNLOCKED :u32 = 0x00000000; // The GPIOCR register is unlocked
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// and may be modified
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pub const GPIO_LOCK_LOCKED :u32 = 0x00000001; // The GPIOCR register is locked
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// and may not be modified
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pub const GPIO_LOCK_KEY :u32 = 0x4C4F434B; // Unlocks the GPIO_CR register
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the GPIO_O_SI register.
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//
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//*****************************************************************************
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pub const GPIO_SI_SUM :u32 = 0x00000001; // Summary Interrupt
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the GPIO_O_DR12R register.
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//
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//*****************************************************************************
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pub const GPIO_DR12R_DRV12_M :u32 = 0x000000FF; // Output Pad 12-mA Drive Enable
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pub const GPIO_DR12R_DRV12_12MA :u32 = 0x00000001; // The corresponding GPIO pin has
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// 12-mA drive. This encoding is
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// only valid if the GPIOPP EDE bit
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// is set and the appropriate
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// GPIOPC EDM bit field is
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// programmed to 0x3
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the GPIO_O_WAKEPEN register.
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//
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//*****************************************************************************
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pub const GPIO_WAKEPEN_WAKEP4 :u32 = 0x00000010; // P[4] Wake Enable
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the GPIO_O_WAKELVL register.
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//
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//*****************************************************************************
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pub const GPIO_WAKELVL_WAKELVL4 :u32 = 0x00000010; // P[4] Wake Level
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the GPIO_O_WAKESTAT
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// register.
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//
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//*****************************************************************************
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pub const GPIO_WAKESTAT_STAT4 :u32 = 0x00000010; // P[4] Wake Status
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the GPIO_O_PP register.
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//
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//*****************************************************************************
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pub const GPIO_PP_EDE :u32 = 0x00000001; // Extended Drive Enable
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the GPIO_O_PC register.
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//
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//*****************************************************************************
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pub const GPIO_PC_EDM7_M :u32 = 0x0000C000; // Extended Drive Mode Bit 7
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pub const GPIO_PC_EDM6_M :u32 = 0x00003000; // Extended Drive Mode Bit 6
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pub const GPIO_PC_EDM5_M :u32 = 0x00000C00; // Extended Drive Mode Bit 5
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pub const GPIO_PC_EDM4_M :u32 = 0x00000300; // Extended Drive Mode Bit 4
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pub const GPIO_PC_EDM3_M :u32 = 0x000000C0; // Extended Drive Mode Bit 3
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pub const GPIO_PC_EDM2_M :u32 = 0x00000030; // Extended Drive Mode Bit 2
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pub const GPIO_PC_EDM1_M :u32 = 0x0000000C; // Extended Drive Mode Bit 1
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pub const GPIO_PC_EDM0_M :u32 = 0x00000003; // Extended Drive Mode Bit 0
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pub const GPIO_PC_EDM0_DISABLE :u32 = 0x00000000; // Drive values of 2, 4 and 8 mA
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// are maintained. GPIO n Drive
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// Select (GPIODRnR) registers
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// function as normal
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pub const GPIO_PC_EDM0_6MA :u32 = 0x00000001; // An additional 6 mA option is
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// provided
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pub const GPIO_PC_EDM0_PLUS2MA :u32 = 0x00000003; // A 2 mA driver is always enabled;
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// setting the corresponding
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// GPIODR4R register bit adds 2 mA
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// and setting the corresponding
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// GPIODR8R of GPIODR12R register
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// bit adds an additional 4 mA
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pub const GPIO_PC_EDM7_S :u32 = 14; |
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pub const GPIO_PC_EDM6_S :u32 = 12; |
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pub const GPIO_PC_EDM5_S :u32 = 10; |
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pub const GPIO_PC_EDM4_S :u32 = 8; |
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pub const GPIO_PC_EDM3_S :u32 = 6; |
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pub const GPIO_PC_EDM2_S :u32 = 4; |
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pub const GPIO_PC_EDM1_S :u32 = 2; |
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@ -0,0 +1,146 @@
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//*****************************************************************************
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//
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// hw_memmap.h - Macros defining the memory map of the device.
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//
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// Copyright (c) 2005-2014 Texas Instruments Incorporated. All rights reserved.
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// Software License Agreement
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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// The following are defines for the base address of the memories and
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// peripherals.
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//
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//*****************************************************************************
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pub const FLASH_BASE :u32 = 0x00000000; // FLASH memory
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pub const SRAM_BASE :u32 = 0x20000000; // SRAM memory
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pub const WATCHDOG0_BASE :u32 = 0x40000000; // Watchdog0
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pub const WATCHDOG1_BASE :u32 = 0x40001000; // Watchdog1
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pub const GPIO_PORTA_BASE :u32 = 0x40004000; // GPIO Port A
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pub const GPIO_PORTB_BASE :u32 = 0x40005000; // GPIO Port B
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pub const GPIO_PORTC_BASE :u32 = 0x40006000; // GPIO Port C
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pub const GPIO_PORTD_BASE :u32 = 0x40007000; // GPIO Port D
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pub const SSI0_BASE :u32 = 0x40008000; // SSI0
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pub const SSI1_BASE :u32 = 0x40009000; // SSI1
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pub const SSI2_BASE :u32 = 0x4000A000; // SSI2
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pub const SSI3_BASE :u32 = 0x4000B000; // SSI3
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pub const UART0_BASE :u32 = 0x4000C000; // UART0
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pub const UART1_BASE :u32 = 0x4000D000; // UART1
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pub const UART2_BASE :u32 = 0x4000E000; // UART2
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pub const UART3_BASE :u32 = 0x4000F000; // UART3
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pub const UART4_BASE :u32 = 0x40010000; // UART4
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pub const UART5_BASE :u32 = 0x40011000; // UART5
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pub const UART6_BASE :u32 = 0x40012000; // UART6
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pub const UART7_BASE :u32 = 0x40013000; // UART7
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pub const I2C0_BASE :u32 = 0x40020000; // I2C0
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pub const I2C1_BASE :u32 = 0x40021000; // I2C1
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pub const I2C2_BASE :u32 = 0x40022000; // I2C2
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pub const I2C3_BASE :u32 = 0x40023000; // I2C3
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pub const GPIO_PORTE_BASE :u32 = 0x40024000; // GPIO Port E
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pub const GPIO_PORTF_BASE :u32 = 0x40025000; // GPIO Port F
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pub const GPIO_PORTG_BASE :u32 = 0x40026000; // GPIO Port G
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pub const GPIO_PORTH_BASE :u32 = 0x40027000; // GPIO Port H
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pub const PWM0_BASE :u32 = 0x40028000; // Pulse Width Modulator (PWM)
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pub const PWM1_BASE :u32 = 0x40029000; // Pulse Width Modulator (PWM)
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pub const QEI0_BASE :u32 = 0x4002C000; // QEI0
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pub const QEI1_BASE :u32 = 0x4002D000; // QEI1
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pub const TIMER0_BASE :u32 = 0x40030000; // Timer0
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pub const TIMER1_BASE :u32 = 0x40031000; // Timer1
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pub const TIMER2_BASE :u32 = 0x40032000; // Timer2
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pub const TIMER3_BASE :u32 = 0x40033000; // Timer3
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pub const TIMER4_BASE :u32 = 0x40034000; // Timer4
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pub const TIMER5_BASE :u32 = 0x40035000; // Timer5
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pub const WTIMER0_BASE :u32 = 0x40036000; // Wide Timer0
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pub const WTIMER1_BASE :u32 = 0x40037000; // Wide Timer1
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pub const ADC0_BASE :u32 = 0x40038000; // ADC0
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pub const ADC1_BASE :u32 = 0x40039000; // ADC1
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pub const COMP_BASE :u32 = 0x4003C000; // Analog comparators
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pub const GPIO_PORTJ_BASE :u32 = 0x4003D000; // GPIO Port J
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pub const CAN0_BASE :u32 = 0x40040000; // CAN0
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pub const CAN1_BASE :u32 = 0x40041000; // CAN1
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pub const WTIMER2_BASE :u32 = 0x4004C000; // Wide Timer2
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pub const WTIMER3_BASE :u32 = 0x4004D000; // Wide Timer3
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pub const WTIMER4_BASE :u32 = 0x4004E000; // Wide Timer4
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pub const WTIMER5_BASE :u32 = 0x4004F000; // Wide Timer5
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pub const USB0_BASE :u32 = 0x40050000; // USB 0 Controller
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pub const GPIO_PORTA_AHB_BASE :u32 = 0x40058000; // GPIO Port A (high speed)
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pub const GPIO_PORTB_AHB_BASE :u32 = 0x40059000; // GPIO Port B (high speed)
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pub const GPIO_PORTC_AHB_BASE :u32 = 0x4005A000; // GPIO Port C (high speed)
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pub const GPIO_PORTD_AHB_BASE :u32 = 0x4005B000; // GPIO Port D (high speed)
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pub const GPIO_PORTE_AHB_BASE :u32 = 0x4005C000; // GPIO Port E (high speed)
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pub const GPIO_PORTF_AHB_BASE :u32 = 0x4005D000; // GPIO Port F (high speed)
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pub const GPIO_PORTG_AHB_BASE :u32 = 0x4005E000; // GPIO Port G (high speed)
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pub const GPIO_PORTH_AHB_BASE :u32 = 0x4005F000; // GPIO Port H (high speed)
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pub const GPIO_PORTJ_AHB_BASE :u32 = 0x40060000; // GPIO Port J (high speed)
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pub const GPIO_PORTK_BASE :u32 = 0x40061000; // GPIO Port K
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pub const GPIO_PORTL_BASE :u32 = 0x40062000; // GPIO Port L
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pub const GPIO_PORTM_BASE :u32 = 0x40063000; // GPIO Port M
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pub const GPIO_PORTN_BASE :u32 = 0x40064000; // GPIO Port N
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pub const GPIO_PORTP_BASE :u32 = 0x40065000; // GPIO Port P
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pub const GPIO_PORTQ_BASE :u32 = 0x40066000; // GPIO Port Q
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pub const GPIO_PORTR_BASE :u32 = 0x40067000; // General-Purpose Input/Outputs
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// (GPIOs)
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pub const GPIO_PORTS_BASE :u32 = 0x40068000; // General-Purpose Input/Outputs
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// (GPIOs)
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pub const GPIO_PORTT_BASE :u32 = 0x40069000; // General-Purpose Input/Outputs
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// (GPIOs)
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pub const EEPROM_BASE :u32 = 0x400AF000; // EEPROM memory
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pub const ONEWIRE0_BASE :u32 = 0x400B6000; // 1-Wire Master Module
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pub const I2C8_BASE :u32 = 0x400B8000; // I2C8
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pub const I2C9_BASE :u32 = 0x400B9000; // I2C9
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pub const I2C4_BASE :u32 = 0x400C0000; // I2C4
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pub const I2C5_BASE :u32 = 0x400C1000; // I2C5
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pub const I2C6_BASE :u32 = 0x400C2000; // I2C6
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pub const I2C7_BASE :u32 = 0x400C3000; // I2C7
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pub const EPI0_BASE :u32 = 0x400D0000; // EPI0
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pub const TIMER6_BASE :u32 = 0x400E0000; // General-Purpose Timers
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pub const TIMER7_BASE :u32 = 0x400E1000; // General-Purpose Timers
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pub const EMAC0_BASE :u32 = 0x400EC000; // Ethernet Controller
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pub const SYSEXC_BASE :u32 = 0x400F9000; // System Exception Module
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pub const HIB_BASE :u32 = 0x400FC000; // Hibernation Module
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pub const FLASH_CTRL_BASE :u32 = 0x400FD000; // FLASH Controller
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pub const SYSCTL_BASE :u32 = 0x400FE000; // System Control
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pub const UDMA_BASE :u32 = 0x400FF000; // uDMA Controller
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pub const CCM0_BASE :u32 = 0x44030000; // Cyclical Redundancy Check (CRC)
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pub const SHAMD5_BASE :u32 = 0x44034000; // SHA/MD5 Accelerator
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pub const AES_BASE :u32 = 0x44036000; // Advance Encryption
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// Hardware-Accelerated Module
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pub const DES_BASE :u32 = 0x44038000; // Data Encryption Standard
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// Accelerator (DES)
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pub const LCD0_BASE :u32 = 0x44050000; // LCD Controller
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pub const ITM_BASE :u32 = 0xE0000000; // Instrumentation Trace Macrocell
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pub const DWT_BASE :u32 = 0xE0001000; // Data Watchpoint and Trace
|
||||
pub const FPB_BASE :u32 = 0xE0002000; // FLASH Patch and Breakpoint
|
||||
pub const NVIC_BASE :u32 = 0xE000E000; // Nested Vectored Interrupt Ctrl
|
||||
pub const TPIU_BASE :u32 = 0xE0040000; // Trace Port Interface Unit
|
||||
@ -0,0 +1,4 @@
|
||||
pub mod sysctl; |
||||
pub mod pinmap; |
||||
pub mod memmap; |
||||
pub mod gpio; |
||||
@ -0,0 +1,224 @@
|
||||
//*****************************************************************************
|
||||
//
|
||||
// pin_map.h - Mapping of peripherals to pins for all parts.
|
||||
//
|
||||
// Copyright (c) 2007-2014 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// TM4C123GH6PM Port/Pin Mapping Definitions
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
pub const GPIO_PA0_U0RX :u32 = 0x00000001; |
||||
pub const GPIO_PA0_CAN1RX :u32 = 0x00000008; |
||||
|
||||
pub const GPIO_PA1_U0TX :u32 = 0x00000401; |
||||
pub const GPIO_PA1_CAN1TX :u32 = 0x00000408; |
||||
|
||||
pub const GPIO_PA2_SSI0CLK :u32 = 0x00000802; |
||||
|
||||
pub const GPIO_PA3_SSI0FSS :u32 = 0x00000C02; |
||||
|
||||
pub const GPIO_PA4_SSI0RX :u32 = 0x00001002; |
||||
|
||||
pub const GPIO_PA5_SSI0TX :u32 = 0x00001402; |
||||
|
||||
pub const GPIO_PA6_I2C1SCL :u32 = 0x00001803; |
||||
pub const GPIO_PA6_M1PWM2 :u32 = 0x00001805; |
||||
|
||||
pub const GPIO_PA7_I2C1SDA :u32 = 0x00001C03; |
||||
pub const GPIO_PA7_M1PWM3 :u32 = 0x00001C05; |
||||
|
||||
pub const GPIO_PB0_U1RX :u32 = 0x00010001; |
||||
pub const GPIO_PB0_T2CCP0 :u32 = 0x00010007; |
||||
|
||||
pub const GPIO_PB1_U1TX :u32 = 0x00010401; |
||||
pub const GPIO_PB1_T2CCP1 :u32 = 0x00010407; |
||||
|
||||
pub const GPIO_PB2_I2C0SCL :u32 = 0x00010803; |
||||
pub const GPIO_PB2_T3CCP0 :u32 = 0x00010807; |
||||
|
||||
pub const GPIO_PB3_I2C0SDA :u32 = 0x00010C03; |
||||
pub const GPIO_PB3_T3CCP1 :u32 = 0x00010C07; |
||||
|
||||
pub const GPIO_PB4_SSI2CLK :u32 = 0x00011002; |
||||
pub const GPIO_PB4_M0PWM2 :u32 = 0x00011004; |
||||
pub const GPIO_PB4_T1CCP0 :u32 = 0x00011007; |
||||
pub const GPIO_PB4_CAN0RX :u32 = 0x00011008; |
||||
|
||||
pub const GPIO_PB5_SSI2FSS :u32 = 0x00011402; |
||||
pub const GPIO_PB5_M0PWM3 :u32 = 0x00011404; |
||||
pub const GPIO_PB5_T1CCP1 :u32 = 0x00011407; |
||||
pub const GPIO_PB5_CAN0TX :u32 = 0x00011408; |
||||
|
||||
pub const GPIO_PB6_SSI2RX :u32 = 0x00011802; |
||||
pub const GPIO_PB6_M0PWM0 :u32 = 0x00011804; |
||||
pub const GPIO_PB6_T0CCP0 :u32 = 0x00011807; |
||||
|
||||
pub const GPIO_PB7_SSI2TX :u32 = 0x00011C02; |
||||
pub const GPIO_PB7_M0PWM1 :u32 = 0x00011C04; |
||||
pub const GPIO_PB7_T0CCP1 :u32 = 0x00011C07; |
||||
|
||||
pub const GPIO_PC0_TCK :u32 = 0x00020001; |
||||
pub const GPIO_PC0_SWCLK :u32 = 0x00020001; |
||||
pub const GPIO_PC0_T4CCP0 :u32 = 0x00020007; |
||||
|
||||
pub const GPIO_PC1_TMS :u32 = 0x00020401; |
||||
pub const GPIO_PC1_SWDIO :u32 = 0x00020401; |
||||
pub const GPIO_PC1_T4CCP1 :u32 = 0x00020407; |
||||
|
||||
pub const GPIO_PC2_TDI :u32 = 0x00020801; |
||||
pub const GPIO_PC2_T5CCP0 :u32 = 0x00020807; |
||||
|
||||
pub const GPIO_PC3_SWO :u32 = 0x00020C01; |
||||
pub const GPIO_PC3_TDO :u32 = 0x00020C01; |
||||
pub const GPIO_PC3_T5CCP1 :u32 = 0x00020C07; |
||||
|
||||
pub const GPIO_PC4_U4RX :u32 = 0x00021001; |
||||
pub const GPIO_PC4_U1RX :u32 = 0x00021002; |
||||
pub const GPIO_PC4_M0PWM6 :u32 = 0x00021004; |
||||
pub const GPIO_PC4_IDX1 :u32 = 0x00021006; |
||||
pub const GPIO_PC4_WT0CCP0 :u32 = 0x00021007; |
||||
pub const GPIO_PC4_U1RTS :u32 = 0x00021008; |
||||
|
||||
pub const GPIO_PC5_U4TX :u32 = 0x00021401; |
||||
pub const GPIO_PC5_U1TX :u32 = 0x00021402; |
||||
pub const GPIO_PC5_M0PWM7 :u32 = 0x00021404; |
||||
pub const GPIO_PC5_PHA1 :u32 = 0x00021406; |
||||
pub const GPIO_PC5_WT0CCP1 :u32 = 0x00021407; |
||||
pub const GPIO_PC5_U1CTS :u32 = 0x00021408; |
||||
|
||||
pub const GPIO_PC6_U3RX :u32 = 0x00021801; |
||||
pub const GPIO_PC6_PHB1 :u32 = 0x00021806; |
||||
pub const GPIO_PC6_WT1CCP0 :u32 = 0x00021807; |
||||
pub const GPIO_PC6_USB0EPEN :u32 = 0x00021808; |
||||
|
||||
pub const GPIO_PC7_U3TX :u32 = 0x00021C01; |
||||
pub const GPIO_PC7_WT1CCP1 :u32 = 0x00021C07; |
||||
pub const GPIO_PC7_USB0PFLT :u32 = 0x00021C08; |
||||
|
||||
pub const GPIO_PD0_SSI3CLK :u32 = 0x00030001; |
||||
pub const GPIO_PD0_SSI1CLK :u32 = 0x00030002; |
||||
pub const GPIO_PD0_I2C3SCL :u32 = 0x00030003; |
||||
pub const GPIO_PD0_M0PWM6 :u32 = 0x00030004; |
||||
pub const GPIO_PD0_M1PWM0 :u32 = 0x00030005; |
||||
pub const GPIO_PD0_WT2CCP0 :u32 = 0x00030007; |
||||
|
||||
pub const GPIO_PD1_SSI3FSS :u32 = 0x00030401; |
||||
pub const GPIO_PD1_SSI1FSS :u32 = 0x00030402; |
||||
pub const GPIO_PD1_I2C3SDA :u32 = 0x00030403; |
||||
pub const GPIO_PD1_M0PWM7 :u32 = 0x00030404; |
||||
pub const GPIO_PD1_M1PWM1 :u32 = 0x00030405; |
||||
pub const GPIO_PD1_WT2CCP1 :u32 = 0x00030407; |
||||
|
||||
pub const GPIO_PD2_SSI3RX :u32 = 0x00030801; |
||||
pub const GPIO_PD2_SSI1RX :u32 = 0x00030802; |
||||
pub const GPIO_PD2_M0FAULT0 :u32 = 0x00030804; |
||||
pub const GPIO_PD2_WT3CCP0 :u32 = 0x00030807; |
||||
pub const GPIO_PD2_USB0EPEN :u32 = 0x00030808; |
||||
|
||||
pub const GPIO_PD3_SSI3TX :u32 = 0x00030C01; |
||||
pub const GPIO_PD3_SSI1TX :u32 = 0x00030C02; |
||||
pub const GPIO_PD3_IDX0 :u32 = 0x00030C06; |
||||
pub const GPIO_PD3_WT3CCP1 :u32 = 0x00030C07; |
||||
pub const GPIO_PD3_USB0PFLT :u32 = 0x00030C08; |
||||
|
||||
pub const GPIO_PD4_U6RX :u32 = 0x00031001; |
||||
pub const GPIO_PD4_WT4CCP0 :u32 = 0x00031007; |
||||
|
||||
pub const GPIO_PD5_U6TX :u32 = 0x00031401; |
||||
pub const GPIO_PD5_WT4CCP1 :u32 = 0x00031407; |
||||
|
||||
pub const GPIO_PD6_U2RX :u32 = 0x00031801; |
||||
pub const GPIO_PD6_M0FAULT0 :u32 = 0x00031804; |
||||
pub const GPIO_PD6_PHA0 :u32 = 0x00031806; |
||||
pub const GPIO_PD6_WT5CCP0 :u32 = 0x00031807; |
||||
|
||||
pub const GPIO_PD7_U2TX :u32 = 0x00031C01; |
||||
pub const GPIO_PD7_PHB0 :u32 = 0x00031C06; |
||||
pub const GPIO_PD7_WT5CCP1 :u32 = 0x00031C07; |
||||
pub const GPIO_PD7_NMI :u32 = 0x00031C08; |
||||
|
||||
pub const GPIO_PE0_U7RX :u32 = 0x00040001; |
||||
|
||||
pub const GPIO_PE1_U7TX :u32 = 0x00040401; |
||||
|
||||
pub const GPIO_PE4_U5RX :u32 = 0x00041001; |
||||
pub const GPIO_PE4_I2C2SCL :u32 = 0x00041003; |
||||
pub const GPIO_PE4_M0PWM4 :u32 = 0x00041004; |
||||
pub const GPIO_PE4_M1PWM2 :u32 = 0x00041005; |
||||
pub const GPIO_PE4_CAN0RX :u32 = 0x00041008; |
||||
|
||||
pub const GPIO_PE5_U5TX :u32 = 0x00041401; |
||||
pub const GPIO_PE5_I2C2SDA :u32 = 0x00041403; |
||||
pub const GPIO_PE5_M0PWM5 :u32 = 0x00041404; |
||||
pub const GPIO_PE5_M1PWM3 :u32 = 0x00041405; |
||||
pub const GPIO_PE5_CAN0TX :u32 = 0x00041408; |
||||
|
||||
pub const GPIO_PF0_U1RTS :u32 = 0x00050001; |
||||
pub const GPIO_PF0_SSI1RX :u32 = 0x00050002; |
||||
pub const GPIO_PF0_CAN0RX :u32 = 0x00050003; |
||||
pub const GPIO_PF0_M1PWM4 :u32 = 0x00050005; |
||||
pub const GPIO_PF0_PHA0 :u32 = 0x00050006; |
||||
pub const GPIO_PF0_T0CCP0 :u32 = 0x00050007; |
||||
pub const GPIO_PF0_NMI :u32 = 0x00050008; |
||||
pub const GPIO_PF0_C0O :u32 = 0x00050009; |
||||
|
||||
pub const GPIO_PF1_U1CTS :u32 = 0x00050401; |
||||
pub const GPIO_PF1_SSI1TX :u32 = 0x00050402; |
||||
pub const GPIO_PF1_M1PWM5 :u32 = 0x00050405; |
||||
pub const GPIO_PF1_PHB0 :u32 = 0x00050406; |
||||
pub const GPIO_PF1_T0CCP1 :u32 = 0x00050407; |
||||
pub const GPIO_PF1_C1O :u32 = 0x00050409; |
||||
pub const GPIO_PF1_TRD1 :u32 = 0x0005040E; |
||||
|
||||
pub const GPIO_PF2_SSI1CLK :u32 = 0x00050802; |
||||
pub const GPIO_PF2_M0FAULT0 :u32 = 0x00050804; |
||||
pub const GPIO_PF2_M1PWM6 :u32 = 0x00050805; |
||||
pub const GPIO_PF2_T1CCP0 :u32 = 0x00050807; |
||||
pub const GPIO_PF2_TRD0 :u32 = 0x0005080E; |
||||
|
||||
pub const GPIO_PF3_SSI1FSS :u32 = 0x00050C02; |
||||
pub const GPIO_PF3_CAN0TX :u32 = 0x00050C03; |
||||
pub const GPIO_PF3_M1PWM7 :u32 = 0x00050C05; |
||||
pub const GPIO_PF3_T1CCP1 :u32 = 0x00050C07; |
||||
pub const GPIO_PF3_TRCLK :u32 = 0x00050C0E; |
||||
|
||||
pub const GPIO_PF4_M1FAULT0 :u32 = 0x00051005; |
||||
pub const GPIO_PF4_IDX0 :u32 = 0x00051006; |
||||
pub const GPIO_PF4_T2CCP0 :u32 = 0x00051007; |
||||
pub const GPIO_PF4_USB0EPEN :u32 = 0x00051008; |
||||
@ -0,0 +1,66 @@
|
||||
use driverlib::sysctl; |
||||
use driverlib::gpio; |
||||
use driverlib::memmap; |
||||
use core::ptr; |
||||
|
||||
pub struct TivaGpio { |
||||
pub sysctl_idx : u32, |
||||
pub base_addr : u32, |
||||
pub use_hpb : bool, |
||||
} |
||||
|
||||
pub enum TivaGpioMode { |
||||
GpioIn, |
||||
GpioInPd, |
||||
GpioInPu, |
||||
GpioOut, |
||||
GpioOD, |
||||
GpioODPu, |
||||
} |
||||
|
||||
impl TivaGpio { |
||||
pub unsafe fn init(&self) { |
||||
// bit-band access
|
||||
write_bitband!(sysctl::SYSCTL_RCGCGPIO, self.sysctl_idx, 1); |
||||
|
||||
// Use HPB instead of APB
|
||||
write_bitband!(sysctl::SYSCTL_GPIOHBCTL, self.sysctl_idx, 1); |
||||
} |
||||
|
||||
pub unsafe fn init_pin(&self, pin:u8, mode : TivaGpioMode){ |
||||
match mode { |
||||
GpioOut => { |
||||
write_bitband!(memmap::GPIO_PORTF_AHB_BASE + gpio::GPIO_O_DEN, pin, 1); |
||||
write_bitband!(memmap::GPIO_PORTF_AHB_BASE + gpio::GPIO_O_DIR, pin, 1); |
||||
}, |
||||
_ => { |
||||
}, |
||||
} |
||||
} |
||||
|
||||
pub unsafe fn write_pin(&self, pin:u8, val:u8){ |
||||
hwreg!(self.base_addr + gpio::GPIO_O_DATA | (1<<(pin + 2)), |
||||
u32, |
||||
if val != 0 {1<<pin} else {0} |
||||
); |
||||
} |
||||
|
||||
pub unsafe fn write_pins(&self, pin_mask:u8, val:u8){ |
||||
hwreg!(self.base_addr + gpio::GPIO_O_DATA | ((pin_mask as u32)<<2), |
||||
u32, |
||||
val as u32 |
||||
); |
||||
} |
||||
|
||||
pub unsafe fn read_pin(&self, pin:u8) -> u8 { |
||||
return hwreg!(self.base_addr + gpio::GPIO_O_DATA | (1<<(pin + 2)), |
||||
u32 |
||||
) as u8; |
||||
} |
||||
|
||||
pub unsafe fn read_pins(&self, pin_mask:u8)-> u8 { |
||||
return hwreg!(self.base_addr + gpio::GPIO_O_DATA | ((pin_mask as u32)<<2), |
||||
u32 |
||||
) as u8; |
||||
} |
||||
} |
||||
@ -0,0 +1,53 @@
|
||||
use driverlib::sysctl; |
||||
use driverlib::pinmap; |
||||
use driverlib::memmap; |
||||
use driverlib::gpio; |
||||
|
||||
use core::ptr; |
||||
|
||||
struct TivaUartConf { |
||||
sysctl_periph_uart : u32, |
||||
sysctl_periph_gpio : u32, |
||||
gpio_base_addr_ahb : u32, |
||||
gpio_rx_pin : u32, |
||||
gpio_tx_pin: u32, |
||||
uart_base: u32, |
||||
} |
||||
|
||||
const Uart0 : TivaUartConf = TivaUartConf { |
||||
sysctl_periph_uart : sysctl::SYSCTL_PERIPH_UART0, |
||||
sysctl_periph_gpio : sysctl::SYSCTL_PERIPH_GPIOA, |
||||
gpio_base_addr_ahb : memmap::GPIO_PORTA_AHB_BASE, |
||||
gpio_rx_pin : pinmap::GPIO_PA0_U0RX, |
||||
gpio_tx_pin : pinmap::GPIO_PA1_U0TX, |
||||
uart_base : memmap::UART0_BASE |
||||
}; |
||||
|
||||
|
||||
macro_rules! config_gpio_pins { |
||||
($ahb_addr:expr, $pin :expr) => { |
||||
let pmc_index_shift : u32 = ($pin >> 8) & 0xff; |
||||
let pmc_pin_mask : u32 = $pin & 0xf; |
||||
|
||||
hwreg!($ahb_addr + gpio::GPIO_O_PCTL, u32, |
||||
((hwreg!($ahb_addr + gpio::GPIO_O_PCTL, u32) & |
||||
!(0xf << pmc_index_shift)) | |
||||
(pmc_pin_mask << pmc_index_shift))); |
||||
} |
||||
} |
||||
|
||||
pub unsafe fn uart_init(uart: u8, baudrate: u32) { |
||||
let uart_conf : TivaUartConf = match (uart) { |
||||
0 => Uart0, |
||||
_ => Uart0 |
||||
}; |
||||
|
||||
sysctl::sys_ctl_peripheral_enable(uart_conf.sysctl_periph_uart); |
||||
sysctl::sys_ctl_peripheral_enable(uart_conf.sysctl_periph_gpio); |
||||
|
||||
config_gpio_pins!(uart_conf.gpio_base_addr_ahb, uart_conf.gpio_rx_pin); |
||||
config_gpio_pins!(uart_conf.gpio_base_addr_ahb, uart_conf.gpio_tx_pin); |
||||
|
||||
|
||||
|
||||
} |
||||
Loading…
Reference in new issue