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388 lines
16 KiB
388 lines
16 KiB
#!/usr/bin/env python3
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import binascii
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import struct
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import re
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import argparse
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class GpioHook:
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def __init__(self):
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pass
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def call(self, reg, val):
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if reg[0].startswith('GPIOPCTL_'):
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print " > ",
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mask = 0xF
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pm = []
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for i in range(8):
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v = (val & (mask << (4*i)))>>4*i
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pm.append(str(v))
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print ', '.join(['pm[{}]={}'.format(idx, pmval) for idx,pmval in enumerate(pm)])
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elif reg[0].startswith('GPIOAFSEL_'):
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print " > ",
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mask = 0xFF
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val = val & mask
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afsel = []
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for i in range(8):
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v = (val & (1<<i)) != 0
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afsel.append(str(v))
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print ', '.join(['AF[{}]={}'.format(idx, afval) for idx,afval in enumerate(afsel)])
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elif reg[0].startswith('GPIOSLR_'):
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print " > ",
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mask = 0xFF
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val = val & mask
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srvals = []
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for i in range(8):
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v = (val & (1<<i)) != 0
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srvals.append(str(v))
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print ', '.join(['SlewRate[{}]={}'.format(idx, srval) for idx,srval in enumerate(srvals)])
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elif reg[0].startswith('GPIODR2R_'):
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print " > ",
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mask = 0xFF
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val = val & mask
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d2vals = []
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for i in range(8):
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v = (val & (1<<i)) != 0
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d2vals.append(str(v))
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print ', '.join(['2mA[{}]={}'.format(idx, d2val) for idx,d2val in enumerate(d2vals)])
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elif reg[0].startswith('GPIODR4R_'):
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print " > ",
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mask = 0xFF
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val = val & mask
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d4vals = []
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for i in range(8):
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v = (val & (1<<i)) != 0
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d4vals.append(str(v))
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print ', '.join(['4mA[{}]={}'.format(idx, d4val) for idx,d4val in enumerate(d4vals)])
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elif reg[0].startswith('GPIODR8R_'):
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print " > ",
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mask = 0xFF
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val = val & mask
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d8vals = []
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for i in range(8):
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v = (val & (1<<i)) != 0
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d8vals.append(str(v))
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print ', '.join(['8mA[{}]={}'.format(idx, d8val) for idx,d8val in enumerate(d8vals)])
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elif reg[0].startswith('GPIODIR_'):
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print ' > ',
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mask = 0xFF
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val = val & mask
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dirvals = []
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for i in range(8):
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v = (val & (1<<i)) != 0
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dirvals.append('OUT' if v else 'IN')
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print ', '.join(['Dir[{}]={}'.format(idx, dirval) for idx,dirval in enumerate(dirvals)])
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class RCC2Hook:
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def call(self, reg, val):
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usercc2 = (val &(1<<32))!=0
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print ' > [USERCC2] Use RCC2: {}'.format(usercc2)
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if not usercc2:
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return
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class RCCHook:
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def call(self, reg, val):
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print ' > Main oscillator {}'.format('DISABLED'if val & 0x1 else 'ENABLED')
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oscsrc = (val & (0x3<<4))>>4
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oscvals = {0:'[MOSC] Main Oscillator',
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1:'[PIOSC] Precision internal oscillator',
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2:'[PIOSC/4] Precision internal oscillator/4',
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3:'[LFIOSC] Low-freq internal oscillator/4',
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}
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print ' > Oscillator source: {}'.format(oscvals[oscsrc])
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xtalvals = {
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0x6:('4', 'Reserved'),
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0x7:('4.096', 'Reserved'),
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0x8:('4.9152', 'Reserved'),
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0x9:('5','5'),
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0xA:('5.12', '5.12'),
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0xB:('6', '6'),
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0xC:('6.144', '6.144'),
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0xD:('7.3728', '7.3728'),
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0xE:('8', '8'),
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0xF:('8.192', '8.192'),
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0x10:('10.0', '10.0'),
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0x11:('12.0', '12.0'),
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0x12:('12.288', '12.288'),
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0x13:('13.56', '13.56'),
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0x14:('14.31818', '14.31818'),
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0x15:('16.0', '16.0'),
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0x16:('16.364', '16.364'),
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0x17:('18.0', '18.0'),
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0x18:('20.0', '20.0'),
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0x19:('24.0', '24.0'),
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0x1A:('25.0', '25.0'),
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}
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xtalval = (val & (0x1F<<6))>>6
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print ' > [XTAL] Crystal value {} Mhz'.format(xtalvals[xtalval][0])
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pllbypass = (val & (1<<11)) != 0
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print ' > [BYPASS] The system clock is {} divided by SYSDIV'.format('derived from the OSC' if pllbypass else 'the PLL output')
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pllpwrdown = (val & (1<<13)) != 0
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print ' > PLL is {}'.format('powered down' if pllpwrdown else 'operating normally')
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pwmdiv = (val & (0x7<<17))>>17
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print ' > [PWMDIV] PWM Unit Clock Divisor is {}'.format(2**(pwmdiv+1) if pwmdiv < 5 else '64')
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pwmclockdiv = (val & (1<<20)) != 0
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print ' > [USEPWMDIV] PWM Clock Divisor : {} is the source for PWM'.format('The PWM clock divider' if pwmclockdiv else 'The system clock divider')
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usesysdiv = (val & (1<<22)) != 0
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print ' > [USESYSDIV] Enable System Clock Divider: {}'.format('system clock divider is used (forced when PLL is selected as the source)' if usesysdiv else 'The system clock is used undivided')
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sysdiv = (val & (0xF<<23))>>23
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print ' > [SYSDIV] System Clock Divisor: {}'.format(sysdiv+1)
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if not pllbypass:
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print ' > {}'.format({
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0x0 : 'reserved',
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0x1 : 'reserved',
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0x2 : '66.67 Mhz',
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0x3 : '50 Mhz',
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0x4 : '40 Mhz',
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0x5 : '33.33 Mhz',
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0x6 : '28.57 Mhz',
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0x7 : '25 Mhz',
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0x8 : '22.22 Mhz',
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0x9 : '20 Mhz',
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0xa : '18.18 Mhz',
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0xb : '16.67 Mhz',
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0xc : '15.38 Mhz',
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0xd : '14.29 Mhz',
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0xe : '13.33 Mhz',
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0xf : '12.5 Mhz',
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}[sysdiv])
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acg = (val & (1<<27)) != 0
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print ' > [ACG] Auto Clock Gating: {}'.format('SCGCn/DCGCn registers are used' if acg else 'RCGCn registers are used')
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class UartHook:
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def __init__(self, baudrate = 115200):
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self.ibrd = None
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self.fbrd = None
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self.baudrate = baudrate
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def call(self, reg, val):
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if reg[0].startswith('UARTIBRD_'):
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self.ibrd = val
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elif reg[0].startswith('UARTFBRD_'):
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self.fbrd = val
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print " > ",
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print "UART clock is {} for baudrate {}".format(
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((2 * (64 * self.ibrd + self.fbrd)-1) * self.baudrate)/8,
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self.baudrate)
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elif reg[0].startswith('UARTLCHR_'):
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print ' > BRK: {}'.format('send' if (val & 0x1) else 'normal' )
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print ' > Parity [PEN]: {}'.format('enabled' if (val & 0x2) else 'disabled')
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print ' > Even parity select [EPS]: {}'.format('enabled' if (val & 0x4) else 'disabled')
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print ' > 2 stop bits [STP2]: {}'.format('enabled' if (val & (1<<3)) else 'disabled')
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print ' > Enable FIFO [FEN]: {}'.format('enabled' if (val & (1<<4)) else 'disabled')
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wlen = (val & (0x3<<5))>>5
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print ' > Word len [WLEN]: {} bits'.format(wlen + 5)
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print ' > Stick Parity Select [SPS]: {}'.format('checked...' if (val & (1<<7)) else 'disabled')
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elif reg[0].startswith('UARTCTL_'):
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print ' > UART Enable [UARTEN]: {}'.format((val & 0x1) != 0)
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print ' > UART Sir Enable [SIREN]: {}'.format((val & 0x2) != 0)
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print ' > UART Sir LowPower Mode [SIRLP]: {}'.format('enabled' if ((val & (1<<2)) != 0) else 'disabled')
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print ' > ISO 7816 support [SMART]: {}'.format('smart mode' if ((val & (0x1<<3)) != 0) else 'normal')
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print ' > End of Transmission [EOT]: TXRIS set when {}'.format('all transmitted' if (val & (1<<4)) else 'UARTIFLS conditions...' )
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print ' > High Speed enable [HSE]: sys clock divided by {}'.format(8 if (val&(1<<5)) else 16)
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print ' > Loop Back Enable [LBE]: {}'.format('enabled' if (val & (1<<7)) else 'disabled')
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print ' > UART Transmit Enable [TXE]: {}'.format('enabled' if (val & (1<<8)) else 'disabled')
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print ' > UART Receive Enable [RXE]: {}'.format('enabled' if (val & (1<<9)) else 'disabled')
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rtsen = (val & (1<<14)) != 0
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print ' > Request to send [RTS]: {}'.format('set' if (val & (1<<9)) and not rtsen else 'clear' if (val & (1<<9)) and not rtsen else 'discarded' )
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print ' > Enable Request to Send [RTSEN]: Hardware flow contrlol is {}'.format('enable' if rtsen else 'disabled')
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print ' > Enable Clear to Send [CTSEN]: CTS hardware flow is {}'.format('enable' if (val & (1<<15)) else 'disabled')
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class GpioHbctlHook:
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def call(self, reg, val):
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print " > Use HPB : ",
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mask = 0xFF
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val = val & mask
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hpb_vals = []
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ports = ['PORTA', 'PORTB', 'PORTC', 'PORTD',
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'PORTE', 'PORTF']
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for i in range(8):
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v = (val & (1<<i)) != 0
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hpb_vals.append(str(v))
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print ', '.join(['{}: {}'.format(prt, hpb_val) for prt,hpb_val in zip(ports, hpb_vals)])
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parser = argparse.ArgumentParser(description='Parse command for reading Tiva status.')
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parser.add_argument("-r", '--register', action='append', help='a regexp for matching some registers')
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parser.add_argument('--use-apb', action='store_true', help='use legacy APB instead of AHB for GPIO registers')
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class ReadTiva (gdb.Command):
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"""Read something."""
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def __init__ (self):
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super (ReadTiva, self).__init__ ("read-tiva", gdb.COMMAND_USER)
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def single_read(self, reg):
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name = reg[0]
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addr = reg[1]
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size = reg[2]
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hook = reg[3]
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inf = gdb.selected_inferior ()
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m = inf.read_memory (addr, size)
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val = struct.unpack('i', m)[0]
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print "{} : 0x{:08X} @ 0x{:08X}".format(name, val, addr)
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if hook:
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hook.call(reg,val)
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def invoke (self, arg, from_tty):
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args = gdb.string_to_argv(arg)
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parsed_args = parser.parse_args(args)
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uart0hook = UartHook()
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gpiohook = GpioHook()
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rcchook = RCCHook()
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rcc2hook = RCC2Hook()
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gpiohbctlhook = GpioHbctlHook()
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all_regs = [
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('RCC', 0x400FE060, 4, rcchook),
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('RCC2', 0x400FE070, 4, rcc2hook),
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('RCGCUART', 0x400FE618, 4, None),
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('RCGCGPIO', 0x400FE608, 4, None),
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('UARTIBRD_0', 0x4000C024, 4, uart0hook),
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('UARTFBRD_0', 0x4000C028, 4, uart0hook),
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('UARTLCHR_0', 0x4000C02C, 4, uart0hook),
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('UARTCTL_0', 0x4000C030, 4, uart0hook),
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('GPIOHBCTL', 0x400FE06C, 4, gpiohbctlhook),
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]
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if parsed_args.use_apb:
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all_regs += [
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('GPIODIR_PORTA', 0x40004400, 4, gpiohook),
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('GPIOAFSEL_PORTA', 0x40004420, 4, gpiohook),
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('GPIOPCTL_PORTA', 0x4000452C, 4, gpiohook),
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('GPIOSLR_PORTA', 0x40004518, 4, gpiohook),
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('GPIODR2R_PORTA', 0x40004500, 4, gpiohook),
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('GPIODR4R_PORTA', 0x40004504, 4, gpiohook),
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('GPIODR8R_PORTA', 0x40004508, 4, gpiohook),
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('GPIODIR_PORTB', 0x40005400, 4, gpiohook),
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('GPIOAFSEL_PORTB', 0x40005420, 4, gpiohook),
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('GPIOPCTL_PORTB', 0x4000552C, 4, gpiohook),
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('GPIOSLR_PORTB', 0x40005518, 4, gpiohook),
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('GPIODR2R_PORTB', 0x40005500, 4, gpiohook),
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('GPIODR4R_PORTB', 0x40005504, 4, gpiohook),
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('GPIODR8R_PORTB', 0x40005508, 4, gpiohook),
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('GPIODIR_PORTC', 0x40006400, 4, gpiohook),
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('GPIOAFSEL_PORTC', 0x40006420, 4, gpiohook),
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('GPIOPCTL_PORTC', 0x4000652C, 4, gpiohook),
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('GPIOSLR_PORTC', 0x40006518, 4, gpiohook),
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('GPIODR2R_PORTC', 0x40006500, 4, gpiohook),
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('GPIODR4R_PORTC', 0x40006504, 4, gpiohook),
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('GPIODR8R_PORTC', 0x40006508, 4, gpiohook),
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('GPIODIR_PORTD', 0x40007400, 4, gpiohook),
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('GPIOAFSEL_PORTD', 0x40007420, 4, gpiohook),
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('GPIOPCTL_PORTD', 0x4000752C, 4, gpiohook),
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('GPIOSLR_PORTD', 0x40007518, 4, gpiohook),
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('GPIODR2R_PORTD', 0x40007500, 4, gpiohook),
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('GPIODR4R_PORTD', 0x40007504, 4, gpiohook),
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('GPIODR8R_PORTD', 0x40007508, 4, gpiohook),
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('GPIODIR_PORTE', 0x40024400, 4, gpiohook),
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('GPIOAFSEL_PORTE', 0x40024420, 4, gpiohook),
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('GPIOPCTL_PORTE', 0x4002452C, 4, gpiohook),
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('GPIOSLR_PORTE', 0x40024518, 4, gpiohook),
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('GPIODR2R_PORTE', 0x40024500, 4, gpiohook),
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('GPIODR4R_PORTE', 0x40024504, 4, gpiohook),
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('GPIODR8R_PORTE', 0x40024508, 4, gpiohook),
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('GPIODIR_PORTF', 0x40025400, 4, gpiohook),
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('GPIOAFSEL_PORTF', 0x40025420, 4, gpiohook),
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('GPIOPCTL_PORTF', 0x4002552C, 4, gpiohook),
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('GPIOSLR_PORTF', 0x40025518, 4, gpiohook),
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('GPIODR2R_PORTF', 0x40025500, 4, gpiohook),
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('GPIODR4R_PORTF', 0x40025504, 4, gpiohook),
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('GPIODR8R_PORTF', 0x40025508, 4, gpiohook),
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]
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else:
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all_regs += [
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('GPIODIR_PORTA', 0x40058400, 4, gpiohook),
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('GPIOAFSEL_PORTA', 0x40058420, 4, gpiohook),
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('GPIOPCTL_PORTA', 0x4005852C, 4, gpiohook),
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('GPIOSLR_PORTA', 0x40058518, 4, gpiohook),
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('GPIODR2R_PORTA', 0x40058500, 4, gpiohook),
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('GPIODR4R_PORTA', 0x40058504, 4, gpiohook),
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('GPIODR8R_PORTA', 0x40058508, 4, gpiohook),
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('GPIODIR_PORTB', 0x40059400, 4, gpiohook),
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('GPIOAFSEL_PORTB', 0x40059420, 4, gpiohook),
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('GPIOPCTL_PORTB', 0x4005952C, 4, gpiohook),
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('GPIOSLR_PORTB', 0x40059518, 4, gpiohook),
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('GPIODR2R_PORTB', 0x40059500, 4, gpiohook),
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('GPIODR4R_PORTB', 0x40059504, 4, gpiohook),
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('GPIODR8R_PORTB', 0x40059508, 4, gpiohook),
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('GPIODIR_PORTC', 0x4005A400, 4, gpiohook),
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('GPIOAFSEL_PORTC', 0x4005A420, 4, gpiohook),
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('GPIOPCTL_PORTC', 0x4005A52C, 4, gpiohook),
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('GPIOSLR_PORTC', 0x4005A518, 4, gpiohook),
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('GPIODR2R_PORTC', 0x4005A500, 4, gpiohook),
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('GPIODR4R_PORTC', 0x4005A504, 4, gpiohook),
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('GPIODR8R_PORTC', 0x4005A508, 4, gpiohook),
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('GPIODIR_PORTD', 0x4005B400, 4, gpiohook),
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('GPIOAFSEL_PORTD', 0x4005B420, 4, gpiohook),
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('GPIOPCTL_PORTD', 0x4005B52C, 4, gpiohook),
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('GPIOSLR_PORTD', 0x4005B518, 4, gpiohook),
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('GPIODR2R_PORTD', 0x4005B500, 4, gpiohook),
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('GPIODR4R_PORTD', 0x4005B504, 4, gpiohook),
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('GPIODR8R_PORTD', 0x4005B508, 4, gpiohook),
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('GPIODIR_PORTE', 0x4005C400, 4, gpiohook),
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('GPIOAFSEL_PORTE', 0x4005C420, 4, gpiohook),
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('GPIOPCTL_PORTE', 0x4005C52C, 4, gpiohook),
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('GPIOSLR_PORTE', 0x4005C518, 4, gpiohook),
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('GPIODR2R_PORTE', 0x4005C500, 4, gpiohook),
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('GPIODR4R_PORTE', 0x4005C504, 4, gpiohook),
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('GPIODR8R_PORTE', 0x4005C508, 4, gpiohook),
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('GPIODIR_PORTF', 0x4005D400, 4, gpiohook),
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('GPIOAFSEL_PORTF', 0x4005D420, 4, gpiohook),
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('GPIOPCTL_PORTF', 0x4005D52C, 4, gpiohook),
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('GPIOSLR_PORTF', 0x4005D518, 4, gpiohook),
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('GPIODR2R_PORTF', 0x4005D500, 4, gpiohook),
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('GPIODR4R_PORTF', 0x4005D504, 4, gpiohook),
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('GPIODR8R_PORTF', 0x4005D508, 4, gpiohook),
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]
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reg_to_print = all_regs
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if parsed_args.register:
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reg_to_print = []
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for regex in [re.compile(x) for x in parsed_args.register]:
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filtered = [x for x in all_regs]
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reg_to_print += filter(lambda x: regex.match(x[0]), all_regs)
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for reg in reg_to_print:
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self.single_read(reg)
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ReadTiva ()
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